ISL9N306AP3 FAIRCHILD | Alldatasheet
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Fast switching r DS(ON) = 0.0052Ω (Typ), VGS = 10V r DS(ON) = 0.0085Ω (Typ), VGS = 4.5V Q g (Typ) = 30nC, VGS = 5V Q gd (Typ) = 11nC C ISS (Typ) = 3400pF MOSFET Maximum Ratings TA = 25°C unless otherwise noted Thermal Characteristics Package Marking and Ordering Information Symbol Parameter Ratings Units VDSS Drain to Source Voltage 30 V VGS Gate to Source Voltage ±20 V ID Drain Current
75 AContinuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 4.5V) 61 A Continuous (TC = 25oC, VGS = V, RθJC = 43oC/W) 18 A Pulsed Figure 4 A PD Power dissipation Derate above 25oC 125 0.83 W W/oC TJ, TSTG Operating and Storage Temperature -55 to 175 oC R θJC Thermal Resistance Junction to Case TO-220, TO-263 1.2 oC/W R θJA Thermal Resistance Junction to Ambient TO-220, TO-263 62 oC/W R θJA Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 43 oC/W Device Marking Device Package Reel Size Tape Width Quantity N306AS ISL9N306AS3ST TO-263AB 330mm 24mm 800 units N306AP ISL9N306AP3 TO-220AB Tube N/A 50 units D G S TO-263AB TO-220AB DRAIN SOURCE GATE DRAIN (FLANGE)
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N306AP3/ISL9N306AS3ST Electrical Characteristics TA = 25°C unless otherwise noted Off Characteristics On Characteristics Dynamic Characteristics Switching Characteristics (VGS = 4.5V) Switching Characteristics (VGS = 10V) Unclamped Inductive Switching Drain-Source Diode Characteristics Symbol Parameter Test Conditions Min Typ Max Units BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V IDSS Zero Gate Voltage Drain Current VDS = 25V - - 1 µAVGS = 0V T C = 150o - - 250 IGSS Gate to Source Leakage Current V GS = ±20V - - ±100 nA VGS(TH) Gate to Source Threshold Voltage V GS = VDS , ID = 250µA1 - 3 V C ISS Input Capacitance VDS = 15V, VGS = 0V, f = 1MHz -3 4 0 0- p F C OSS Output Capacitance - 650 - pF C RSS Reverse Transfer Capacitance - 300 - pF Qg(TOT) Total Gate Charge at 10V V GS = 0V to 10V VDD = 15V ID = 61A Ig = 1.0mA 60 90 nC Q g(5) Total Gate Charge at 5V V GS = 0V to 5V - 30 45 nC Q g(TH) Threshold Gate Charge V GS = 0V to 1V - 3.0 4.5 nC Q gs Gate to Source Gate Charge - 10 - nC Q gd Gate to Drain “Miller” Charge - 11 - nC tON Turn-On Time VDD = 15V, ID = 18A VGS = 4.5V, RGS = 4.3Ω - - 131 ns td(ON) Turn-On Delay Time - 16 - ns tr Rise Time - 70 - ns td(OFF) Turn-Off Delay Time - 34 - ns tf Fall Time - 30 - ns tOFF Turn-Off Time - - 97 ns tON Turn-On Time VDD = 15V, ID = 18A VGS = 10V, RGS = 4.3Ω - - 80 ns td(ON) Turn-On Delay Time - 10 - ns tr Rise Time - 43 - ns td(OFF) Turn-Off Delay Time - 62 - ns tf Fall Time - 29 - ns tOFF Turn-Off Time - - 137 ns tAV Avalanche Time I D = 3.6A, L = 3mH 240 - - µs VSD Source to Drain Diode Voltage ISD = 61A - - 1.25 V ISD = 25A - - 1.0 V trr Reverse Recovery Time I SD = 61A, dISD /dt = 100A/µs- - 3 5 n s Q RR Reverse Recovered Charge I SD = 61A, dISD /dt = 100A/µs- - 3 0 n C
must be reviewed to ensure that TJM is never exceeded. serves as the basis for establishing the rating of the part.
- Mounting pad area onto which the device is attached and
- The number of copper layers and the thickness of the
- The use of external heat sinks.
- Air flow and board orientation.
- For non steady state applications, the pulse width, the
the board and the environment they are in. maximum transient thermal impedance curve. Figure 21. Thermal Resistance vs Mounting
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N306AP3/ISL9N306AS3ST .SUBCKT ISL9N306A 2 1 3 ;rev May 2001 CA 12 8 2.0e-9 CB 15 14 2.3e-9 CIN 6 8 3e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 35.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 4.58e-9 LSOURCE 3 7 1.47e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1e-3 RGATE 9 20 2.69 RLDRAIN 2 5 10 RLGATE 1 9 45.8 RLSOURCE 3 7 14.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*275),5))} 0.51) .MODEL DBREAKMOD D (RS = 1.7e- 1TRS1 = 1e- 3TRS2 = -8.9e-6) .MODEL DPLCAPMOD D (CJO = 11.5e-1 0IS = 1e-3 0N = 10 M = 0.46) .MODEL MMEDMOD NMOS (VTO = 1.7 KP = 9 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.69) .MODEL MSTROMOD NMOS (VTO = 2.1 KP = 100 IS = 1e-30 N= 10 TOX = 1 L = 1u W = 1u) .MODEL RBREAKMOD RES (TC1 = 1e- 3TC2 = -7e-7) .MODEL RDRAINMOD RES (TC1 = 1.2e- 2TC2 = 3.0e-5) .MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.6e-3 TC2 = -7.5e-6) .MODEL RVTEMPMOD RES (TC1 = -1.8e- 3TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF= -0.8) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.8 VOFF= -4.0) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.3 VOFF= 0.2) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.3) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. + - + - 8 + RBREAK RVTEMP VBAT RVTHRES IT 17 18 S1A S1B S2A S2B CA CB EGS EDS MWEAK EBREAK DBODY RSOURCE SOURCE 7 3 LSOURCE RLSOURCE CIN RDRAIN EVTHRES 1621 MMED MSTRO DRAIN LDRAIN RLDRAIN DBREAK DPLCAP ESLC RSLC1 RSLC2 GATE RGATE EVTEMP ESG LGATE RLGATE
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N306AP3/ISL9N306AS3ST REV May 2001 template ISL9N306A n2,n1,n3 electrical n2,n1,n3 var i iscl dp..model dbreakmod = (rs =0.17, trs1 = 1e-3, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 11.5e-10, isl=10e-30, nl=10, m=0.46) m..model mmedmod = (type=_n, vto = 1.7, kp=9, is=1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.1, kp = 100, is = 1e-30, tox = 1) c.ca n12 n8 = 2.0e-9 c.cb n15 n14 = 2.3e-9 c.cin n6 n8 = 3e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 4.58e-9 l.lsource n3 n7 = 1.47e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -7e-7 res.rdrain n50 n16 = 1e-3, tc1 = 1.2e-2, tc2 = 3.0e-5 res.rgate n9 n20 = 2.69 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 45.8 res.rlsource n3 n7 = 14.7 res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.5e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = -1e-6 res.rvthres n22 n8 = 1, tc1 = -2.6e-3, tc2 = -7.5e-6 spe.ebreak n11 n7 n17 n18 = 35.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/275))** 5)) + - + - 8 + RBREAK RVTEMP VBAT RVTHRES IT 17 18 S1A S1B S2A S2B CA CB EGS EDS MWEAK EBREAK DBODY RSOURCE SOUR CE 7 3 LSOURCE RLSOURCE CIN RDRAIN EVTHRES 1621 MMED MSTRO DRAIN LDRAIN RLDRAIN DBREAK DPLCAP ISCL RSLC1 RSLC2 GATE RGATE EVTEMP ESG LGATE RLGATE
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002 ISL9N306AP3/ISL9N306AS3ST SPICE Thermal Model REV May 2001 ISL9N306AT CTHERM1 th 6 2.7e-4 CTHERM2 6 5 3.9e-3 CTHERM3 5 4 4.2e-3 CTHERM4 4 3 4.8e-3 CTHERM5 3 2 1.9e-2 CTHERM6 2 tl 5.9e-2 RTHERM1 th 6 1.0e-3 RTHERM2 6 5 4.8e-3 RTHERM3 5 4 4.5e-2 RTHERM4 4 3 2.6e-1 RTHERM5 3 2 3.1e-1 RTHERM6 2 tl 3.4e-1 SABER Thermal Model SABER thermal model ISL9N306AT template thermal_model th tl thermal_c th, tl ctherm.ctherm1 th 6 = 2.7e-4 ctherm.ctherm2 6 5 = 3.9e-3 ctherm.ctherm3 5 4 = 4.2e-3 ctherm.ctherm4 4 3 = 4.8e-3 ctherm.ctherm5 3 2 = 1.9e-2 ctherm.ctherm6 2 tl = 5.9e-2 rtherm.rtherm1 th 6 = 1.0e-3 rtherm.rtherm2 6 5 = 4.8e-3 rtherm.rtherm3 5 4 = 4.5e-2 rtherm.rtherm4 4 3 = 2.6e-1 rtherm.rtherm5 3 2 = 3.1e-1 rtherm.rtherm6 2 tl = 3.4e-1 RTHERM4 RTHERM6 RTHERM5 RTHERM3 RTHERM2 RTHERM1 CTHERM4 CTHERM6 CTHERM5 CTHERM3 CTHERM2 CTHERM1 tl th JUNCTION CASE
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