N28B

DP8570A_11 TI1 | Alldatasheet

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DP8570A Timer Clock Peripheral (TCP) Literature Number: SNAS557

DP8570A Timer Clock Peripheral (TCP) May 1993 DP8570A Timer Clock Peripheral (TCP) General Description The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS tech- nology to provide low standby power in battery back-up en- vironments. The circuit’s architecture is such that it looks like a contiguous block of memory or I/O ports. The address space is organized as 2 software selectable pages of 32 bytes. This includes the Control Registers, the Clock Coun- ters, the Alarm Compare RAM, the Timers and their data RAM, and the Time Save RAM. Any of the RAM locations that are not being used for their intended purpose may be used as general purpose CMOS RAM. Time and date are maintained from 1/100 of a second to year and leap year in a BCD format, 12 or 24 hour modes. Day of week, day of month and day of year counters are provided. Time is controlled by an on-chip crystal oscillator requiring only the addition of the crystal and two capacitors. The choice of crystal frequency is program selectable. Two independent multifunction 10 MHz 16-bit timers are provided. These timers operate in four modes. Each has its own prescaler and can select any of 8 possible clock inputs. Thus, by programming the input clocks and the timer coun- ter values a very wide range of timing durations can be achieved. The range is from about 400 ns (4.915 MHz oscil- lator) to 65,535 seconds (18 hrs., 12 min.). Power failure logic and control functions have been integrat- ed on chip. This logic is used by the TCP to issue a power fail interrupt, and lock out the mp interface. The time power fails may be logged into RAM automatically when V BB l VCC. Additionally, two supply pins are provided. When V BB l VCC, internal circuitry will automatically switch from the main supply to the battery supply. Status bits are provided to indi- cate initial application of battery power, system power, and low battery detect. (Continued)

Features

Y Full function real time clock/calendar Ð 12/24 hour mode timekeeping Ð Day of week and day of years counters Ð Four selectable oscillator frequencies Ð Parallel Resonant Oscillator Y Two 16-bit timers Ð 10 MHz external clock frequency Ð Programmable multi-function output Ð Flexible re-trigger facilities Y Power fail features Ð Internal power supply switch to external battery Ð Power Supply Bus glitch protection Ð Automatic log of time into RAM at power failure Y On-chip interrupt structure Ð Periodic, alarm, timer and power fail interrupts Y Up to 44 bytes of CMOS RAM Y INTR/MFO/T1 pins programmable High/Low and push- pull or open drain Block Diagram TL/F/8638–1 FIGURE 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2 ) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (V CC) b0.5V to a7.0V DC Input Voltage (V IN) b0.5V to V CC a0.5V DC Output Voltage (V OUT) b0.5V to V CC a 0.5V Storage Temperature Range b65§Ct o a150§C Power Dissipation (PD) 500 mW Lead Temperature (Soldering, 10 sec.) 260 Operation Conditions Min Max Unit Supply Voltage (V CC) (Note 3) 4.5 5.5 V Supply Voltage (V BB) (Note 3) 2.2 V CCb0.4 V DC Input or Output Voltage 0.0 V CC V(VIN,V OUT) Operation Temperature (T A) b40 a85 §C Electr-Static Discharge Rating TBD 1 kV Transistor Count 15,200 Typical Values i JA DIP Board e 45§C/W Socket e 50§C/W iJA PLCC Board e 77§C/W Socket e 85§C/W VCC e 5V g10%, V BB e 3V, V PFAIL l VIH,C L e 100 pF (unless otherwise specified) Symbol Parameter Conditions Min Max Units VIH High Level Input Voltage Any Inputs Except OSC IN, 2.0 V (Note 4) OSC IN with External Clock V BB b0.1 V VIL Low Level Input Voltage All Inputs Except OSC IN 0.8 V OSC IN with External Clock 0.1 V VOH High Level Output Voltage I OUT eb 20 mAV CC b0.1 V (Excluding OSC OUT) I OUT eb 4.0 mA 3.5 V VOL Low Level Output Voltage I OUT e 20 mA 0.1 V (Excluding OSC OUT) I OUT e 4.0 mA 0.25 V IIN Input Current (Except OSC IN) V IN e VCC or GND g1.0 mA IOZ Output TRI-STATE É Current V OUT e VCC or GND g5.0 mA ILKG Output High Leakage Current V OUT e VCC or GND g5.0 mAT1, MFO, INTR Pins Outputs Open Drain ICC Quiescent Supply Current F OSC e 32.768 kHz (Note 7) V IN e VCC or GND (Note 5) 260 mA VIN e VCC or GND (Note 6) 1.0 mA VIN e VIH or V IL (Note 6) 12.0 mA FOSC e 4.194304 MHz or

4.9152 MHz

VIN e VCC or GND (Note 6) 8 mA VIN e VIH or V IL (Note 6) 20 mA ICC Quiescent Supply Current V BB e GND (Single Supply Mode) V IN e VCC or GND (Note 7) F OSC e 32.768 kHz 80 mA FOSC e 4.9152 MHz or 7.5 mA

4.194304 MHz

IBB Standby Mode Battery V CC e GND Supply Current OSC OUT e Open Circuit, (Note 8) Other Pins e GND FOSC e 32.768 kHz 10 mA FOSC e 4.9152 MHz or 400 mA IBLK Battery Supply Leakage 2.2V s VBB s 4.0V Other Pins at GND VCC e GND, V BB e 4.0V 1.5 mA VCC e 5.5V, V BB e 2.2V b5 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Single Supply Mode: Data retention voltage is 2.2V min. In single Supply Mode (Power connected to V CC pin) 4.5V s VCC s 5.5V. Note 4: This parameter (V IH) is not tested on all pins at the same time. Note 5: This specification tests I CC with all power fail circuitry disabled, by setting D7 of Interrupt Control Register 1 to 0. Note 6: This specification tests I CC with all power fail circuitry enabled, by setting D7 of Interrupt Control Register 1 to 1. Note 7: This specification is tested with both the timers and OSC IN driven by a signal generator. Contents of the Test Register e 00(H), the MFO pin is not configured as buffered oscillator out and MFO, T1, INTR, are configured as open drain. Note 8: This specification is tested with both the timers off, and only OSC IN is driven by a signal generator. Contents of the Test Register e 00(H) and the MFO pin is not configured as buffered oscillator out.

VCC e 5V g10%, V BB e 3V, V PFAIL l VIH,C L e 100 pF (unless otherwise specified) Symbol Parameter Min Max Units READ TIMING tAR Address Valid Prior to Read Strobe 20 ns tRW Read Strobe Width (Note 9) 80 ns tCD Chip Select to Data Valid Time 80 ns tRAH Address Hold after Read (Note 10) 3 ns tRD Read Strobe to Valid Data 70 ns tDZ Read or Chip Select to TRI-STATE 60 ns tRCH Chip Select Hold after Read Strobe 0 ns tDS Minimum Inactive Time between Read or Write Accesses 50 ns WRITE TIMING tAW Address Valid before Write Strobe 20 ns tWAH Address Hold after Write Strobe (Note 10) 3 ns tCW Chip Select to End of Write Strobe 90 ns tWW Write Strobe Width (Note 11) 80 ns tDW Data Valid to End of Write Strobe 50 ns tWDH Data Hold after Write Strobe (Note 10) 3 ns tWCH Chip Select Hold after Write Strobe 0 ns TIMER 0/TIMER 1 TIMING FTCK Input Frequency Range DC 10 MHz tCK Propagation Delay Clock to Output Þ 120 ns tGO Propagation Delay G0 to G1 100 nsto Timer Output (Note 12) O tPGW Pulse Width G0 or G1 É (Note 12) 25 ns tGS Setup Time, G0, G1 to TCK (Note 13) 100 ns INTERRUPT TIMING tROLL Clock Rollover to INTR Out is Typically 16.5 ms Note 9: Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when both signals are low and terminates when either signal returns high. Note 10: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels. Note 11: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when both signals are low and terminates when either signal returns high. Note 12: Timers in Mode 3. Note 13: Guaranteed by design, not production tested. This limit is not used to calculate outgoing quality levels. AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise and Fall Times 6 ns (10%–90%) Input and Output 1.3VReference Levels TRI-STATE Reference Active High a0.5V Levels (Note 15) Active Low b0.5V Note 14: CL e 100 pF, includes jig and scope capacitance. Note 15: S1 e VCC for active low to high impedance measurements. S1 e GND for active high to high impedance measurements. S1 e open for all other timing measurements. Capacitance (TA e 25§C, f e 1 MHz) Symbol Parameter Typ Units(Note 16) CIN Input Capacitance 5 pF COUT Output Capacitance 7 pF Note 16: This parameter is not 100% tested. Note 17: Output rise and fall times 25 ns max (10%–90%) with 100 pF load. TL/F/8638–23

TL/F/8638–24 Write Timing Diagram TL/F/8638–25

General Description (Continued) The DP8570A’s interrupt structure provides four basic types of interrupts: Periodic, Alarm/Compare, Timer, and Power Fail. Interrupt mask and status registers enable the masking and easy determination of each interrupt. One dedicated general purpose interrupt output is provided. A second interrupt output is available on the Multiple Func- tion Output (MFO) pin. Each of these may be selected to generate an interrupt from any source. Additionally, the MFO pin may be programmed to be either as oscillator out- put or Timer 0’s output. Pin Description CS,R D ,W R (Inputs): These pins interface to mP control lines. The CS pin is an active low enable for the read and write operations. Read and Write pins are also active low and enable reading or writing to the TCP. All three pins are disabled when power failure is detected. However, if a read or write is in progress at this time, it will be allowed to com- plete its cycle. A0–A4 (Inputs): These 5 pins are for register selection. They individually control which location is to be accessed. These inputs are disabled when power failure is detected. OSC IN (Input): OSC OUT (Output): These two pins are used to connect the crystal to the internal parallel resonant oscillator. The oscillator is always running when power is applied to V BB and V CC, and the correct crystal select bits in the Real Time Mode Register have been set. MFO (Output): The multi-function output can be used as a second interrupt output for interrupting the mP. This pin can also provide an output for the oscillator or the internal Timer 0. The MFO output can be programmed active high or low, open drain or push-pull. If in battery backed mode and a pull-up resistor is attached, it should be connected to a volt- age no greater than V BB. This pin is configured open drain during battery operation (V BB l VCC). INTR (Output): The interrupt output is used to interrupt the processor when a timing event or power fail has occurred and the respective interrupt has been enabled. The INTR output can be programmed active high or low, push-pull or open drain. If in battery backed mode and a pull-up resistor is attached, it should be connected to a voltage no greater than V BB. This pin is configured open drain during battery operation (V BB l VCC). The output is a DC voltage level. To clear the INTR, writ ea1t ot h e appropriate bit(s) in the Main Status Register. D0–D7 (Input/Output): These 8 bidirectional pins connect to the host mP’s data bus and are used to read from and write to the TCP. When the PFAIL pin goes low and a write is not in progress, these pins are at TRI-STATE. PFAIL (Input): In battery backed mode, this pin can have a digital signal applied to it via some external power detection logic. When PFAIL e logic 0 the TCP goes into a lockout mode, in a minimum of 30 ms or a maximum of 63 ms unless lockout delay is programmed. In the single power supply mode, this pin is not useable as an input and should be tied to V CC. Refer to section on Power Fail Functional Descrip- tion. VBB (Battery Power Pin): This pin is connected to a back- up power supply. This power supply is switched to the inter- nal circuitry when the V CC becomes lower than V BB. Utiliz- ing this pin eliminates the need for external logic to switch in and out the back-up power supply. If this feature is not to be used then this pin must be tied to ground, the TCP pro- grammed for single power supply only, and power applied to the V CC pin. TCK, G1, G0, (Inputs), T1 (Output): TCK is the clock input to both timers when they have an external clock selected. In modes 0, 1, and 2, G0 and G1 are active low enable inputs for timers 0 and 1 respectively. In mode 3, G0 and G1 are positive edge triggers to the timers. T1 is dedicated to the timer 1 output. The T1 output can be programmed active high or low, push-pull or open drain. Timer 0 output is avail- able through MFO pin if desired. If in battery backed mode and a pull-up resistor is attached to T1, it should be con- nected to a voltage no greater than V BB. The T1 pin is con- figured open drain during battery operation (V BB l VCC). VCC: This is the main system power pin. GND: This is the common ground power pin for both V BB and V CC. Connection Diagrams Dual-In-Line TL/F/8638–5 Top View Order Number DP8570AN See NS Package Number N28B Plastic Chip Carrier TL/F/8638–6 Top View Order Number DP8570AV See NS Package Number V28A

FIGURE 4. Oscillator Circuit Diagram

4.194304 MHz 68 pF 0 pF–80 pF 500 X to 900 X

4.9152 MHz 68 pF 29 pF–49 pF 500 X to 900 X

active high or low, and open drain or push pull outputs. regardless of the state of the Interrupt Routing Register. all conditions routed to the external pins. Main Status Register are the main interrupt bits. will reset all the periodic flags.

FIGURE 5. Interrupt Control Logic Overview

FIGURE 6. System-Battery Switchover (Upper Left), Power Fail 480 ms has elapsed by resetting the delay enable bit. allowed to equal the voltage at the V BB pin.

Functional Description (Continued) the chip is unlocked, but only after another 30 ms min x 63 ms max debounce time. The system designer must en- sure that his system is stable when power has returned. The power fail circuitry contains active linear circuitry that draws supply current from V CC. In some cases this may be undesirable, so this circuit can be disabled by masking the power fail interrupt. The power fail input can perform all lock-out functions previously mentioned, except that no ex- ternal interrupt will be issued. Note that the linear power fail circuitry is switched off automatically when using V BB in standby mode. LOW BATTERY, INITIAL POWER ON DETECT, AND POWER FAIL TIME SAVE There are three other functions provided on the DP8570A to ease power supply control. These are an initial Power On detect circuit, which also can be used as a time keeping failure detect, a low battery detect circuit, and a time save on power failure. On initial power up the Oscillator Fail Flag will be set to a one and the real time clock start bit reset to a zero. This indicates that an oscillator fail event has occurred, and time keeping has failed. The Oscillator Fail flag will not be reset until the real-time clock is started. This allows the system to discriminate be- tween an initial power-up and recovery from a power failure. If the battery backed mode is selected, then bit D6 of the Periodic Flag Register must be written low. This will not af- fect the contents of the Oscillator Fail Flag. Another status bit is the low battery detect. This bit is set only when the clock is operating under the V CC pin, and when the battery voltage is determined to be less than 2.1V (typical). When the power fail interrupt enable bit is low, it disables the power fail circuit and will also shut off the low battery voltage detection circuit as well. To relieve CPU overhead for saving time upon power failure, the Time Save Enable bit is provided to do this automatical- ly. (See also Reading the Clock: Latched Read.) The Time Save Enable bit, when set, causes the Time Save RAM to follow the contents of the clock. This bit can be reset by software, but if set before a power failure occurs, it will auto- matically be reset when the clock switches to the battery supply (not when a power failure is detected by the PFAIL pin). Thus, writing a one to the Time Save bit enables both a software write or power fail write. SINGLE POWER SUPPLY APPLICATIONS The DP8570A can be used in a single power supply applica- tion. To achieve this, the V BB pin must be connected to ground, and the power connected to V CC and PFAIL pins. The Oscillator Failed/Single Supply bit in the Periodic Flag Register should be set to a logic 1, which will disable the oscillator battery reference circuit. The power fail interrupt should also be disabled. This will turn off the linear power fail detection circuits, and will eliminate any quiescent power drawn through these circuits. Until the crystal select bits are initialized, the DP8570A may consume about 50 mA due to arbitrary oscillator selection at power on. (This extra 50 mA is not consumed if the battery backed mode is selected). TIMER FUNCTIONAL DESCRIPTION The DP8570A contains 2 independent multi-mode timers. Each timer is composed of a 16-bit negative edge triggered binary down counter and associated control. The operation is similar to existing mP peripheral timers except that several features have been enhanced. The timers can operate in four modes, and in addition, the input clock frequency can be selected from a prescaler over a wide range of frequen- cies. Furthermore, these timers are capable of generating interrupts as well as hardware output signals, and both the interrupt and timer outputs are fully programmable active high, or low, open drain, or push-pull. Figure 7 shows the functional block diagram of one of the timers. The timer consists of a 16-bit counter, two 8-bit input registers, two 8-bit output registers, clock prescaler, mode control logic, and output control logic. The timer and the data registers are organized as two bytes for each timer. Under normal operations a read/write to the timer locations will read or write to the data input register. The timer con- tents can be read by setting the counter Read bit (RD) in the timer control register. TIMER INITIALIZATION The timer’s operation is controlled by a set of registers, as listed in Table III. These consist of 2 data input registers and one control register per timer. The data input registers con- tain the timers count down value. The Timer Control Regis- ter is used to set up the mode of operation and the input clock rate. The timer related interrupts can be controlled by programming the Interrupt Routing Register and Interrupt Control Register 0. The timer outputs are configured by the Output Mode Register. TABLE III. Timer Associated Registers Register Name Register Page AddressSelect Select Timer 0 Data MSB X 0 10H Timer 0 Data LSB X 0 0FH Timer 0 Control Register 0 0 01H Timer 1 Data MSB X 0 12H Timer 1 Data LSB X 0 11H Timer 1 Control Register 0 0 02H Interrupt Routing Register 0 0 04H Interrupt Control Reg. 0 1 0 03H Output Mode Register 1 0 02H All these registers must be initialized prior to starting the timer(s). The Timer Control Register should first be set to select the timer mode with the timer start/stop bit reset. Then when the timer is to be started the control register should be rewritten identically but with the start/stop bit set. TIMER OPERATION Each timer is capable of operation in one of four modes. As mentioned, these modes are programmed in each timer’s Control Register which is described later. All four modes operate in a similar manner. They operate on the two 8-bit data words stored into the Data Input Register. At the begin- ning of a counting cycle the 2 bytes are loaded into the timer and the timer commences counting down towards zero. The exact action taken when zero is reached depends on the mode selected, but in general, the timer output will change state, and an interrupt will be generated if the timer inter- rupts are unmasked.

the corresponding setting in the Timer Control Register.

100 Hz a32 ms

10 Hz a32 ms

FIGURE 7. DP8570A Timer Block Diagram

Functional Description (Continued) TABLE VII. Register/Counter/RAM Addressing for DP8570A A0-4 PS RS Description(Note 1) (Note 2) CONTROL REGISTERS

00 X X Main Status Register

01 0 0 Timer 0 Control Register 02 0 0 Timer 1 Control Register 03 0 0 Periodic Flag Register 04 0 0 Interrupt Routing Register 01 0 1 Real Time Mode Register 02 0 1 Output Mode Register 03 0 1 Interrupt Control Register 0 04 0 1 Interrupt Control Register 1 COUNTERS (CLOCK CALENDAR) 05 0 X 1/100, 1/10 Seconds (0–99) 06 0 X Seconds (0–59) 07 0 X Minutes (0–59) 08 0 X Hours (1–12, 0–23) 09 0 X Days of 0A 0 X Months (1–12) 0B 0 X Years (0–99) 0C 0 X Julian Date (LSB) (0–99) (Note 3) 0D 0 X Julian Date (0–3) 0E 0 X Day of Week (1–7) TIMER DATA REGISTERS 0F 0 X Timer 0 LSB 10 0 X Timer 0 MSB 11 0 X Timer 1 LSB 12 0 X Timer 1 MSB TIME COMPARE RAM 13 0 X Sec Compare RAM (0–59) 14 0 X Min Compare RAM (0–59) 15 0 X Hours Compare RAM (1–12, 0–23) 16 0 X DOM Compare 17 0 X Months Compare RAM (1–12) 18 0 X DOW Compare RAM (1–7) TIME SAVE RAM 19 0 X Seconds Time Save RAM 1A 0 X Minutes Time Save RAM 1B 0 X Hours Time Save RAM 1C 0 X Day of Month Time Save RAM 1D 0 X Months Time Save RAM 1E 0 1 RAM 1F 0 X RAM/Test Mode Register 01–1F 1 X 2nd Page General Purpose RAM Note 1: PSÐPage Select (Bit D7 of Main Status Register) Note 2: RSÐRegister Select (Bit D6 of Main Status Register) Note 3: The LSB counters count 0–99 until the hundreds of days counter reaches 3. Then the LSB counters count to 65 or 66 (if a leap year). The rollover is from 365/366 to 1. MAIN STATUS REGISTER TL/F/8638–14 The Main Status Register is always located at address 0 regardless of the register block or the page selected. D0: This read only bit is a general interrupt status bit that is taken directly from the interrupt pins. The bit is a one when an interrupt is pending on either the INTR pin or the MFO pin (when configured as an interrupt). This is unlike D3–D5 which can be set by an internal event but may not cause an interrupt. This bit is reset when the interrupt status bits in the Main Status Register are cleared. D1–D5: These five bits of the Main Status Register are the main interrupt status bits. Any bit may be a one when any of the interrupts are pending. Once an interrupt is asserted the mP will read this register to determine the cause. These interrupt status bits are not reset when read. Except for D1, to reset an interrupt a one is written back to the correspond- ing bit that is being tested. D1 is reset whenever the PFAIL pin e logic 1. This prevents loss of interrupt status when reading the register in a polled mode. D1, D3–D5 are set regardless of whether these interrupts are masked or not by bits D6 and D7 of Interrupt Control Registers 0 and 1. D6 and D7: These bits are Read/Write bits that control which register block or RAM page is to be selected. Bit D6 controls the register block to be accessed (see memory map). The memory map of the clock is further divided into two memory pages. One page is the registers, clock and timers, and the second page contains 31 bytes of general purpose RAM. The page selection is determined by bit D7.

Functional Description (Continued) TIMER 0 AND 1 CONTROL REGISTER TL/F/8638–15 These registers control the operation of the timers. Each timer has its own register. D0: This bit will Start (1) or Stop (0) the timer. When the timer is stopped the timer’s prescaler and counter are reset, and the timer will restart from the beginning when started again. In mode 0 on time out the TSS bit is internally reset. D1 and D2: These control the count mode of the timers. See Table VI. D3–D5: These bits control which clock signal is applied to the timer’s counter input. There is one external clock input pin (TCK) and either (or both) timer(s) can be selected to run off this pin: refer to Table IV for details. D6: This is the read bit. If a one is written into this location it will cause the contents of the timer to be latched into a holding register, which can be read by the mP at any time. Reading the least significant byte of the timer will reset the RD bit. The timer read cycle can be aborted by writing RD to zero. D7: The CHG bit has two mode dependent functions. In modes 0 through 2 writing a one to this bit will suspend the timer operation (without resetting the timer prescaler). How- ever, in mode 3 this bit is used to trigger or re-trigger the count sequence as with the gate pins. If retriggering is de- sired using the CHG bit, it is not necessary to write a zero to this location prior to the re-trigger. The action of further writ- ing a one to this bit will re-trigger the count. PERIODIC FLAG REGISTER TL/F/8638–16 The Periodic Flag Register has the same bit for bit corre- spondence as Interrupt Control Register 0 except for D6 and D7. For normal operation (i.e., not a single supply appli- cation) this register must be written to on initial power up or after an oscillator fail event. D0–D5 are read only bits, D6 and D7 are read/write. D0–D5: These bits are set by the real time rollover events: (Time Change e 1). The bits are reset when the register is read and can be used as selective data change flags. D6: This bit performs a dual function. When this bit is read, a one indicates that an oscillator failure has occurred and the time information may have been lost. Some of the ways an oscillator failure may be caused are: failure of the crystal; shorting OSC IN or OSC OUT to GND or V CC; removal of crystal; removal of battery when in the battery backed mode (when a ‘0’ is written to D6); lowering the voltage at the V BB pin to a value less than 2.2V when in the battery backed mode. Bit D6 is automatically set to 1 on initial power-up or an oscillator fail event. The oscillator fail flag is reset by writing a one to the clock start/stop bit in the Real Time Mode Register, with the crystal oscillating. When D6 is written to, it defines whether the TCP is being used in battery backed (normal) or in a single supply mode application. When set to a one this bit configures the TCP for single power supply applications. This bit is automatically set on initial power-up or an oscillator fail event. When set, D6 disables the oscillator reference circuit. The result is that the oscillator is referenced to V CC. When a zero is written to D6 the oscillator reference is enabled, thus the oscillator is referenced to V BB. This allows operation in standard battery standby applications. At initial power on, if the DP8570A is going to be pro- grammed for battery backed mode, the V BB pin should be connected to a potential in the range of 2.2V to V CC b 0.4V. For single supply mode operation, the V BB pin should be connected to GND and the PFAIL pin connected to V CC. D7: Writing a one to this bit enables the test mode register at location 1F (see Table VII). This bit should be forced to zero during initialization for normal operation. If the test mode has been entered, clear the test mode register before leaving test mode. (See separate test mode application note for further details.) INTERRUPT ROUTING REGISTER TL/F/8638–17 D0–D4: The lower 5 bits of this register are associated with the main interrupt sources created by this chip. The purpose of this register is to route the interrupts to either the MFO (multi-function pin), or to the main interrupt pin. When any bit is set the associated interrupt signal will be sent to the MFO pin, and when zero it will be sent to the INTR pin.

Functional Description (Continued) D5: The Delay Enable bit is used when a power fail occurs. If this bit is set, a 480 ms delay is generated internally before the mP interface is locked out. This will enable the mPt o access the registers for up to 480 ms after it receives a power fail interrupt. After a power failure is detected but prior to the 480 ms delay timing out, the host mP may force immediate lock out by resetting the Delay Enable bit. Note if this bit i s a 0 when power fails then after a delay of 30 ms min/63 ms max the mP cannot read the chip. D6: This read only bit is set and reset by the voltage at the V BB pin. It can be used by the mP to determine whether the battery voltage at the V BB pin is getting too low. A compara- tor monitors the battery and when the voltage is lower than 2.1V (typical) this bit is set. The power fail interrupt must be enabled to check for a low battery voltage. D7: Time Save Enable bit controls the loading of real-time- clock data into the Time Save RAM. When a one is written to this bit the Time Save RAM will follow the corresponding clock registers, and when a zero is written to this bit the time in the Time Save RAM is frozen. This eliminates any syn- chronization problems when reading the clock, thus negat- ing the need to check for a counter rollover during a read cycle. This bit must be set to a one prior to power failing to enable the Time Save feature. When the power fails this bit is auto- matically reset and the time is saved in the Time Save RAM. REAL TIME MODE REGISTER TL/F/8638–18 D0–D1: These are the leap year counter bits. These bits are written to set the number of years from the previous leap year. The leap year counter increments on December 31st and it internally enables the February 29th counter state. This method of setting the leap year allows leap year to occur whenever the user wishes to, thus providing flexibility in implementing Japanese leap year function. LY1 LY0 Leap Year Counter 0 0 Leap Year Current Year 0 1 Leap Year Last Year 1 0 Leap Year 2 Years Ago 1 1 Leap Year 3 Years Ago D2: The count mode for the hours counter can be set to either 24 hour mode or 12 hour mode with AM/PM indicator. A one will place the clock in 12 hour mode. D3: This bit is the master Start/Stop bit for the clock. When a one is written to this bit the real time counter’s prescaler and counter chain are enabled. When this bit is reset to zero the contents of the real time counter is stopped and the prescaler is cleared. When the TCP is initially powered up this bit will be held at a logic 0 until the oscillator starts functioning correctly after which this bit may be modified. If an oscillator fail event occurs, this bit will be reset to logic 0. D4: This bit controls the operation of the interrupt output in standby mode. If set to a one it allows Alarm, Periodic, and Power Fail interrupts to be functional in standby mode. Tim- er interrupts will also be functional provided that bit D5 is also set. Note that the MFO and INTR pins are configured as open drain in standby mode. If bit D4 is set to a zero then interrupt control register 0 and bits D6 and D7 of interrupt control register 1 will be reset when the TCP enters the standby mode (V BB l VCC). They will have to be re-configured when system (V CC) power is restored. D5: This bit controls the operation of the timers in standby mode. If set to a one the timers will continue to function when the TCP is in standby mode. The input pins TCK, G0, G1 are locked out in standby mode, and cannot be used. Therefore external control of the timers is not possible in standby mode. Note also that MFO and T1 pins are auto- matically reconfigured open drain during standby. D6 and D7: These two bits select the crystal clock frequen- cy as per the following table: XT1 XT0 Crystal Frequency 0 0 32.768 kHz 0 1 4.194304 MHz 1 0 4.9152 MHz 1 1 32.000 kHz All bits are Read/Write, and any mode written into this regis- ter can be determined by reading the register. On initial power up these bits are random. OUTPUT MODE REGISTER TL/F/8638–19

Functional Description (Continued) D0: This bit, when set to a one makes the T1 (timer 1) output pin active high, and when set to a zero, it makes this pin active low. D1: This bit controls whether the T1 pin is an open drain or push-pull output. A one indicates push pull. D2: This bit, when set to a one makes the INTR output pin active high, and when set to a zero, it makes this pin active low. D3: This bit controls whether the INTR pin is an open drain or push-pull output. A one indicates push-pull. D4: This bit, when set to a one makes the MFO output pin active high, and when set to a zero, it makes this pin active low. D5: This bit controls whether the MFO pin is an open drain or push-pull output. A one indicates push-pull. D6 and D7: These bits are used to program the signal ap- pearing at the MFO output, as follows: D7 D6 MFO Output Signal 0 0 2nd Interrupt 0 1 Timer 0 Waveform

1 X Buffered Crystal Oscillator

INTERRUPT CONTROL REGISTER 0 TL/F/8638–20 If battery backed mode is selected and the DP8570A is in standby (V BB l VCC), then all bits are controlled by D4 of the Real Time Mode Register. D0–D5: These bits are used to enable one of the selected periodic interrupts by writing a one into the appropriate bit. These interrupts are issued at the rollover of the clock. For example, the minutes interrupt will be issued whenever the minutes counter increments. In all likelihood the interrupt will be enabled asynchronously with the real time change. Therefore, the very first interrupt will occur in less than the periodic time chosen, but after the first interrupt all subse- quent interrupts will be spaced correctly. These interrupts are useful when minute, second, real time reading, or task switching is required. When all six bits are written to a 0 this disables periodic interrupts from the Main Status Register and the interrupt pin. D6 and D7: These are individual timer enable bits. A one written to these bits enable the timers to generate interrupts to the mP. INTERRUPT CONTROL REGISTER 1 TL/F/8638–21 D0–D5: Each of these bits are enable bits which will enable a comparison between an individual clock counter and its associated compare RAM. If any bit is a zero then that clock-RAM comparator is set to the ‘‘always equal’’ state and the associated TIME COMPARE RAM byte can be used as general purpose RAM. However, to ensure that an alarm interrupt is not generated at bit D3 of the Main Status Regis- ter, all bits must be written to a logic zero. D6: In order to generate an external alarm compare inter- rupt to the mP from bit D3 of the Main Status Register, this bit must be written to a logic 1. If battery backed mode is selected and the DP8570A is in standby (V BB l VCC), then this bit is controlled by D4 of the Real Time Mode Register. D7: The MSB of this register is the enable bit for the Power Fail Interrupt. When this bit is set to a one an interrupt will be generated to the mP when PFAIL e 0. If battery backed mode is selected and the DP8570A is in standby BB l VCC), then this bit is controlled by D4 of the Real Time Mode Register. This bit also enables the low battery detection analog cir- cuitry. If the user wishes to mask the power fail interrupt, but utilize the analog circuitry, this bit should be enabled, and the Routing Register can be used to route the interrupt to the MFO pin. The MFO pin can then be left open or configured as the Timer 0 or buffered oscillator output.

Control and Status Register Address Bit Map D7 D6 D5 D4 D3 D2 D1 D0 1. Reset byMain Status Register PS e 0R S e 0 ADDRESS e 00H writingR/W R/W R/W 1 R/W1 R/W1 R/W1 R2 R3 1 to bit. Page Register Timer 1 Timer 0 Alarm Periodic Power Fail Interrupt 2. Set/reset bySelect Select Interrupt Interrupt Interrupt Interrupt Interrupt Status voltage at PFAIL pin. 3. Reset when all pending interrupts are removed. Timer 0 Control Register PS e 0R S e 0 Address e 01H Count Hold Timer Input Clock Input Clock Input Clock Mode Mode Timer All Bits R/WGate Read Select C2 Select C1 Select C0 Select M1 Select M0 Start/Stop Timer 1 Control Register PS e 0R S e 0 Address e 02H Count Hold Timer Input Clock Input Clock Input Clock Mode Mode Timer All Bits R/WGate Read Select C2 Select C1 Select C0 Select M1 Select M0 Start/Stop Periodic Flag Register PS e 0R S e 0 Address e 03H 4. Read Osc failR/W R/W 4 R5 R5 R5 R5 R5 R5 Write 0 Batt- Test Osc. Fail/ 1 ms 10 ms 100 ms Seconds 10 Second Minute Backed Mode Mode Single Supply Flag Flag Flag Flag Flag Flag Write 1 Single Supply Mode 5. Reset by positive edge of read. Interrupt Routing Register PS e 0R S e 0 Address e 04H R/W R 6 R/W R/W R/W R/W R/W R/W Time Save Low Battery Power Fail Timer 1 Timer 0 Alarm Periodic Power Fail 6. Set and reset voltage.Enable MFO/INT MFO/INT MFO/INT MFO/INT MFO/INT Real Time Mode Register PS e 0R S e 1 Address e 01H Crystal Crystal Timers EN Interrupt EN Clock 12/24 Hr. Leap Year Leap Year All Bits R/WFreq. XT1 Freq. XT0 on Back-Up on Back-Up Start/Stop Mode MSB LSB Output Mode Register PS e 0R S e 1 Address e 02H MFO as MFO as MFO MFO INTR INTR T1 T1 All Bits R/WCrystal Timer 0 PP/OD Active HI/LO PP/OD Active HI/LO PP/OD Active HI/LO Interrupt Control Register 0 PS e 0R S e 1 Address e 03H Timer 1 Timer 0 1 ms 10 ms 100 ms Seconds 10 Second Minute Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt All Bits R/W Enable Enable Enable Enable Enable Enable Enable Enable Interrupt Control Register 1 PS e 0R S e 1 Address e 04H Power Fail Alarm DOW Month DOM Hours Minute Second Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt All Bits R/W Enable Enable Enable Enable Enable Enable Enable Enable

Suggested Initialization Procedure for DP8570A in bat- tery backed applications that use the V BB pin 1. Enter the test mode by writin ga1t ob i tD 7i nt h e Period- ic Flag Register. 2. Write zero to the RAM/TEST mode Register located in page 0, address HEX 1F. 3. Leave the test mode by writin ga0t ob i tD 7i nt h e Period- ic Flag Register. Steps 1, 2, 3 guarantee that if the test mode had been entered during power on (due to random pulses from the system), all test mode conditions are cleared. Most important is that the OSC Fail Disable bit is cleared. Refer to AN-589 for more information on test mode operation. 4. After power on (V CC and V BB powered), select the cor- rect crystal frequency bits (D7, D6 in the Real Time Mode Register) as shown in Table I. TABLE I Frequency D7 D6 32.768 kHz 0 0

4.194304 MHz 0 1

4.9152 MHz 1 0

32.0 kHz 1 1 5. Enter a software loop that does the following: Set a 3 second (approx.) software counter. The crystal oscillator may take 1 second to start.

5.1 Writ ea1t ob i tD 3i nt h e Real Time Mode Register

(try to start the clock). Make sure the crystal select bits remain the same as in step 1. Under normal operation, this bit can be set only if the oscillator is running. During the software loop, RAM, real time counters, output configuration, interrupt control and timer functions may be initialized. 6. Test bit D6 in the Periodic Flag Register: I Fa1 , go to 5.1. If this bit remain s a 1 after 3 seconds, then abort and check hardware. The crystal may be de- fective or not installed. There may be a short at OSC IN or OSC OUT to V CC or GND, or to some impedance that is less than 10 M X. I Fa0 , then the oscillator is running, go to step 7. 7. Writ ea0t ob i tD 6i nt h e Periodic Flag Register. This action puts the clock chip in the battery backed mode. This mode can be entered only if the osc fail flag (bit D6 of the Periodic Flag Register) is a 0. Reminder, Bit D6 is a dual function bit. When read, D6 returns oscillator status. When written, D6 causes either the Battery Backed Mode, or the Single Supply Mode of operation. The only method to ensure the chip is in the battery backed mode is to measure the waveform at the OSC OUT pin. If the battery backed mode was selected suc- cessfully, then the peak to peak waveform at OSC OUT is referenced to the battery voltage. If not in battery backed mode, the waveform is referenced to V CC. The measurement should be made with a high impedance low capacitance probe (10 M X, 10 pF oscilloscope probe or better). Typical peak to peak swings are within 0.6V of V CC and ground respectively. 8. Writ ea1t ob i tD 7o f Interrupt Control Register 1. This action enables the PFAIL pin and associated circuitry. 9. Writ ea1t ob i tD 4o ft h e Real Time Mode Register. This action ensures that bit D7 of Interrupt Control Register 1 remains a 1 when V BB l VCC (Standby Mode). 10. Initialize the rest of the chip as needed. Typical Application TL/F/8638–22 *These components may be necessary to meet UL requirements for lithium batteries. Consult battery manufacturer.

TL/F/8638–30 FIGURE A1. Typical Interface Where the ‘‘Write Strobe’’ is Synchronized to the Decrementing Clock of the Timer

Typical Performance Characteristics Operating Current vs Supply Voltage (Single Supply Mode F OSC e 32.768 kHz) TL/F/8638–26 Operating Current vs Supply Voltage (Battery Backed Mode F OSC e 32.768 kHz) TL/F/8638–27 Standby Current vs Power Supply Voltage OSC e 32.768 kHz) TL/F/8638–28 Standby Current vs Power Supply Voltage F OSC e 4.194304 MHz TL/F/8638–29

Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number DP8570AN

DP8570A Timer Clock Peripheral (TCP) Physical Dimensions inches (millimeters) (Continued) Plastic Chip Carrier Package (V) Order Number DP8570AV LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd. 2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16 P.O. Box 58090 D-82256 F 4urstenfeldbruck Engineering Center Ocean Centre, 5 Canton Rd. 120-3A Business Park Drive Santa Clara, CA 95052-8090 Germany Bldg. 7F Tsimshatsui, Kowloon Sao Paulo-SP Monash Business Park Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999 Tel: (043) 299-2300 Fax: (55-11) 212-1181 Fax: (3) 558-9998 Fax: (043) 299-2500 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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