DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 21
Technical content
Features
- Contactless Transmission of Data
- ISO 15693 / ISO 18000−3 Mode1 Compliant ♦ Vicinity Range Communication (up to 150 cm) ♦ Air Interface Communication at 13.56 MHz (HF) ♦ To tag: ASK Modulation with 1.65 Kbit/s or 26.48 Kbit/s Data Rate ♦ From Tag: Load Modulation Using Manchester Coding with 423 kHz and 484 kHz Subcarriers in Low (6.6 Kbit/s) or high (26 Kbit/s) Data Rate Mode. Supports the 53 Kbit/s Data Rate with Fast Commands
- Read & Write 32−bit Block Mode
- Anti−collision Support
- Security: ♦ 64−bit Unique Identifier (UID) ♦ Multiple 32−bit Passwords and Lock Feature for Each User Memory Sector
- Supports Fast (400 kHz) and Fast−Plus (1 MHz) I2C Protocol
- 1.8 V to 5.5 V Supply V oltage Range
- 4−Byte Page Write Buffer
- I2C Timeout
- Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA)
- 512Blocks x 32 Bits (16 Sectors of 32 Blocks Each): RF Mode
- 2048 x 8 Bits I2C Mode
- 2,000,000 Program/Erase Cycles
- 200 Year Data Retention
- −40/C0095C to +105/C0095C Temperature Range
- SOIC, TSSOP 8−lead Packages
- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant* www.onsemi.com SOIC 8 CASE 751BD See detailed ordering and shipping information on page 21 of this data sheet.
ORDERING INFORMATION
A0, A1 SDA VCC VSS Device Address Serial Data Power Supply Ground Pin Name Function *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. TSSOP8, 4.4x3 CASE 948AL AN1 AN2 VSS SDA SCL VCC SOIC (W, X), TSSOP (Y) SCL AN1, AN2 Serial Clock Antenna Coil X = Specific Device Code A = Assembly Site Code Y = Production Year (Last Digit) M = Production Month Code ZZZ = Last 3 Characters of Assembly Lot Number X AYMZZZ X AYMZZZ
Figure 1. Functional Symbol Table 1. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- During transitions, the voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on the SCL and SDA
I2C pins should not exceed the absolute maximum ratings, irrespective of VCC. Table 2. RELIABILITY CHARACTERISTICS − EEPROM (Note 2)
- Determined through qualification/characterization.
- A Write Cycle refers to writing a Byte or a Page.
Table 3. DC OPERATING CHARACTERISTICS − I2C MODE performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- When not driven, the A0 and A1 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
CMOS input buffer, the strong pull−down is disabled. Table 4. PIN IMPEDANCE CHARACTERISTICS
- These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
Table 5. AC CHARACTERISTICS − I2C MODE (Note 6) performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- Test conditions according to “AC Test Conditions” table.
- Tested initially and after a design or process change that affects this parameter.
PU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. AC TEST CONDITIONS
Table 7. RF CHARACTERISTICS (Notes 9, 10) (TA = −40°C to +105°C, unless otherwise specified)
- External size: 72 mm x 42 mm
- Number of turns: 7
- Antenna is printed on the PCB plated with 35 /C0109m of Cooper
- Track width: 0.8 mm
- Space: 0.5 mm
- Coil: 5 /C0109H 11. Characterized at room temperature only.
www.onsemi.com Power−On Reset (POR) Each N24RF16 incorporates Power −On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi −directional POR behavior protects the device against ‘brown−out’ failure following a temporary loss of power. Pin Description
- SCL: The Serial Clock input pin accepts the clock signal generated by the Master
- SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL
- A0, A1: The Address inputs set the device address that must be matched by the corresponding Slave address bits. The Address inputs are hard−wired HIGH or LOW allowing for up to four devices to be used (cascaded) on the same bus. When left floating, these pins are pulled LOW internally
- AN1, AN2: These inputs are used to connect the device to an external antenna. The coil is used to power and access the device through the ISO 15693 and ISO 18000−3 mode 1 RF protocols Functional Description The N24RF16 is a dual interface RFID/NFC tag with 16 Kb EEPROM. The device follows the ISO 15693 and ISO 18000−3 mode 1 standard for the radio frequency power and signal interface via the 13.56 MHz carrier. When connected to an antenna coil, no external power supply is required, as the operating power is derived from the RF energy The communication from the RF Reader to the N24RF16 tag takes place using the ASK modulation with a 1.65 Kb/s data rate using the 1/256 pulse coding or a data rate of 26.48 Kb/s using the 1/4 pulse coding. The communication from the EEPROM tag to the RF reader takes place via load modulation using Manchester coding with 423 kHz and 484 kHz subcarrier frequencies at 6.62 Kb/s or 26.48 Kb/s data rate. The device supports also the 53 Kb/s fast mode. The N24RF16 supports the Inter−Integrated Circuit (I 2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic and Slave devices which execute requests. The N24RF16 operates as a Slave device with a 4−bit device identifier code (1010b) according to the I 2C standard definition. Memory Organization In the RF mode, the user memory area is organized into 16 sectors of 32 blocks each for a total of 512 blocks x 32 bits. The memory access from the I 2C interface is organized as 2048 x 8 bits, divided into 16 sectors of 128 bytes each. The user and system memory organization is shown in Figure 4. Each memory sector can be individually read and/or write protected using a specific password. The N24RF16 provides four 32−bit blocks to store three RF password and one I2C password codes. In RF mode, the read and write access is done by 32−bit block. Read and Write access is controlled by a Sector Security Status (SSS) byte which includes 5 significant bits: Sector Lock bit, two Read / Write protection bits and two Password Control bits. In I 2C mode, a sector has 128 bytes that can be individually accessed for Read and Write. Each sector can be protected against write operations using the I 2C−Write_Lock bit from the 16−bit block area. The N24RF16 features a 64−bit block to store the 64−bit Unique Identifier (UID) per the ISO 15963 requirements. The UID value is written by ON Semiconductor during manufacturing and it is used during the anti −collision sequence. The system memory area also includes the application family identifier (AFI) and a data storage family identifier (DSFID) used in the anti−collision algorithm. The access to the user memory area requires the A2 bit from the Slave address byte set to “0” (Figure 5). All system memory blocks are accessed with A2 bit set to “1”. Table 8. I2C Byte Address Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0] A2=1 0 SSS 3 (00h) SSS 2 (00h) SSS 1 (00h) SSS 0 (00h) A2=1 4 SSS 7 (00h) SSS 6 (00h) SSS 5 (00h) SSS 4 (00h) A2=1 8 SSS 11 (00h) SSS 10 (00h) SSS 9 (00h) SSS 8 (00h) A2=1 12 SSS 15 (00h) SSS 14 (00h) SSS 13 (00h) SSS 12 (00h) A2=1 2048 − − I2C Write Lock [15:8] (00h) I2C Write Lock [7:0] (00h) A2=1 2304 I2C password (0000 0000h) A2=1 2308 RF password 1 (0000 0000h) A2=1 2312 RF password 2 (0000 0000h) A2=1 2316 RF password 3 (0000 0000h) A2=1 2320 DSFID (FFh) AFI (00h) ON reserved ON reserved
Table 8. (continued) Figure 4. Memory Organization
1 Kbit EEPROM Sector
00 Sector not protected by password
01 Sector protected by Password 1
10 Sector protected by Password 2
11 Sector protected by Password 3
HIGH SDA transition, while SCL is HIGH.
www.onsemi.com READ OPERATIONS Immediate Read To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 12). The Slave then returns to Standby mode. Selective Read To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends two address bytes to the Slave. Rather than completing the Byte Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 13). Sequential Read If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 14). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. I2C SECURITY In the I 2C mode it is possible to protect each memory sector from user area against write operations. The sector write access is controlled using the 16−bit I2C_Write_Lock bit area and the 32 −bit I 2C password. There are two commands to control the I 2C password: I 2C Present Password and I2C Write Password. I2C Present Password The I2C Present Password command is used to modify the write access rights of the sectors protected by the I 2C Write−Lock bits, including the password itself. N24RF16 will allow this only if the correct password is presented, via I2C bus. If the password is correct, the access rights remain activated until a new I 2C Present Password command is received, or the device is powered off. Following a Start condition, the master sends a write instruction with the slave address with the Read/Write bit equal to 0 and the A2 bit equal to 1 (system memory). The device acknowledges this and expects two I 2C password address bytes, 09h and 00h. The device responds to each address byte with an ACK. The device then expects the 4 password data bytes, the validation code, 09h, and a resend of the 4 password data bytes. The most significant byte of the password is sent first, followed by the least significant bytes. The 32−bit password must be sent twice to prevent any data corruption during the sequence. If the two 32 −bit passwords sent are not exactly the same, the command will not be accepted. When the bus master generates a Stop condition immediately after the Ack bit, an internal delay equivalent to the write cycle time is triggered. A Stop condition at any other time does not trigger the internal delay. During that delay, the N24RF16 compares the 32 received data bits with the 32 bits of the stored I 2C password. If the values match, the write access rights to all protected sectors are modified after the internal delay. If the values do not match, the protected sectors remains protected. During the internal delay, the SDA output is tri−stated and the Slave does not acknowledge the Master. I2C Write Password The I2C Write Password command is used to overwrite the 32−bit I2C password block. This command is used in I 2C mode to update the I2C password value. It cannot be used to modify any of the RF passwords. After the write cycle, the new I 2C password value is automatically activated. The I2C password value can only be modified after issuing a valid I 2C Present Password command. Following a Start condition, the master sends a write instruction with the slave address with the Read/Write bit equal to 0 and the A2 bit equal to 1 (system memory). The device acknowledges this and expects two I 2C password address bytes, 09h and 00h. The device responds to each address byte with an ACK. The device then expects the 4 password data bytes, the validation code, 07h, and a resend of the 4 password data bytes. The most significant byte of the password is sent first, followed by the least significant bytes. N24RF16 is shipped with the default I 2C password 00000000h. By default, the password is activated. The 32−bit password must be sent twice to prevent any data corruption during the sequence. If the two 32 −bit passwords sent are not exactly the same, the command will not be accepted. When the bus master generates a Stop condition immediately after the Ack bit, the internal write cycle is triggered. A Stop condition at any other time does not trigger the internal write cycle. During the internal write cycle, the SDA output is tri−stated and the Slave does not acknowledge the Master.
- Activation of the N24RF16 memory tag by the electromagnetic field of the RF Reader
- Transmission of a command / request by the RF Reader
- Transmission of a response by the memory tag The memory tag operates continuously under the electromagnetic field (H) generated by the RF Reader. The transmission of data and power is based on inductive coupling using the carrier frequency (f C) as 13.56 MHz ±7 kHz per ISO 15693 standard. Each request from the Reader and each response from the N24RF16 tag are organized in a frame, delimited by a start of frame (SOF) and an end of frame (EOF). Communication from RF Reader to N24RF16 Tag The communication between the RF Reader and memory tag uses the ASK (Amplitude Shift Keying) modulation. The received signal is demodulated by the ASK demodulator of the memory tag. The N24RF16 supports both 100% and 10% modulation index. The Reader selects which index is used. Figure 14 shows the 100% ASK modulation waveform. The data transmission uses pulse position coding described in the ISO 15693: 1 out of 256 data coding with a resulting data rate of 1.65 Kb/s or 1 out of 4 data coding with a data rate of 26.48 Kb/s. The request from RF Reader to the memory tag consists of: a request SOF, flags, command code, parameters, data, 2−byte CRC, a request EOF. The SOF defines the data coding mode that will be used by the RF Reader for the following command. Figure 15 shows a SOF to select 1 out of 256 data coding and Figure 16 illustrates the SOF to select
Figure 15. Request SOF for 1 out of 256 Data Coding Figure 16. Request SOF for 1 out of 4 Data Coding Table 9. TAG RESPONSE DATA RATES
6.67 Kb/s
26.69 Kb/s
Table 10. RF COMMAND DESCRIPTION
1 Inventory Perform the anticollision sequence
2 Stay quiet Put the N24RF16 in quiet mode, where it does not respond to any inventory
3 Read single block Output the 32 bits of the selected block and its locking status
4 Write single block Write the 32−bit value in the selected block, if it is not locked
5 Read multiple blocks Read the selected blocks and send back their value
6 Select Select the N24RF16; after this command the device processes all Read/Write
7 Reset to ready Enter the ready state
8 Write AFI Write the 8−bit value in the AFI register
9 Lock AFI Used to lock the AFI register
10 Write DSFID Write the 8−bit value in the DSFID register
11 Lock DSFID Lock the DSFID register.
12 Get system info Provide the system information value
13 Get multiple block security status Send the security status of the selected block
14 Write sector password Write the 32−bit selected password
15 Lock sector Write the sector security status bits of the selected sector
16 Present sector password Enables the user to present a password to unprotect the user blocks linked to
17 Fast read single block Output the 32 bits of the selected block and its locking status
18 Fast inventory initiated Perform the anticollision sequence triggered by the Initiate command
19 Fast initiate Trigger the tag response to the Inventory initiated sequence
20 Fast read multiple blocks Read the selected blocks and send back their value
21 Inventory initiated Perform the anticollision sequence triggered by the Initiate command
22 Initiate Trigger the tag response to the Inventory initiated sequence
Table 11. RF COMMAND FORMAT
1 Inventory x 8 bits 01h − − 8 bits 8 bits
2 Stay Quiet x 8 bits 02h − 8 bytes − − − 16 bits x
3 Read
4 Write
5 Read
6 Select x 8 bits 25h − 8 bytes − − − 16 bits x
Table 11. RF COMMAND FORMAT (continued)
7 Reset to
8 Write AFI x 8 bits 27h − 8 bytes
9 Lock AFI x 8 bits 28h − 8 bytes
10 Write
11 Lock
12 GET
13 Get
14 Write
15 Lock
16 Present
17 Fast read
18 Fast
19 Fast
20 Fast read
21 Inventory
22 Initiate x 8 bits D2h 67h − − − − 16 bits x
14.Block number/First block number.
Table 12. INSTRUCTION RESPONSE FORMAT (No Error)
1 Inventory x 00h DSFID 8 bytes − − − − − 16 bits x
3 Read single
4 Write single
5 Read multiple
6 Select x 00h − − − − − − − 16 bits x
7 Reset to ready x 00h − − − − − − − 16 bits x
8 Write AFI x 00h − − − − − − − 16 bits x
9 Lock AFI x 00h − − − − − − − 16 bits x
10 Write DSFID x 00h − − − − − − − 16 bits x
11 Lock DSFID x 00h − − − − − − − 16 bits x
12 Get System
18.SSS optional (FL_OPT = 1). Table 13. INSTRUCTION RESPONSE FORMAT (Error Flag = 1)
3 Read single block x 01h 8 bits 16 bits x
4 Write single block x 01h 8 bits 16 bits x
5 Read multiple block x 01h 8 bits 16 bits x
6 Select x 01h 8 bits 16 bits x
7 Reset to ready x 01h 8 bits 16 bits x
8 Write AFI x 01h 8 bits 16 bits x
9 Lock AFI x 01h 8 bits 16 bits x
10 Write DSFID x 01h 8 bits 16 bits x
11 Lock DSFID x 01h 8 bits 16 bits x
12 Get System Info x 01h 8 bits 16 bits x
13 Get Multiple Block SS x 01h 8 bits 16 bits x
14 Write sector password x 01h 8 bits 16 bits x
15 Lock sector x 01h 8 bits 16 bits x
16 Present sector password x 01h 8 bits 16 bits x
17 Fast read single Block x 01h 8 bits 16 bits x
Table 13. INSTRUCTION RESPONSE FORMAT (Error Flag = 1) (continued)
18 Fast Inventory Initiated − − − − −
19 Fast Initiate − − − − −
20 Fast read multiple Block x 01h 8 bits 16 bits x
21 Inventory Initiated − − − − −
Table 14. RESPONSE ERROR CODE
3 Read single block − x − x − − − − x
4 Write single block − x − x − x x − −
5 Read multiple block − x x x − − − − x
10 Write DSFID − x − − − x x − −
11 Lock DSFID − x − − x − − x −
13 Get Multiple Block SS − x x x − − − − −
14 Write sector password x x − x − x x − −
15 Lock sector x x − x x − − x −
16 Present sector password x x x x − − − − −
17 Fast read single Block x x − x − − − − x
18 Fast Inventory Initiated − − − − − − − − −
20 Fast read multiple Block x x x x − − − − x
Table 15. REQUEST FLAGS
1 Inventory 0 0 − 0/1 − 0/1 0 1 0/1 0/1
2 Stay Quiet 0 0 1 − 0 − 0 0 0/1 0/1
3 Read single block 0 0/1 0/1 − 0/1 − 1 0 0/1 0/1
4 Write single block 0 0/1 0/1 − 0/1 − 1 0 0/1 0/1
6 Select 0 0 1 − 0 − 0 0 0/1 0/1
7 Reset to ready 0 0 0/1 − 0/1 − 0 0 0/1 0/1
8 Write AFI 0 0/1 0/1 − 0/1 − 0 0 0/1 0/1
9 Lock AFI 0 0/1 0/1 − 0/1 − 0 0 0/1 0/1
10 Write DSFID 0 0/1 0/1 − 0/1 − 0 0 0/1 0/1
11 Lock DSFID 0 0/1 0/1 − 0/1 − 0 0 0/1 0/1
12 GET System Info 0 0 0/1 − 0/1 − 0/1 0 0/1 0/1
13 Get Multiple
14 Write sector
15 Lock sector 0 0/1 0/1 − 0/1 − 0 0 0/1 0/1
16 Present sector
17 Fast read single
18 Fast Inventory
19 Fast Initiate 0 0 0 − 0 − 0 0 0/1 0
20 Fast read multiple
21 Inventory Initiated 0 0 − 0/1 − 0/1 0 1 0/1 0/1
22 Initiate 0 0 0 − 0 − 0 0 0/1 0/1
www.onsemi.com PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E A h θ L c e b D PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. SYMBOL MIN NOM MAX θ A b c D E e h 0º 8º 0.10 0.33 0.19 0.25 4.80 5.80 3.80
1.27 BSC
1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 L 0.40 1.27 1.35
www.onsemi.com TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O E1 E e b D cA TOP VIEW SIDE VIEW END VIEW /C01131 L Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. SYMBOL θ MIN NOM MAX A b c D E e 0º 8º L 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30
0.65 BSC
1.00 REF
1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
www.onsemi.com Marking Package Type Temperature Range Lead Finish Shipping1 N24RF16DWPT3G 24RF04 SOIC−8 (Pb−Free) −40/C0095C to +105/C0095C NiPdAu 3000 / Tape & Reel N24RF16DTPT3G RF04 TSSOP−8 (Pb−Free) −40/C0095C to +105/C0095C NiPdAu 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 20.All packages are RoHS−compliant (Pb−Free, Halogen−free). 21.Contact factory for availability. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries i n the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . A listing of ON Semiconductor’s product/patent ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the right s of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 N24RF16/D ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol. LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative