N24C008 ONSEMI | Alldatasheet
Document overview
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- PDF pages: 11
Technical content
Features
- Supports Standard, Fast and Fast−Plus I2C Protocol
- SCL and SDA are referred to 1.2 V
- 1.4 V (Min) to 2.2 V (Max) Supply V oltage Range
- 16 Byte Page Write Buffer
- Lockable Secure Data Page
- User Programmable Write Protection
- User Programmable Device Address
- Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
- Low Power CMOS Technology
- 1,000,000 Program/Erase Cycles
- 100 Year Data Retention
- Industrial Temperature Range: −40°C to +85°C
- Ultra−thin 4−ball WLCSP Package
- This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant* 1.2 V See detailed ordering and shipping information on page 9 of this data sheet.
ORDERING INFORMATION
Figure 1. Typical Application
Table 1. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 1.0 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2)
- These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
Table 3. DC AND AC OPERATING CHARACTERISTICS Table 4. D.C. OPERATING CHARACTERISTICS performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 5. PIN IMPEDANCE CHARACTERISTICS
- These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
- Test conditions according to “A.C. Test Conditions” table.
- Tested initially and after a design or process change that affects this parameter.
- t PU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 7. A.C. TEST CONDITIONS Figure 2. Maximum Pull−up Resistance vs. Load Capacitance at I/Os for Typical Applications
www.onsemi.com POWER−ON RESET (POR) The N24C008 incorporates Power −On Reset (POR) circuitry which protects the device against powering up in the wrong state. The N24C008 will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when V CC drops below the POR trigger level. This bi−directional POR feature protects the device against “brown−out” failure following a temporary loss of power. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. Functional Description The N24C008 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The N24C008 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 2 devices may be connected to the bus as determined by the Device Address bit A2 in the Device Configuration Register. I2C Bus Protocol The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the 1.2 V via pull−up resistors. Master and Slave devices connect to the 2−wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 3). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake −up’ call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8 -bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations, and to 1011 for special Read/Write operations (Figure 4). The next bit must match the A2 bit in the Device Configuration Register. The next two bits are MSB’s memory address. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. The factory default for the A2 bit is 0. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9 th clock cycle (Figure 5). The Slave will also acknowledge all address bytes and every data byte presented in Write mode if the addressed location is not write protected. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9 th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 6.
Figure 3. Start/Stop Conditions Figure 4. Slave Address Bits
1011 A2 x x R/W
Figure 5. Acknowledge Timing Figure 6. Bus Timing
acknowledge any Read or Write request from the Master. starts immediately following the STOP. acknowledge the Slave address. of 10xx xxxx, where x is don’t care. read, but not to write the content of the Secure Data Page. of each bit.) The A2 bit determines the Device Address. to 1. The SWP bit alone can be changed to 0. not support acknowledge polling. Table 8. BYTE ADDRESS
www.onsemi.com READ OPERATIONS Immediate Read Upon receiving a Slave address with the R/W bit set to ‘1’, the N24C008 will interpret this as a request for data residing at the current byte address in memory. The N24C008 will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the N24C008 returns to Standby mode. Selective Read To read data residing at a specific location, the internal address counter must first be initialized as described under Byte Write. If rather than following up the address byte with data, the Master instead follows up with an Immediate Read sequence, then the N24C008 will use the 10 active address bits to initialize the internal address counter and will shift out data residing at the corresponding location. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 11), the N24C008 returns to Standby mode. Sequential Read If during a Read session the Master acknowledges the 1st data byte, then the N24C008 will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap−around at end of memory (rather than end of page). Secure Data Page Read The Secure Data Page Read instruction is similar to a Sequential Read instruction. To read data from a specific location within the Secure Data Page, the address counter is initialized by sending the device header and the address byte as for a Secure Data Page Write instruction. This dummy write instruction is followed by an Immediate Read with the device header 1011b, and the device will shift back data from Secure Data Page. When the end of the Secure Data Page is reached, the address counter will wrap −around to zero, and the next byte returned will be the first byte in the page. Device Configuration Register Read The Device Configuration Register Read instruction is similar to a Selective Read instruction. The user must send the device header and the address byte as for a Device Configuration Register Write instruction. This dummy write instruction is followed by an Immediate Read with the device header 1011b, and the device will shift back the content of the Device Configuration Register. Don’t care bits are read as 1s. If the master acknowledges the data byte, requesting more data, the device will continue to return the content of the Device Configuration Register until the master responds with a NoACK. Unique ID Number Read The Unique ID Number Read instruction is similar to a Sequential Read instruction. The user must send the device header starting with 1011b followed by the A2 bit that match the bit in the Device Configuration register. As specified in Table 8, the second byte consists of 01xx 0000 where x is don’t care. This dummy write instruction is followed by an Immediate Read with the device header 1011b, and the device will shift back the Unique ID byte by byte. The Unique ID is 16 bytes (128 bits) long. After the last byte of the Unique ID has been shifted, if the master acknowledges (requesting more data), the device will wrap −around and start returning the Unique ID from the beginning. Secure Data Page Lock Status Read There are two ways to check the lock status of the Security Sector. The first way is to initiate a Secure Data Page Write. The EEPROM will acknowledge if the Secure Data Page is unlocked, and it will not acknowledge if the Secure Data Page is locked. After the acknowledge bit, it is recommended to generate a Start condition followed by a Stop condition, to reset the interface. The second way is to use a Lock Status Read instruction. This instruction is similar to a Selective Read instruction, but requires the use of the device address 1011b followed by the A2 bit. The master first sends a dummy write instruction followed by the address byte specified in Table 8 (10xx xxxx where x is don’t care). This is followed by a read instruction using the same device address as above. The device will return a data byte where Bit 1 indicates the lock status. If the lock is active this bit is “1”, otherwise it is “0”. Delivery State The N24C008 is shipped erased, i.e., all memory array bytes are FFh, and the settable Device Configuration bits set to 0 (7Dh).
WLCSP4 0.75x0.75x0.3 CASE 567GG ISSUE A DATE 19 JAN 2023 X = Specific Device Code M = Month Code GENERIC MARKING DIAGRAM* XM *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “/C0071”, may or may not be present. Some products may not follow the Generic Marking. MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 98AON26320HDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1WLCSP4 0.75X0.75X0.3 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2021 www.onsemi.com
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