N20A

DP8303A NSC | Alldatasheet

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Y 8-bit directional data flow reduces system package count Y Bidirectional TRI-STATE inputs/outputs interface with bus oriented systems Y PNP inputs reduce input loading Y Output high voltage interfaces with TTL, MOS, and CMOS Y 48 mA/300 pF bus drive capability Y Pinouts simplify system interconnections Y Transmit/Receive and chip disable simplify control logic Y Compact 20-pin dual-in-line package Y Bus port glitch free power up/down Logic and Connection Diagrams TL/F/5856–1 Dual-In-Line Package TL/F/5856–2 Top View Order Number DP8303AN See NS Package Number N20A Logic Table Inputs Resulting Conditions Chip Disable Transmit/Receive A Port B Port OUT IN IN OUT X TRI-STATE TRI-STATE X e Don’t care TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1996 National Semiconductor Corporation RRD-B30M36/Printed in U. S. A. http://www.national.com

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage 5.5V Output Voltage 5.5V Maximum Power Dissipation* at 25§C Cavity Package 1667 mW Molded Package 1832 mW *Derate cavity package 11.1 mW/§C above 25§C; derate molded package 14.7 mW/§C. Storage Temperature b65§C to a150§C Lead Temperature (soldering, 4 seconds) 260§C Recommended Operating Conditions Min Max Units Supply Voltage (VCC) DP8303A 4.75 5.25 V Temperature (TA) DP8303A Symbol Parameter Conditions Min Typ Max Units A PORT (A0–A7) VIH Logical ‘‘1’’ Input Voltage CD e VIL, T/R e 2.0V 2.0 V VIL Logical ‘‘0’’ Input Voltage CD e VIL, T/R e 2.0V 0.7 V VOH Logical ‘‘1’’ Output Voltage CD e T/R e VIL IOH e b0.4 mA VCC b 1.15 VCC b 0.7 V VIL e 0.5V IOH e b3 mA 2.7 3.95 V VOL Logical ‘‘0’’ Output Voltage CD e T/R e VIL IOL e 16 mA 0.35 0.5 V VIL e 0.5V IOL e 8 mA 0.3 0.4 V IOS Output Short Circuit CD e VIL, T/R e VIL, VO e 0V, b10 b38 b75 mA Current VCC e Max, (Note 4) IIH Logical ‘‘1’’ Input Current CD e VIL, T/R e 2.0V, VIH e 2.7V 0.1 mA II Input Current at Maximum CD e 2.0V, VCC e Max, VIH e 5.25V mA Input Voltage IIL Logical ‘‘0’’ Input Current CD e VIL, T/R e 2.0V, VIN e 0.4V b70 b200 mA VCLAMP Input Clamp Voltage CD e 2.0V, IIN e b12 mA b0.7 b1.5 V IOD Output/Input CD e 2.0V VIN e 0.4V b200 mA TRI-STATE Current VIN e 4.0V mA B PORT (B0–B7) VIH Logical ‘‘1’’ Input Voltage CD e VIL, T/R e VIL 2.0 V VIL Logical ‘‘0’’ Input Voltage CD e VIL, T/R e VIL 0.7 V VOH Logical ‘‘1’’ Output Voltage CD e VIL, T/R e 2.0V IOH e b0.4 mA VCC b 1.15 VCC b0.8 V VIL e 0.5V IOH e b5 mA 2.7 3.9 V IOH e b10 mA 2.4 3.6 V VOL Logical ‘‘0’’ Output Voltage CD e VIL, T/R e 2.0V IOL e 20 mA 0.3 0.4 V IOL e 48 mA 0.4 0.5 V IOS Output Short Circuit CD e VIL, T/R e 2.0V, VO e 0V, b25 b50 b150 mA Current VCC e Max, (Note 4) IIH Logical ‘‘1’’ Input Current CD e VIL, T/R e VIL, VIH e 2.7V 0.1 mA II Input Current at Maximum CD e 2.0V, VCC e Max, VIH e 5.25V mA Input Voltage IIL Logical ‘‘0’’ Input Current CD e VIL, T/R e VIL, VIN e 0.4V b70 b200 mA VCLAMP Input Clamp Voltage CD e 2.0V, IIN e b12 mA b0.7 b1.5 V IOD Output/Input CD e 2.0V VIN e 0.4V b200 mA TRI-STATE Current VIN e 0.4V a200 mA http://www.national.com

CONTROL INPUTS CD, T/R VIH Logical ‘‘1’’ Input Voltage 2.0 V VIL Logical ‘‘0’’ Input Voltage 0.7 V IIH Logical ‘‘1’’ Input Current VIH e 2.7V 0.5 mA II Maximum Input Current VCC e Max, VIH e 5.25V 1.0 mA IIL Logical ‘‘0’’ Input Current VIL e 0.4V T/R b0.1 b0.25 mA CD b0.25 b0.5 mA VCLAMP Input Clamp Voltage IIN e b12 mA b0.8 b1.5 V POWER SUPPLY CURRENT ICC Power Supply Current CD e 2.0V, VIN, VCC e Max 100 mA CD e 0.4V, VINA e T/R e 2V, VCC e Max 100 150 mA Symbol Parameter Conditions Min Typ Max Units A PORT DATA/MODE SPECIFICATIONS tPDHLA Propagation Delay to a Logical ‘‘0’’ from CD e 0.4V, T/R e 0.4V(Figure A) ns B Port to A Port R1 e 1k, R2 e 5k, C1 e 30 pF tPDLHA Propagation Delay to a Logical ‘‘1’’ from CD e 0.4V, T/R e 0.4V(Figure A) ns B Port to A Port R1 e 1k, R2 e 5k, C1 e 30 pF tPLZA Propagation Delay from a Logical ‘‘0’’ to B0 to B7 e 2.4V, T/R e 0.4V(Figure C) ns TRI-STATE from CD to A Port S3 e 1, R5 e 1k, C4 e 15 pF tPHZA Propagation Delay from a Logical ‘‘1’’ to B0 to B7 e 0.4V, T/R e 0.4V(Figure C) ns TRI-STATE from CD to A Port S3 e 0, R5 e 1k, C4 e 15 pF tPZLA Propagation Delay from TRI-STATE to B0 to B7 e 2.4V, T/R e 0.4V(Figure C) ns a Logical ‘‘0’’ from CD to A Port S3 e 1, R5 e 1k, C4 e 30 pF tPZHA Propagation Delay from TRI-STATE to B0 to B7 e 0.4V, T/R e 0.4V(Figure C) ns a Logical ‘‘1’’ from CD to A Port S3 e 0, R5 e 5k, C4 e 30 pF B PORT DATA/MODE SPECIFICATIONS tPDHLB Propagation Delay to a Logical ‘‘0’’ from CD e 0.4V, T/R e 2.4V(Figure A) ns A Port to B Port R1 e 100X, R2 e 1k, C1 e 300 pF ns R1 e 667X, R2 e 5k, C1 e 45 pF tPDLHB Propagation Delay to a Logical ‘‘1’’ from CD e 0.4V, T/R e 2.4V(Figure A) ns A Port to B Port R1 e 100X, R2 e 1k, C1 e 300 pF ns R1 e 667X, R2 e 5k, C1 e 45 pF tPLZB Propagation Delay from a Logical ‘‘0’’ to A0 to A7 e 2.4V, T/R e 2.4V(Figure C) ns TRI-STATE from CD to B Port S3 e 1, R5 e 1k, C4 e 15 pF tPHZB Propagation Delay from a Logical ‘‘1’’ to A0 to A7 e 0.4V, T/R e 2.4V(Figure C) ns TRI-STATE from CD to B Port S3 e 0, R5 e 1k, C4 e 15 pF tPLZB Propagation Delay from TRI-STATE to A0 to A7 e 2.4V, T/R e 2.4V(Figure C) ns a Logical ‘‘0’’ from CD to B Port S3 e 1, R5 e 100X, C4 e 300 pF ns S3 e 1, R5 e 667X, C4 e 45 pF tPZHB Propagation Delay from TRI-STATE to A0 to A7 e 0.4V, T/R e 2.4V(Figure C) ns a Logical ‘‘1’’ from CD to B Port S3 e 0, R5 e 1k, C4 e 300 pF ns S3 e 0, R5 e 5kX, C4 e 45 pF http://www.national.com

TRANSMIT/RECEIVE MODE SPECIFICATIONS tTRL Propagation Delay from Transmit Mode to CD e 0.4V(Figure B) Receive a Logical ‘‘0’’, T/R to A Port S1 e 1, R4 e 100X, C3 e 5 pF ns S2 e 1, R3 e 1k, C2 e 30 pF tTRH Propagation Delay from Transmit Mode to CD e 0.4V(Figure B) Receive a Logical ‘‘1’’, T/R to A Port S1 e 0, R4 e 100X, C3 e 5 pF ns S2 e 0, R3 e 5k, C2 e 30 pF tRTL Propagation Delay from Receive Mode to CD e 0.4V(Figure B) Transmit a Logical ‘‘0’’, T/R to B Port S1 e 1, R4 e 100X, C3 e 300 pF ns S2 e 1, R3 e 300X, C2 e 5 pF tRTH Propagation Delay from Receive Mode to CD e 0.4V (Figure B) Transmit a Logical ‘‘1’’, T/R to B Port S1 e 0, R4 e 1k, C3 e 300 pF ns S2 e 0, R3 e 300X, C2 e 5 pF Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: Unless otherwise specified, min/max limits apply across the supply and temperature range listed in the table of Recommended Operating Conditions. All typical values given are for VCC e 5V and TA e 25§C. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 4: Only one output at a time should be shorted. Switching Time Waveforms and AC Test Circuits TL/F/5856–3 TL/F/5856–4 Note: C1 includes test fixture capacitance. FIGURE A. Propagation Delay from A Port to B Port or from B Port to A Port http://www.national.com

Switching Time Waveforms and AC Test Circuits (Continued) TL/F/5856–5 TL/F/5856–6 Note: C2 ad C3 include test fixture capacitance. FIGURE B. Propagation Delay from T/R to A Port or B Port TL/F/5856–7 TL/F/5856–8 Note: C4 includes test fixture capacitance. Port input is in a fixed logical condition. See AC table. FIGURE C. Propagation Delay to/from TRI-STATE from CD to A Port or B Port http://www.national.com

DP8303A 8-Bit TRI-STATE Bidirectional Transceiver (Inverting) Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number DP8303AN LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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