N1308

NCP1308 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

• Free−Running Borderline/Critical Mode Quasi−Resonant Operation
• Current−Mode with Adjustable Skip Cycle Capability
• Dynamic Self−Supply Type of V CC
• Auto−Recovery Overcurrent Protection
• Improved UVLO for VCC below 10 V
• Latching Overvoltage Protection on V CC
• 500 mA Peak Current Source/Sink Capability
• Internal 1.0 ms Soft−Start
• Internal 10 /C0109s Minimum TOFF
• Adjustable Skip Level
• Internal Temperature Shutdown
• Internal Leading Edge Blanking
• Direct Optocoupler Connection
• SPICE Models Available for TRANsient Analysis
• This is a Pb−Free Device Typical Applications
• AC−DC Adapters for Notebooks, etc.
• Offline Battery Chargers
• Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.) http://onsemi.com SOIC−8 DR SUFFIX CASE 751 PIN CONNECTIONS MARKING DIAGRAM A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071= Pb−Free Package 1Dmg 8 HV 2FB 3CS 4GND

6 VCC

5 Drv

(T op View) 1308 ALYW /C0071 Device Package Shipping †

ORDERING INFORMATION

NCP1308DR2G SOIC−8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

Figure 1. Typical Application Schematic

12 V @ 1 A

Y1 Type*Please refer to the application information section. 1 Dmg Core reset detection The auxiliary FLYBACK signal ensures discontinuous operation. skip level, the device shuts off.

3 CS Current sense input and skip

4 GND The IC ground −

5 Drv Driving pulses The driver’s output to an external MOSFET. winding brings this pin above 16 V typical, the circuit permanently latches off. 7 NC − This unconnected pin ensures adequate creepage distance.

Figure 2. Internal Circuit Architecture

5.3 V (Fault)

may occur and reliability may be affected.

http://onsemi.com ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C, VCC = 11 V unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit DYNAMIC SELF SUPPLY VCC Increasing Level at which the Current Source Turns−Off 6 VCCOFF 10.8 12 12.9 V VCC Decreasing Level at which the Current Source Turns−On 6 VCCON 9.1 10 10.6 V VCC Decreasing Level at which the Latchoff Phase Ends 6 VCClatch − 5.3 − V VCC Level at which pulses are disabled 6 VUVLO − VCCON − 200 mV − V Internal IC Consumption, No Output Load on Pin 5, FSW = 60 kHz 6 ICC1 − 1.0 1.3 (Note 1) mA Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 60 kHz 6 ICC2 − 1.6 2.0 (Note 1) mA Internal IC Consumption, Latchoff Phase, VCC = 6.0 V 6 ICC3 − 330 − /C0109A INTERNAL STARTUP CURRENT SOURCE ( TJ = 0°C) High−Voltage Current Source, VCC = 10 V 8 IC1 4.3 7.0 9.6 mA High−Voltage Current Source, VCC = 0 8 IC2 − 8.0 − mA DRIVE OUTPUT Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Output Signal 5 Tr − 40 − ns Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Output Signal 5 Tf − 20 − ns Source Resistance 5 ROH 12 20 36 /C0087 Sink Resistance 5 ROL 5.0 10 20 /C0087 CURRENT COMPARATOR Input Bias Current @ 1.0 V Input Level on Pin 3 3 IIB − 0.02 − /C0109A Maximum Internal Current Setpoint 3 ILimit 0.92 1.0 1.12 V Propagation Delay from Current Detection to Gate OFF State 3 TDEL − 100 160 ns Leading Edge Blanking Duration 3 TLEB − 380 − ns Internal Current Offset Injected on the CS Pin During OFF Time 3 Iskip − 200 − /C0109A OVERVOLTAGE SECTION Voltage on the VCC above which the controller latches off 6 VOVP 14.3 16 17.8 V Integration Time Constraint on the OVP comparator 6 Tint − 50 − /C0109s FEEDBACK SECTION (VCC = 11 V, Pin 5 loaded by 1.0 k/C0087) Internal Pullup Resistor 2 Rup − 20 − k/C0087 Pin 3 to Current Setpoint Division Ratio − Iratio − 3.3 − − Internal Soft−Start − Tss − 1.0 − ms DEMAGNETIZATION DETECTION BLOCK Input Threshold Voltage (Vpin 1 Decreasing) 1 Vth 35 50 90 mV Hysteresis (Vpin 1 Decreasing) 1 VH − 20 − mV Input Clamp Voltage High State (Ipin 1 = 3.0 mA) Low State (Ipin 1 = −2.0 mA) VCH VCL 8.0 −0.9 −0.7 −0.5 V Dmg Propagation Delay 1 Tdem − 210 − ns Internal Input Capacitance at Vpin 1 = 1.0 V 1 Cpar − 10 − pF Minimum TOFF (Internal Blanking Delay After TON) 1 Tblank − 10 − /C0109s Timeout After Last Dmg Transition 1 Tout − 5.0 − /C0109s 1. Max value at T J = 0°C, please see characterization curves.

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APPLICATION INFORMATION

The NCP1308 implements a standard current mode architecture where the switch−off time is dictated by the peak current setpoint, whereas the core reset detection triggers the turn−on event. This component represents the ideal candidate where low part−count is the key parameter, particularly in low−cost AC/DC adapters, consumer electronics, auxiliary supplies, etc. Due to its high−performance High−V oltage technology, the NCP1308 incorporates all the necessary components/features needed to build a rugged and reliable Switch−Mode Power Supply (SMPS):

• Transformer Core Reset Detection: Borderline/critical operation is ensured whatever the operating conditions are. As a result, there are virtually no primary switch turn−on losses and no secondary diode recovery losses. The converter also stays a first−order system and accordingly eases the feedback loop design.
• Quasi−Resonant Operation: By delaying the turn−on event, it is possible to restart the MOSFET in the minimum of the drain−source wave, ensuring reduced EMI/video noise perturbations. In nominal power conditions, the NCP1308 operates in Borderline Conduction Mode (BCM) also called Critical Conduction Mode (CCM).
• Dynamic Self−Supply (DSS): Due to its V ery High V oltage Integrated Circuit (VHVIC) technology, ON Semiconductor ’s NCP1308 allows for a direct pin connection to the high−voltage DC rail. A dynamic current source charges up a capacitor and thus provides a fully independent V CC level to the NCP1308. As a result, there is no need for an auxiliary winding to supply the IC, whose management is always a problem in variable output voltage designs (e.g. battery chargers).
• Overvoltage Protection (OVP): B y monitoring the VCC pin via a 50 /C0109s time constant filter, the NCP1308 goes into latched fault condition whenever an overvoltage condition is detected. This occurs if V CC goes above 16 V typically. The controller stays fully latched in this position until the V CC is cycled down to 4 V , e.g. when the user unplugs the power supply from the mains outlet and re−plugs it.
• Adjustable Skip Cycle Level: By offering the ability to tailor the level at which the skip cycle takes place, the designer can make sure that the skip operation only occurs at low peak current. This point guarantees a noise−free operation with cheap transformer. This option also offers the ability to fix the maximum switching frequency when entering light load conditions.
• Overcurrent Protection (OCP): By continuously monitoring the FB line activity, NCP1308 enters burst mode as soon as the power supply undergoes an overload. The device enters a safe low power operation that prevents from any lethal thermal runaway. As soon as the default disappears, the power supply resumes operation. Unlike other controllers, overload detection is performed independently of any auxiliary winding level. In presence of a bad coupling between both power and auxiliary windings, the short circuit detection can be severely affected. The DSS naturally shields you against these troubles. Dynamic Self−Supply The DSS principle is based on the charge/discharge of the VCC bulk capacitor from a low level up to a higher level. We can easily describe the current source operation with some simple logical equations: POWER−ON: IF VCC < VCCOFF THEN Current Source is ON, no output pulses IF VCC decreasing > VCC ON THEN Current Source is OFF, output is pulsing IF VCC increasing < VCC OFF THEN Current Source is ON, output is pulsing Typical values are: VCCOFF = 12 V , VCCON = 10 V To better understand the operational principle, the diagram in Figure 12 offers the necessary light: Vripple = 2V VCC OFF = 12V VCC ON = 10V ON OFF Output pulses VCCCURRENT SOURCE

Figure 12. The Charge/Discharge Cycle over a 10 /C0109F

Figure 21. A Simple Bipolar Transistor Totally The SOIC package offers a 178 °C/W thermal resistor. or 6.5 mm x 6.5 mm with 70 /C0109m copper thickness (2 oz).

1. Avoid negative spikes at turn−off on the HV pin
2. Split the power budget between this resistor and

the time it stays off (DSSduty−cycle = on/(on + off) ). available at www.onsemi.com/pub/ncp1200. is interesting to implement a true short−circuit protection. note that this can also happen in case of feedback loss, e.g. NCP1308 hosts a dedicated overload detection circuitry. when the fault condition disappears. device internally watches for an overload current situation.

http://onsemi.com If the fault is relaxed during the VCC natural fall down sequence, the IC automatically resumes. If the fault still persists when VCC reached VCCON, then the controller cuts everything off until recovery. Figure 22. TIME TIME TIME INTERNAL FAULT FLAG VCC 12 V 10 V 5.3 V DRV DRIVER PULSES FAULT IS RELAXED FAULT OCCURS HERESTARTUP PHASE REGULATION OCCURS HERE LATCHOFF PHASE Soft−Start The NCP1308 features an internal 1ms soft−start to soften the constraints occurring in the power supply during startup. It is activated during the power on sequence. As soon as V CC reaches VCCOFF, the peak current is gradually increased from nearly zero up to the maximum clamping level (e.g. 1.0 V). The soft−start is also activated during the over current burst (OCP) sequence. Every restart attempt is followed by a soft−start activation. Generally speaking, the soft−start will be activated when V CC ramps up either from zero (fresh power−on sequence) or 5.3 V , the latchoff voltage occurring during OCP . Calculating the VCC Capacitor As the above section describes, the fall down sequence depends upon the VCC level: how long does it take for the VCC line to go from 12 V to 10 V? The required time depends on the startup sequence of your system, i.e. when you first apply the power to the IC. The corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 12 V to 10 V , otherwise the supply will not properly start. The test consists in either simulating or measuring in the lab how much time the system takes to reach the regulation at full load. Let’s suppose that this time corresponds to 6ms. Therefore a V CC fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. If the corresponding IC consumption, including the MOSFET drive, establishes at 1.6 mA (e.g. with a 10 nC Qg), we can calculate the required capacitor using the following formula: /C0068t /C0043/C0068V /C0064C i , with ΔV = 2 V . Then for a wanted Δt of 10 ms, C equals 9 /C0109F or 22 /C0109F for a standard value. When an overload condition occurs, the IC blocks its internal circuitry and its consumption drops to 330 /C0109A typical. This happens at V CC = 10 V and it remains stuck until V CC reaches 5.3 V: we are in latchoff phase. Again, using the calculated 22 /C0109F and 330 /C0109A current consumption, this latchoff phase lasts: 313 ms.

Figure 27. The short−circuit protection forces the IC to enter burst in presence of a secondary overload.

http://onsemi.com PACKAGE DIMENSIONS SOIC−8 DR SUFFIX CASE 751−07 ISSUE AG SEATING PLANE N J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A B S DH C 0.10 (0.004) DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −X− −Y− G MYM0.25 (0.010) −Z− YM0.25 (0.010) Z S X S M /C0095/C0095/C0095/C0095 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 /C0466mm inches/C0467SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 NCP1308/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.