N08L63W2A ONSEMI | Alldatasheet

Document overview

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Technical content

Features

  • Single Wide Power Supply Range 2.3 to 3.6 Volts
  • Very low standby current 4.0µA at 3.0V (Typical)
  • Very low operating current 2.0mA at 3.0V and 1µs(Typical)
  • Very low Page Mode operating current 1.0mA at 3.0V and 1µs (Typical)
  • Simple memory control Dual Chip Enables (CE1 and CE2) Byte control for independent byte operation Output Enable (OE ) for memory expansion
  • Low voltage data retention Vcc = 1.8V
  • Very fast output enable access time 25ns OE access time
  • Very fast Page Mode access time tAAP = 25ns
  • Automatic power down to standby mode
  • TTL compatible three-state output driver Pin Configuration Product Family Part Number Package Type Operating Temperature Power Supply (Vcc) Speed Standby Current (ISB), Typical Operating Current (Icc), Typical N08L63W2AB 48 - BGA -40oC to +85oC 2.3V - 3.6V 70ns@2.7V 85ns @ 2.3V 4 µA2 m A @ 1 M H z N08L63W2AB2 48 - BGA Green 123456 A LB OE A0 A 1 A2 CE2 B I/O8 UB A3 A 4 CE1 I/O0 C I/O9 I/O 10 A 5 A 6 I/O 1 I/O 2 D VSS I/O11 A 17 A7 I/O3 VCC E VCC I/O12 NC A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC

48 Pin BGA (top)

CE1, CE2 Chip Enable Input OE Output Enable Input LB Lower Byte Enable Input UB Upper Byte Enable Input I/O0-I/O15 Data Inputs/Outputs VCC Power VSS Ground NC Not Connected

Rev. 8 | Page 2 of 10 | www.onsemi.com N08L63W2A Functional Block Diagram Functional Description CE1 CE2 WE OE UB LB I/O0 - I/O15 1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. MODE POWER HXXXXX H i g h Z Standby2 2. When the device is in standby mode, control inputs (WE , OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. Standby XLXXXX H i g h Z Standby2 Standby XXXXHH H i g h Z Standby2 Standby LHL X3 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. L1 L1 Data In Write3 Active LHHL L1 L1 Data Out Read Active LHHH L1 L1 High Z Active Active Capacitance1 1. These parameters are verified in device characterization and are not 100% tested Item Symbol Test Condition Min Max Unit Input Capacitance CIN VIN = 0V, f = 1 MHz, TA = 25oC 8p F I/O Capacitance CI/O VIN = 0V, f = 1 MHz, TA = 25oC 8p F Address Inputs A0 - A3 Address Inputs A4 - A18 Word Address Decode Logic 32K Page x 16 word x 16 bit RAM Array Word Mux Input/ Output Mux and Buffers Page Address Decode Logic Control Logic CE1 CE2 WE OE UB LB I/O0 - I/O7 I/O8 - I/O15

Rev. 8 | Page 3 of 10 | www.onsemi.com N08L63W2A Absolute Maximum Ratings1 1. Stresses greater than those listed above may cause permanent dam age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Item Symbol Rating Unit Voltage on any pin relative to VSS VIN,OUT –0.3 to VCC+0.3 V Voltage on VCC Supply Relative to VSS VCC –0.3 to 4.5 V Power Dissipation PD 500 mW Storage Temperature TSTG –40 to 125 oC Operating Temperature TA -40 to +85 oC Soldering Temperature and Time TSOLDER 260oC, 10sec oC Operating Characteristics (Over Specified Temperature Range) Item Symbol Test Conditions Min. Typ1 1. Typical values are measured at Vcc=Vcc Typ., T A=25°C and not 100% tested. Max Unit Supply Voltage VCC 2.3 3.0 3.6 V Data Retention Voltage VDR Chip Disabled3 1.8 V Input High Voltage VIH 1.8 VCC+0.3 V Input Low Voltage VIL –0.3 0.6 V Output High Voltage VOH IOH = 0.2mA V CC–0.2 V Output Low Voltage VOL IOL = -0.2mA 0.2 V Input Leakage Current ILI VIN = 0 to VCC 0.5 µA Output Leakage Current ILO OE = VIH or Chip Disabled 0.5 µA Read/Write Operating Supply Current @ 1 µs Cycle Time2 2. This parameter is specified with the out puts disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. ICC1 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 2.0 3.0 mA Read/Write Operating Supply Current @ 70 ns Cycle Time2 ICC2 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 9.0 15.0 mA Page Mode Operating Supply Current @ 70ns Cycle Time2 (Refer to Power Savings with Page Mode Operation diagram) ICC3 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 2.0 3.0 mA Read/Write Quiescent Operating Sup- ply Current3 3. This device assumes a standby m ode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS. ICC4 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0, f = 0 3.0 mA Maximum Standby Current3 ISB1 VIN = VCC or 0V Chip Disabled tA= 85oC, VCC = 3.6 V 4.0 20.0 µA Maximum Data Retention Current3 IDR Vcc = 1.8V, VIN = VCC or 0 Chip Disabled, tA= 85oC 10 µA

Rev. 8 | Page 4 of 10 | www.onsemi.com N08L63W2A Power Savings with Page Mode Operation (WE = VIH) Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs. Page Address (A4 - A18) LB , UB OE CE1 CE2 Word Address (A0 - A3) Open page Word 1 Word 2 Word 16...

Rev. 8 | Page 5 of 10 | www.onsemi.com N08L63W2A Timing Test Conditions Item Input Pulse Level 0.1VCC to 0.9 VCC Input Rise and Fall Time 5ns Input and Output Timing Reference Levels 0.5 VCC Output Load CL = 30pF Operating Temperature -40 to +85 oC Timing Item Symbol Units Min. Max. Min. Max. Read Cycle Time tRC 85 70 ns Address Access Time (Random Access) tAA 85 70 ns Address Access Time (Page Mode) tAAP 30 25 ns Chip Enable to Valid Output tCO 85 70 ns Output Enable to Valid Output tOE 30 25 ns Byte Select to Valid Output tLB, tUB 85 70 ns Chip Enable to Low-Z output tLZ 10 10 ns Output Enable to Low-Z Output tOLZ 55 n s Byte Select to Low-Z Output tLBZ, tUBZ 10 10 ns Chip Disable to High-Z Output tHZ 02 002 0 n s Output Disable to High-Z Output tOHZ 02 002 0 n s Byte Select Disable to High-Z Output tLBHZ, tUBHZ 02 002 0 n s Output Hold from Address Change tOH 55 n s Write Cycle Time tWC 85 70 ns Chip Enable to End of Write tCW 50 50 ns Address Valid to End of Write tAW 50 50 ns Byte Select to End of Write tLBW, tUBW 50 50 ns Write Pulse Width tWP 40 40 ns Address Setup Time tAS 00 n s Write Recovery Time tWR 00 n s Write to High-Z Output tWHZ 20 20 ns Data to Write Time Overlap tDW 40 40 ns Data Hold from Write Time tDH 00 ns End Write to Low-Z Output tOW 55 n s

Rev. 8 | Page 6 of 10 | www.onsemi.com N08L63W2A Timing of Read Cycle (CE1 = OE = VIL, WE = CE2 = VIH) Timing Waveform of Read Cycle (WE=VIH) Address Data Out tRC tAA, tAAP tOH Data ValidPrevious Data Valid Address LB, UB OE Data Valid tRC tAA, tAAP tCO tHZ tOHZ tLBHZ, tUBHZ tOLZ tOE tLZ High-Z Data Out tLB, tUB tLBLZ, tUBLZ CE1 CE2

Rev. 8 | Page 7 of 10 | www.onsemi.com N08L63W2A Timing Waveform of Page Mode Read Cycle (WE = VIH) Page Address (A4 - A17) LB, UB OE tAA tCO tHZ tOHZ tLBHZ, tUBHZ tOLZ tOE High-Z Data Out tLB, tUB tLBLZ, tUBLZ CE1 CE2 Word Address (A0 - A3) tAAP tRC

Rev. 8 | Page 8 of 10 | www.onsemi.com N08L63W2A Timing Waveform of Write Cycle (WE control) Timing Waveform of Write Cycle (CE1 Control) Address Data In CE1 CE2 LB, UB Data Valid tWC tAW tCW tWR tWHZ tDH High-Z WE Data Out High-Z tOW tAS tWP tDW tLBW, tUBW Address WE Data Valid tWC tAW tCW tWR tDH LB, UB Data In High-Z tAS tWP tLZ tDW tLBW, tUBW Data Out tWHZ CE1 (for CE2 Control, use inverted signal)

Rev. 8 | Page 9 of 10 | www.onsemi.com N08L63W2A Ball Grid Array Package Dimensions (mm) DE e = 0.75 BALL MATRIX TYPESD SE J K SIDE VIEWTOP VIEW BOTTOM VIEW E D A1 BALL PAD CORNER (3) 1.10±0.10 0.20±0.05 0.15 0.05 Z Z 1. 0.30±0.05 DIA. 1. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER. PARALLEL TO PRIMARY Z. 2. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. A1 BALL PAD CORNER I.D. TO BE MARKED BY INK. 2. SEATING PLANE - Z SD SE e K TYP J TYP e A1 BALL PAD CORNER

Rev. 8 | Page 10 of 10 | www.onsemi.com N08L63W2A

Ordering Information

Part Number Package Shipping Method N08L63W2AB7I Leaded 48-BGA Tray N08L63W2AB27I Green 48-BGA (RoHS Compliant) Tray N08L63W2AB7IT Leaded 48-BGA Tape & Reel N08L63W2AB27IT Green 48-BGA (RoHS Compliant) Tape & Reel

Revision History

Revision Date Change Description A Jan. 2001 Initial Advance Release B Feb. 2001 Deleted TSOP package, Re vised BGA drawing, misc. errrata C Dec. 2001 Part number change from EM512J16, modified Overview and Features, revised Operating Characteristics table, Package diagram, Functional Description table and Ordering Information diagram D Nov. 2002 Replaced Isb and Icc on Product Family table with typical values E Oct 2004 Added Green Package Option F Dec. 2005 Added RoHS compliant G September 2006 Converted to AMI Semiconductor

8 July 2008 Converted to ON Semiconductor and new part numbers

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