N02L6181A ONSEMI | Alldatasheet

Document overview

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Technical content

Features

  • Single Wide Power Supply Range 1.65 to 2.2 Volts
  • Very low standby current 0.5µA at 1.8V (Typical)
  • Very low operating current 1.4mA at 1.8V and 1µs (Typical)
  • Very low Page Mode operating current 0.5mA at 1.8V and 1µs (Typical)
  • Simple memory control Single Chip Enable (CE) Byte control for independent byte operation Output Enable (OE ) for memory expansion
  • Low voltage data retention Vcc = 1.2V
  • Very fast output enable access time 30ns OE access time
  • Automatic power down to standby mode
  • TTL compatible three-state output driver
  • Compact space saving BGA package Product Family Part Number Package Type Operating Temperature Power Supply (Vcc) Speed Standby Current (ISB), Max Operating Current (Icc), Max N02L6181AB 48 - BGA -40oC to +85oC 1.65V - 2.2V 70 and 85ns @ 1.65V 10 µA3 m A @ 1 M H z N02L6181AB2 Green 48-BGA

Rev. 4 | Page 2 of 11 | www.onsemi.com N02L6181A Pin Configurations Pin Descriptions Pin Name Pin Function A0-A16 Address Inputs WE Write Enable Input CE Chip Enable Input OE Output Enable Input LB Lower Byte Enable Input UB Upper Byte Enable Input I/O0-I/O15 Data Inputs/Outputs NC Not Connected VCC Power VSS Ground 123456 A LB OE A0 A 1 A2 NC B I/O8 UB A3 A 4 CE I/O0 C I/O9 I/O 10 A 5 A 6 I/O 1 I/O 2 D VSS I/O11 NC A7 I/O3 VCC E VCC I/O12 NC A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC

48 Pin BGA (top)

Rev. 4 | Page 3 of 11 | www.onsemi.com N02L6181A Functional Block Diagram Functional Description CE WE OE UB LB I/O0 - I/O15 1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. MODE POWER HXXXX H i g h Z Standby2 2. When the device is in standby mode, control inputs (WE , OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. Standby L X X H H High Z Standby2 Standby LL X3 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. L1 L1 Data In Write3 Active LHL L1 L1 Data Out Read Active LHH L1 L1 High Z Active Active Capacitance1 1. These parameters are verified in device characterization and are not 100% tested Item Symbol Test Condition Min Max Unit Input Capacitance CIN VIN = 0V, f = 1 MHz, TA = 25oC 8p F I/O Capacitance CI/O VIN = 0V, f = 1 MHz, TA = 25oC 8p F I/O8 - I/O15 Control Logic Page Decode Logic Address Inputs A4 - A16 Input/ Output Mux and Buffers I/O0 - I/O7 Address Word Decode Logic AddressAddress InputsA0 - A3 8K Page x 16 word x 16 bit RAM Array Word Mux CE WE OE UB LB

Rev. 4 | Page 4 of 11 | www.onsemi.com N02L6181A Absolute Maximum Ratings1 Item Symbol Rating Unit Voltage on any pin relative to VSS VIN,OUT –0.3 to VCC+0.3 V Voltage on VCC Supply Relative to VSS VCC –0.3 to 3.0 V Power Dissipation PD 500 mW Storage Temperature TSTG –40 to 125 oC Operating Temperature TA -40 to +85 oC Soldering Temperature and Time TSOLDER 240oC, 10sec(Lead only) oC 1. Stresses greater than those listed above may cause permanent da mage to the device. This is a stress rating only and functiona l operation of the device at these or any ot her conditions above those indicated in the operating se ction of this specification i s not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Characteristics (Over Specified Temperature Range) Item Symbol Test Conditions Min. Typ1 1. Typical values are measured at Vcc=Vcc Typ., T A=25°C and are not 100% tested. Max Unit Supply Voltage VCC 1.65 1.8 2.2 V Data Retention Voltage VDR Chip Disabled2 1.2 2.2 V Input High Voltage VIH 0.7Vcc VCC+0.3 V Input Low Voltage VIL –0.3 0.3Vcc V Output High Voltage VOH IOH = 0.2mA V CC–0.2 V Output Low Voltage VOL IOL = -0.2mA 0.3 V Input Leakage Current ILI VIN = 0 to VCC 0.5 µA Output Leakage Current ILO OE = VIH or Chip Disabled 0.5 µA Read/Write Operating Supply Current @ 1 µs Cycle Time2 2. This parameter is specified with the ou tputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. ICC1 VCC=2.2 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 1.4 3.0 mA Read/Write Operating Supply Current @ 70 ns Cycle Time2 ICC2 VCC=2.2 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 8.0 17.0 mA Page Mode Operating Supply Current @ 70ns Cycle Time2 (Refer to Power Savings with Page Mode Operation diagram) ICC3 VCC=2.2V, VIN=VIH or VIL Chip Enabled, IOUT = 0 2.0 4.0 mA Read/Write Quiescent Operating Sup- ply Current3 3. This device assumes a standby m ode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS ICC4 VCC=2.2V, VIN=VIH or VIL Chip Enabled, IOUT = 0, f = 0 0.1 mA Maximum Standby Current3 ISB1 VIN = VCC or 0V Chip Disabled tA= 85oC, VCC = 2.2 V 0.5 10.0 µA Maximum Data Retention Current3 IDR VCC = 1.2V, VIN = VCC or 0 Chip Disabled, tA= 85oC 5.0 µA

Rev. 4 | Page 5 of 11 | www.onsemi.com N02L6181A Power Savings with Page Mode Operation (WE = VIH) Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs. Page Address (A4 - A16 ) LB , UB OE CE Word Address (A0 - A3) Open page Word 1 Word 2 Word 16...

Rev. 4 | Page 6 of 11 | www.onsemi.com N02L6181A Timing Test Conditions Item Input Pulse Level 0.1VCC to 0.9 VCC Input Rise and Fall Time 5ns Input and Output Timing Reference Levels 0.5 VCC Output Load CL = 30pF Power Supply Voltage 1.65 - 2.2V Operating Temperature -40 to +85 oC Timing Item Symbol 85ns 70ns Units Min. Max. Min. Max. Read Cycle Time tRC 85 70 ns Address Access Time tAA 85 70 ns Chip Enable to Valid Output tCO 85 70 ns Output Enable to Valid Output tOE 30 25 ns Byte Select to Valid Output tLB, tUB 85 70 ns Chip Enable to Low-Z output tLZ 10 10 ns Output Enable to Low-Z Output tOLZ 55 n s Byte Select to Low-Z Output tLBZ, tUBZ 10 10 ns Chip Disable to High-Z Output tHZ 30 25 ns Output Disable to High-Z Output tOHZ 30 25 ns Byte Select Disable to High-Z Output tLBHZ, tUBHZ 30 25 ns Output Hold from Address Change tOH 55 n s Write Cycle Time tWC 85 70 ns Chip Enable to End of Write tCW 50 40 ns Address Valid to End of Write tAW 50 40 ns Byte Select to End of Write tLBW, tUBW 50 40 ns Write Pulse Width tWP 50 40 ns Address Setup Time tAS 00 n s Write Recovery Time tWR 00 n s Write to High-Z Output tWHZ 25 20 ns Data to Write Time Overlap tDW 40 40 ns Data Hold from Write Time tDH 00 ns End Write to Low-Z Output tOW 10 10 ns

Rev. 4 | Page 7 of 11 | www.onsemi.com N02L6181A Timing of Read Cycle (CE = OE = VIL, WE = VIH) Timing Waveform of Read Cycle (WE= VIH) Address Data Out tRC tAA tOH Data ValidPrevious Data Valid Address LB, UB OE Data Valid tRC tAA tCO tHZ tOHZ tLBHZ, tUBHZ tOLZ tOE tLZ High-Z Data Out tLB, tUB tLBLZ, tUBLZ CE

Rev. 4 | Page 8 of 11 | www.onsemi.com N02L6181A Timing Waveform of Write Cycle (WE control) Timing Waveform of Write Cycle (CE Control) Address Data In CE LB, UB Data Valid tWC tAW tCW tWR tWHZ tDH High-Z WE Data Out High-Z tOW tAS tWP tDW tLBW, tUBW Address WE Data Valid tWC tAW tCW tWR tDH LB, UB Data In High-Z tAS tWP tLZ tDW tLBW, tUBW Data Out tWHZ CE

Rev. 4 | Page 9 of 11 | www.onsemi.com N02L6181A 44-Lead TSOP II Package (T44) Note: 1. All dimensions in inches (Millimeters) 2. Package dimensions exclude molding flash 18.41±0.13 10.16±0.13 SEE DETAIL B 1.10±0.15 11.76±0.20 0.45 0.30 0.80mm REF DETAIL B 0.80mm REF 0o-8o 0.20 0.00

Rev. 4 | Page 10 of 11 | www.onsemi.com N02L6181A Ball Grid Array Package Dimensions (mm) DE e = 0.75 BALL MATRIX TYPESD SE J K SIDE VIEWTOP VIEW BOTTOM VIEW E D A1 BALL PAD CORNER (3) 1.24±0.10 0.28±0.05 0.15 0.05 Z Z 1. 0.35±0.05 DIA. 1. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER. PARALLEL TO PRIMARY Z. 2. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. A1 BALL PAD CORNER I.D. TO BE MARKED BY INK. 2. SEATING PLANE - Z SD SE e K TYP J TYP e A1 BALL PAD CORNER

Rev. 4 | Page 11 of 11 | www.onsemi.com N02L6181A

Ordering Information

Part Number Package Shipping Method Speed N02L6181AB7I Leaded 48-BGA Tray 70ns N02L6181AB27I Green 48-BGA (RoHS Compliant) Tray 70ns N02L6181AB8I Leaded 48-BGA Tray 85ns N02L6181AB28I Green 48-BGA (RoHS Compliant) Tray 85ns N02L6181AB7IT Leaded 48-BGA Tape & Reel 70ns N02L6181AB27IT Green 48-BGA (RoHS Compliant) Tape & Reel 70ns N02L6181AB8IT Leaded 48-BGA Tape & Reel 85ns N02L6181AB28IT Green 48-BGA (RoHS Compliant) Tape & Reel 85ns

Revision History

Revision # Date Change Description A Apr. 2003 Initial Release B Nov. 2005 Added TSOP II Green Pkg. , Green Pkg. Part # and RoHS Compliant C September 2006 Converted to AMI Semiconductor

4 July 2008 Converted to ON Semiconductor and new part numbers

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