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Document overview
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- PDF pages: 12
Technical content
Features
- Power Supply Range: 1.7 to 2.2 V
- Very Low Typical Standby Current < 1 /C0109A
- Very Low Operating Current < 10 mA
- Simple Serial Interface ♦ Single-bit SPI Access ♦ DUAL-bit and QUAD-bit SPI-like Access
- Flexible Operating Modes ♦ Word Mode ♦ Page Mode ♦ Burst Mode (Full Array)
- High Frequency Read and Write Operation ♦ Clock Frequency 20 MHz
- Built-in Write Protection (CS High)
- High Reliability ♦ Unlimited Write Cycles
- These Devices are Pb−Free and are RoHS Compliant ♦ Green TSSOP
Table 1. DEVICE OPTIONS
ORDERING INFORMATION
N01S818HAT22I TSSOP −8 (Pb−Free)
100 Units / Tube
TSSOP8 3x4.4 CASE 948BH PACKAGE CONFIGURATION CS SO / SIO1 NC / SIO2 VSS VCC HOLD / SIO3 SCK SI / SIO0N01S818HAT22IT TSSOP −8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Table 2. PIN NAMES Figure 1. Functional Block Diagram Table 3. CONTROL SIGNAL DESCRIPTIONS high during a program cycle, the cycle will complete and then the device will enter standby mode. SI SPI Serial Data In Receives instructions, addresses and data on the rising edge of SCK. SO SPI Serial Data Out Data is transferred out after the falling edge of SCK. must be pulled high while the SCK pin is low. Lowering the HOLD input at any time will take to SO output to High-Z.
discrete I/O lines to operate the device. sampled on the first rising edge of SCK after CS goes low. instruction, the dual and quad access modes may be initiated. Mode operation is programmed. Table 4. INSTRUCTION SET out on the SIO0-3 pins while operating in these two modes. data is read out until the highest memory address is reached. Figure 2. SPI Read Sequence (Single Byte)
The serial SRAM WRITE is selected by enabling CS low. write the data on SI pin and continue to provide clock pulses. already stored in the memory locations. Figure 6. SPI Write Sequence
Figure 14. QUAD Write Mode Register Sequence Table 5. MODE REGISTER
0 Hold Function
1 Reserved
2 Reserved
3 Reserved
4 Reserved
5 Reserved
6 Operating Mode
The serial SRAM enters a know state at power-up time. level on CS is required to enter a active state. Table 6. ABSOLUTE MAXIMUM RATINGS Table 7. OPERATING CHARACTERISTICS (OVER SPECIFIED TEMPERATURE RANGE)
- Typical values are measured at V CC = VCC Typ., TA = 25°C and are not 100% tested.
- Typical lower limit of VCC when data will be retained in the memory array, not 100% tested.
Table 8. CAPACITANCE (Note 3)
- These parameters are verified in device characterization and are not 100% tested.
Table 9. TIMING TEST CONDITIONS Table 10. TIMING
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