MTV6N100E MOTOROLA | Alldatasheet

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1Motorola TMOS Power MOSFET Transistor Device Data /C0068/C0101/C0115/C0105/C0103/C0110/C0101/C0114/C0039/C0115 /C0068/C0097/C0116/C0097 /C0083/C0104/C0101/C0101/C0116 /C0084/C0077/C0079/C0083 /C0069/C0045/C0070/C0069/C0084/C0046 /C0080/C0111/C0119/C0101/C0114 /C0070/C0105/C0101/C0108/C0100 /C0069/C0102/C0102/C0101/C0099/C0116 /C0084/C0114/C0097/C0110/C0115/C0105/C0115/C0116/C0111/C0114 /C0068/C0051/C0080/C0065/C0075 /C0102/C0111/C0114 /C0083/C0117/C0114/C0102/C0097/C0099/C0101 /C0077/C0111/C0117/C0110/C0116 N–Channel Enhancement–Mode Silicon Gate The D3PAK package has the capability of housing the largest chip size of any standard, plastic, surface mount power semiconductor. This allows it to be used in applications that require surface mount components with higher power and lower RDS(on) capabilities. This high voltage MOSFE T uses an advanced termination schem e to provide enhanced voltage–blocking capability without degrading performance over time. In addition, this advanced TMOS E–FET is designed to withstand high energy in the avalanche and commuta- tion modes. The new energy efficient design also offers a drain–to– source diode with a fast recovery time. Designed for high voltage, high speed switching applications in surface mount PWM motor controls and both ac–dc and dc–dc power supplies. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.

  • Robust High Voltage Termination
  • Avalanche Energy Specified
  • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
  • Diode is Characterized for Use in Bridge Circuits
  • IDSS and VDS(on) Specified at Elevated Temperature
  • Short Heatsink Tab Manufactured – Not Sheared
  • Specifically Designed Leadframe for Maximum Power Dissipation
  • Available in 24 mm, 13–inch/500 Unit T ape & Reel, Add –RL Suffix to Part Number MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–to–Source Voltage VDSS 1000 Vdc Drain–to–Gate Voltage (RGS = 1.0 MΩ ) VDGR 1000 Vdc Gate–to–Source Voltage — Continuous Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGS VGSM ±20 ±40 Vdc Vpk Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) ID ID IDM 6.0 4.2 Adc Apk Total Power Dissipation Derate above 25°C Total Power Dissipation @ TC = 25°C (1) PD 178 1.43 2.0 Watts W/°C Watts Operating and Storage T emperature Range TJ, Tstg –55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 6.0 Apk, L = 27.77 mH, RG = 25 Ω ) EAS 720 mJ Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Thermal Resistance — Junction to Ambient (1) R θJC R θJA R θJA 0.70 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C (1)When surface mounted to an FR4 board using the minimum recommended pad size. Designer’s Data for “Worst Case” Conditions— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics— are given to facilitate “worst case” design. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company. Order this document by MTV6N100E/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA CASE 433–01, Style 2 D 3PAK Surface Mount /C0077/C0084/C0086/C0054/C0078/C0049/C0048/C0048/C0069 TMOS POWER FET

6.0 AMPERES

1000 VOLTS

R DS(on) = 1.5 OHM D S G  Motorola, Inc. 1996

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2 Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS 1000 1270 Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 1000 Vdc, VGS = 0 Vdc) (VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS 100 µAdc Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS , ID = 250 µAdc) Threshold T emperature Coefficient (Negative) VGS(th) 2.0 3.0 7.0 4.0 Vdc mV/°C Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 3.0 Adc) R DS(on) — 1.28 1.5 Ohm Drain–to–Source On–Voltage (VGS = 10 Vdc, ID = 6.0 Adc) (VGS = 10 Vdc, ID = 3.0 Adc, TJ = 125°C) VDS(on) 7.9 14.4 9.5 Vdc Forward Transconductance (VDS = 10 Vdc, ID = 3.0 Adc) gFS 4.0 7.2 — mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C iss — 3000 4210 pF Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C oss — 219 440 Transfer Capacitance f = 1.0 MHz) C rss — 43 90 SWITCHING CHARACTERISTICS (2) Turn–On Delay Time (VDD = 500 Vdc, ID = 6.0 Adc, VGS = 10 Vdc, R G = 9.1 Ω ) td(on) — 27 45 ns Rise Time (VDD = 500 Vdc, ID = 6.0 Adc, VGS = 10 Vdc, R G = 9.1 Ω ) tr — 29 65 Turn–Off Delay Time VGS = 10 Vdc, R G = 9.1 Ω ) td(off) — 93 170 Fall Time G = 9.1 Ω ) tf — 43 95 Gate Charge (See Figure 8) (VDS = 400 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) Q T — 66 100 nC (See Figure 8) (VDS = 400 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) Q 1 — 12.5 —(VDS = 400 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) Q 2 — 25.9 — Q 3 — 26 — SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C) VSD 0.81 0.64 1.0 Vdc Reverse Recovery Time (IS = 6.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) trr — 735 — ns (IS = 6.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) ta — 188 —(IS = 6.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) tb — 547 — Reverse Recovery Stored Charge Q RR — 4.7 — µC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD — 4.5 — nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS — 13 — nH (1) Pulse Test: Pulse Width ≤/n636861720000000000000000300 µs, Duty Cycle ≤ 2%. (2)Switching characteristics are independent of operating junction temperature.

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4 Motorola TMOS Power MOSFET Transistor Device Data

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Δt) are deter- mined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculat- ing rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resis- tive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP . Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG /(VGG – VGSP ) tf = Q2 x RG /VGSP where VGG = the gate drive voltage, which varies from zero to VGG R G = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG /(VGG – VGSP )] td(off) = RG Ciss In (VGG /VGSP ) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when cal- culating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). At high switching speeds, parasitic circuit elements com- plicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a func- tion of drain current, the mathematical solution is complex. The M OSFE T output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to mea- sure and, consequently, is not specified. The resistive switching time variation versus gate resis- tance (Figure9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely op- erated into an inductive load; however, snubbing reduces switching losses. Figure 7a. Capacitance Variation Figure 7b. High Voltage Capacitance Variation VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) 10 100 1000 10000 1000 100 C, CAPACITANCE (pF) C iss C oss C rss TJ = 25°CVGS = 0 V GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) 10 0 10 15 20 7000 5000 3000 1000 VGS VDS TJ = 25°CVDS = 0 V VGS = 0 V 6000 4000 2000 5 5 C iss C oss C iss C rss C rss

6 Motorola TMOS Power MOSFET Transistor Device Data

Figure 12. Maximum Rated Forward Biased Figure 13. Maximum Avalanche Energy versus Figure 14. Thermal Response Figure 15. Diode Reverse Recovery Waveform

device, PD is calculated as follows. R θJA versus drain pad area is shown in Figure 15. Figure 16. Thermal Resistance versus Drain Pad

1.75 Watts

3.0 Watts

5.0 Watts

8 Motorola TMOS Power MOSFET Transistor Device Data

tab area. The opening for the leads is still a 1:1 registration. of the pad to be covered with paste. Figure 17. Typical Stencil for DPAK and

  • Always preheat the device.
  • The delta temperature between the preheat and soldering should be 100°C or less.*
  • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.
  • The soldering temperature and time shall not exceed 260°C for more than 10 seconds.
  • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less.
  • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.
  • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

vary among soldering systems but it is a good starting point. efficiently, then distributes this energy to the components. up to 30 degrees cooler than the adjacent solder joints.

40 TO 80 SECONDS

Figure 18. Typical Solder Heating Profile

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10 Motorola TMOS Power MOSFET Transistor Device Data

CASE 433–01 ISSUE B DIM A MIN MAX MIN MAX MILLIMETERS 0.588 0.592 14.94 15.04 INCHES B 0.623 0.627 15.82 15.93 C 0.196 0.200 4.98 5.08 D 0.048 0.052 1.22 1.32 E 0.058 0.062 1.47 1.57 F 0.078 0.082 1.98 2.08 G 0.430 BSC 1.092 BSC H 0.105 0.110 2.67 2.79 J 0.018 0.022 0.46 0.56 K 0.150 0.160 3.81 4.06 L 0.058 0.062 1.47 1.57 N 0.353 0.357 8.97 9.07 P 0.078 0.082 1.98 2.08 Q 0.053 0.057 1.35 1.45 R 0.623 0.627 15.82 15.93 S 0.313 0.317 7.95 8.05 U 0.028 0.032 0.71 0.81 W 0.054 0.058 1.37 1.47 X 0.050 0.060 1.27 1.52 Y 0.104 0.108 2.64 2.74 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN W Y V P U F K N Q B S D G 1 3 A 2 PL 2 PL L M0.13 (0.005) T SEATING J H X E C PLANE–T– R How to reach us: USA / EUROPE : Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.; T atsumi–SPD–JLDC, T oshikatsu Otsuki, P .O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 T atsumi Koto–Ku, T okyo 135, Japan. 03–3521–8315 INTERNET : http://Design–NET .com 51 Ting Kok Road, T ai Po, N.T ., Hong Kong. 852–26629298 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MTV6N100E/D /C0042/C0077/C0084/C0086/C0054/C0078/C0049/C0048/C0048/C0069/C0047/C0068/C0042