MTP9N25E ONSEMI | Alldatasheet
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© Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 1
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Designer’s™ Data Sheet TMOS E−FET.™ Power Field Effect Transistor N−Channel Enhancement−Mode Silicon Gate This advanced TMOS E−FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain−to−source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
- Avalanche Energy Specified
- Source−to−Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
- Diode is Characterized for Use in Bridge Circuits
- IDSS and VDS(on) Specified at Elevated Temperature MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 250 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 250 Vdc Gate−to−Source Voltage — Continuous — Non −Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous — Continuous @ 100 °C — Single Pulse (t p ≤ 10 μs) ID ID IDM 9.0 5.7 Adc Apk Total Power Dissipation Derate above 25°C PD 80 0.64 Watts W/°C Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C Single Pulse Drain−to−Source Avalanche Energy — Starting T J = 25°C (VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 3.0 mH, RG = 25 Ω) EAS 122 mJ Thermal Resistance — Junction to Case — Junction to Ambient RθJC RθJA 1.56 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. Preferred devices are Motorola recommended choices for future use and best overall value. http://onsemi.com TMOS POWER FET
9.0 AMPERES, 250 VOLTS
RDS(on) = 0.45 /C0087 TO−220AB CASE 221A−06 Style 5 D S G
http://onsemi.com ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 μAdc) Temperature Coefficient (Positive) V(BR)DSS 250 328 Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 250 Vdc, VGS = 0 Vdc) (VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS 100 μAdc Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 μAdc) Threshold Temperature Coefficient (Negative) VGS(th) 2.0 3.0 7.0 4.0 Vdc mV/°C Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 4.5 Adc) RDS(on) — 0.37 0.45 Ohm Drain−to−Source On−Voltage (VGS = 10 Vdc, ID = 9.0 Adc) (VGS = 10 Vdc, ID = 4.5 Adc, TJ = 125°C) VDS(on) 3.5 5.4 4.7 Vdc Forward Transconductance (VDS = 15 Vdc, ID = 4.5 Adc) gFS 3.0 5.2 — mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss — 783 1100 pF Output Capacitance Coss — 144 200 Reverse Transfer Capacitance Crss — 32 65 SWITCHING CHARACTERISTICS (2) Turn−On Delay Time (VDD = 125 Vdc, ID = 9.0 Adc, VGS = 10 Vdc, RG = 9.1 Ω) td(on) — 10 20 ns Rise Time tr — 36 70 Turn−Off Delay Time td(off) — 27 55 Fall Time tf — 26 50 Gate Charge (See Figure 8) (VDS = 200 Vdc, ID = 9.0 Adc, VGS = 10 Vdc) QT — 26 40 nC Q1 — 4.8 — Q2 — 12.7 — Q3 — 9.2 — SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (1) (IS = 9.0 Adc, VGS = 0 Vdc) (IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125°C) VSD 0.9 0.81 1.5 Vdc Reverse Recovery Time (See Figure 14) (IS = 9.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/μs) trr — 191 — ns ta — 126 — tb — 65 — Reverse Recovery Stored Charge QRR — 1.387 — μC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD 3.5 4.5 nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS — 7.5 — nH (1) Pulse Test: Pulse Width ≤300 μs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature.
be charged by current from the generator. and Q2 and VGSP are read from the gate charge curve. the on−state when calculating td(off). is difficult to measure and, consequently, is not specified. which approximates an optimally snubbed inductive load. load; however, snubbing reduces switching losses. Figure 7. Capacitance Variation
http://onsemi.com PACKAGE DIMENSIONS CASE 221A−06 ISSUE Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88 F 0.142 0.147 3.61 3.73 G 0.095 0.105 2.42 2.66 H 0.110 0.155 2.80 3.93 J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27 L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33 Q 0.100 0.120 2.54 3.04 R 0.080 0.110 2.04 2.79 S 0.045 0.055 1.15 1.39 T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27 B Q H Z L V G N A K F 12 3 D SEATING PLANE−T− C ST U R J STYLE 5: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MTP9N25E/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.