MTP52N06VL ONSEMI | Alldatasheet

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Technical content

Features

  • Avalanche Energy Specified
  • IDSS and VDS(on) Specified at Elevated Temperature
  • This is a Pb−Free Device* MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 1.0 M/C0087) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−repetitive (tp ≤ 10 ms) VGS VGSM ± 15 ± 25 Vdc Vpk Drain Current − Continuous − Continuous @ 100°C − Single Pulse (tp ≤ 10 /C0109s) ID ID IDM 182 Adc Apk Total Power Dissipation Derate above 25°C PD 188 1.25 W W/°C Operating and Storage Temperature Range TJ, Tstg −55 to 175 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 52 Apk, L = 0.3 mH, RG = 25 /C0087) EAS 406 mJ Thermal Resistance − Junction−to−Case − Junction−to−Ambient R/C0113JC R/C0113JA 0.8 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

52 AMPERES, 60 VOLTS

RDS(on) = 25 m/C0087 Preferred devices are recommended choices for future use and best overall value. Device Package Shipping

ORDERING INFORMATION

N−Channel D S G http://onsemi.com MTP52N06VLG TO −220AB (Pb−Free)

50 Units/Rail

TO−220AB CASE 221A STYLE 5 MARKING DIAGRAM AND PIN ASSIGNMENT A = Location Code Y = Year WW = Work Week G = Pb −Free Package MT P52N06VLG AYWW Gate Source Drain Drain

http://onsemi.com ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Cpk ≥ 2.0) (Note 3) (VGS = 0 Vdc, ID = .25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS 100 /C0109Adc Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS − − 100 nAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (Cpk ≥ 2.0) (Note 3) (VDS = VGS, ID = 250 /C0109Adc) Threshold Temperature Coefficient (Negative) VGS(th) 1.0 1.5 4.5 2.0 Vdc mV/°C Static Drain−to−Source On−Resistance (Cpk ≥ 2.0) (Note 3) (VGS = 5 Vdc, ID = 26 Adc) RDS(on) − 0.022 0.025 /C0087 Drain−to−Source On−Voltage (VGS = 5 Vdc, ID = 52 Adc) (VGS = 5 Vdc, ID = 26 Adc, TJ = 150°C) VDS(on) 1.6 1.4 Vdc Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) gFS 17 30 − Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss − 1900 2660 pF Output Capacitance Coss − 550 770 Transfer Capacitance Crss − 170 340 SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time (VDD = 30 Vdc, ID = 52 Adc, VGS = 5 Vdc, RG = 9.1 /C0087) td(on) − 15 30 ns Rise Time tr − 500 1000 Turn−Off Delay Time td(off) − 100 200 Fall Time tf − 200 400 Gate Charge (See Figure 8) (VDS = 48 Vdc, ID = 52 Adc, VGS = 5 Vdc) QT − 62 90 nC Q1 − 4.0 − Q2 − 31 − Q3 − 16 − SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 52 Adc, VGS = 0 Vdc) (IS = 52 Adc, VGS = 0 Vdc, TJ = 150 °C) VSD 1.03 0.9 1.5 Vdc Reverse Recovery Time (IS = 52 Adc, VGS = 0 Vdc, dIS/dt = 100 A//C0109s) trr − 104 − ns ta − 63 − tb − 41 − Reverse Recovery Stored Charge QRR − 0.28 − /C0109C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD 3.5 4.5 nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS − 7.5 − nH 1. Pulse Test: Pulse Width ≤300 /C0109s, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Cpk = Max limit − Typ 3 x SIGMA

be charged by current from the generator. and Q2 and VGSP are read from the gate charge curve. on−state when calculating td(off). is difficult to measure and, consequently, is not specified. maintain a value of unity regardless of the switching speed. however, snubbing reduces switching losses. Figure 7. Capacitance Variation

5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage versus Current exceed (TJ(MAX) − TC)/(R/C0113JC). assumed to equal the values indicated.

http://onsemi.com PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. STYLE 5: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88 F 0.142 0.147 3.61 3.73 G 0.095 0.105 2.42 2.66 H 0.110 0.155 2.80 3.93 J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27 L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33 Q 0.100 0.120 2.54 3.04 R 0.080 0.110 2.04 2.79 S 0.020 0.055 0.508 1.39 T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27 B Q H Z L V G N A K F 12 3 D SEATING PLANE−T− C ST U R J ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MTP52N06VL/D E−FET is a trademark of Semiconductor Components Industries, LLC (SCILLC). LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative