MTP4N50E ONSEMI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
© Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 2
1 Publication Order Number:
Designer’s™ Data Sheet TMOS E−FET.™ High Energy Power FET N−Channel Enhancement−Mode Silicon Gate This advanced high voltage TMOS E−FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a drain −to−source diode with fast recovery time. Designed for high voltage, high speed switching applications such as power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients.
- Avalanche Energy Capability Specified at Elevated Temperature
- Low Stored Gate Charge for Efficient Switching
- Internal Source−to−Drain Diode Designed to Replace External Zener Transient Suppressor — Absorbs High Energy in the Avalanche Mode
- Source−to−Drain Diode Recovery Time Comparable to Discrete Fast Recovery Diode Designer’s Data for “Worst Case” Conditions— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. Preferred devices are Motorola recommended choices for future use and best overall value. http://onsemi.com TMOS POWER FET
4.0 AMPERES, 500 VOLTS
RDS(on) = 1.5 /C0087 TO−220AB CASE 221A−06 Style 5 D S G
http://onsemi.com MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−Source Voltage VDSS 500 Vdc Drain−Gate Voltage (RGS = 1.0 MΩ) VDGR 500 Vdc Gate−Source Voltage — Continuous Gate−Source Voltage — Non −repetitive VGS VGSM ±20 ±40 Vdc Vpk Drain Current — Continuous Drain Current — Pulsed ID IDM 4.0 Adc Total Power Dissipation @ TC = 25°C Derate above 25°C PD 75 0.6 Watts W/°C Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C UNCLAMPED DRAIN−TO−SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C) Single Pulse Drain−to−Source Avalanche Energy — T J = 25°C Single Pulse Drain−to−Source Avalanche Energy — T J = 100°C Repetitive Pulse Drain−to−Source Avalanche Energy WDSR (1) WDSR (2) 280 7.4 mJ THERMAL CHARACTERISTICS Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient ° RθJC RθJA 1.67 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C (1) VDD = 50 V, ID = 4.0 A (2) Pulse Width and frequency is limited by TJ(max) and thermal response
http://onsemi.com ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0, ID = 250 μAdc) V(BR)DSS 500 — — Vdc Zero Gate Voltage Drain Current (VDS = 500 V, VGS = 0) (VDS = 400 V, VGS = 0, TJ = 125°C) IDSS 0.25 1.0 mAdc Gate−Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF — — 100 nAdc Gate−Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR — — 100 nAdc ON CHARACTERISTICS* Gate Threshold Voltage (VDS = VGS, ID = 250 μAdc) (TJ = 125°C) VGS(th) 2.0 1.5 4.0 3.5 Vdc Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 2.0 A) RDS(on) — 1.3 1.5 Ohm Drain−Source On−Voltage (VGS = 10 Vdc) (ID = 4.0 Adc) (ID = 2.0 A, TJ = 100°C) VDS(on) 7.5 6.0 Vdc Forward Transconductance (VDS = 15 Vdc, ID = 2.0 A) gFS 1.5 — — mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Ciss — 775 — pF Output Capacitance Coss — 84 — Transfer Capacitance Crss — 19 — SWITCHING CHARACTERISTICS* Turn−On Delay Time (VDD = 250 V, ID ≈ 4.0 A, RG = 12 Ω, RL = 62 Ω, VGS(on) = 10 V) td(on) — 24 — ns Rise Time tr — 34 — Turn−Off Delay Time td(off) — 60 — Fall Time tf — 36 — Total Gate Charge (VDS = 400 V, ID = 4.0 A, VGS = 10 V) Qg — 27 32 nC Gate−Source Charge Qgs — 3.5 — Gate−Drain Charge Qgd — 14 — SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 4.0 A, di/dt = 100 A/μs) VSD — — 1.4 Vdc Forward Turn−On Time ton — ** — ns Reverse Recovery Time trr — — 760 INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) Ld 3.5 4.5 nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) Ls — 7.5 — * Indicates Pulse Test: Pulse Width = 300 μs Max, Duty Cycle ≤ 2.0%. ** Limited by circuit inductance. TYPICAL ELECTRICAL CHARACTERISTICS
Figure 10. Thermal Response
Figure 11. Capacitance Variation Figure 12. Gate Charge versus are common applications requiring CSOA data. primarily by device, package, and circuit impedances. from conduction to reverse blocking. CSOA stress is maximized as IS decays from IRM to zero. only a second order effect on CSOA. attained with dIs/dt of 400 A/μs. Figure 13. Commutating Safe Operating Area (CSOA) Figure 14. Commutating Safe Operating Area Figure 15. Commutating Waveforms
0.25 IRM
Figure 20. Gate Charge Test Circuit
10 V 100 k
http://onsemi.com PACKAGE DIMENSIONS CASE 221A−06 ISSUE Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. STYLE 5: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88 F 0.142 0.147 3.61 3.73 G 0.095 0.105 2.42 2.66 H 0.110 0.155 2.80 3.93 J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27 L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33 Q 0.100 0.120 2.54 3.04 R 0.080 0.110 2.04 2.79 S 0.045 0.055 1.15 1.39 T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27 B Q H Z L V G N A K F 12 3 D SEATING PLANE−T− C ST U R J ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MTP4N50E/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.