MTP2P50E_10 ONSEMI | Alldatasheet
Document overview
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- PDF pages: 7
Technical content
Features
- Robust High V oltage Termination
- Avalanche Energy Specified
- Source−to−Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
- Diode is Characterized for Use in Bridge Circuits
- IDSS and VDS(on) Specified at Elevated Temperature
- This is a Pb−Free Device* MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−Source Voltage VDSS 500 Vdc Drain−Gate Voltage (RGS = 1.0 M/C0087) VDGR 500 Vdc Gate−Source Voltage − Continuous − Non−Repetitive (tp ≤ 10 ms) VGS VGSM ±20 ±40 Vdc Vpk Drain Current − Continuous Drain Current − Continuous @ 100°C Drain Current − Single Pulse (tp ≤ 10 /C0109s) ID ID IDM 2.0 1.6 6.0 Adc Apk Total Power Dissipation Derate above 25°C PD 75 0.6 W W/°C Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 4.0 Apk, L = 10 mH, RG = 25 /C0087) EAS 80 mJ Thermal Resistance − Junction−to−Case − Junction−to−Ambient R/C0113JC R/C0113JA 1.67 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 sec TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. D S G
2 AMPERES, 500 VOLTS
RDS(on) = 6 /C0087 Device Package Shipping
ORDERING INFORMATION
P−Channel http://onsemi.com MTP2P50EG TO −220AB (Pb−Free)
50 Units/Rail
TO−220AB CASE 221A STYLE 5 MARKING DIAGRAM AND PIN ASSIGNMENT MTP2P50E = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb −Free Package MTP 2P50EG AYWW Gate Source Drain Drain
http://onsemi.com ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 /C0109Adc) Temperature Coefficient (Positive) V(BR)DSS 500 564 Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 500 Vdc, VGS = 0 Vdc) (VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS 100 /C0109Adc Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0) IGSS − − 100 nAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 250 /C0109Adc) Temperature Coefficient (Negative) VGS(th) 2.0 3.0 4.0 4.0 Vdc mV/°C Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 1.0 Adc) RDS(on) − 4.5 6.0 /C0087 Drain−Source On−Voltage (VGS = 10 Vdc) (ID = 2.0 Adc) (ID = 1.0 Adc, TJ = 125°C) VDS(on) 9.5 14.4 12.6 Vdc Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc) gFS 0.5 − − mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss − 845 1183 pF Output Capacitance Coss − 100 140 Reverse Transfer Capacitance Crss − 26 52 SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time (VDD = 250 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 9.1 /C0087) td(on) − 12 24 ns Rise Time tr − 14 28 Turn−Off Delay Time td(off) − 21 42 Fall Time tf − 19 38 Gate Charge (See Figure 8) (VDS = 400 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) QT − 19 27 nC Q1 − 3.7 − Q2 − 7.9 − Q3 − 9.9 − SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 1) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C) VSD 2.3 1.85 3.5 Vdc Reverse Recovery Time (See Figure 14) (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A//C0109s) trr − 223 − ns ta − 161 − tb − 62 − Reverse Recovery Stored Charge QRR − 1.92 − /C0109C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD 3.5 4.5 nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS − 7.5 − nH 1. Pulse Test: Pulse Width ≤ 300 /C0109s, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperature.
http://onsemi.com PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AF STYLE 5: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88 F 0.142 0.161 3.61 4.09 G 0.095 0.105 2.42 2.66 H 0.110 0.155 2.80 3.93 J 0.014 0.025 0.36 0.64 K 0.500 0.562 12.70 14.27 L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33 Q 0.100 0.120 2.54 3.04 R 0.080 0.110 2.04 2.79 S 0.045 0.055 1.15 1.39 T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27 B Q H Z L V G N A K F 12 3 D SEATING PLANE−T− C ST U R J ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MTP2P50E/D E−FET is a trademark of Semiconductor Components Industries, LLC (SCILLC). LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative