MTP2N40E MOTOROLA | Alldatasheet

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1Motorola TMOS Power MOSFET Transistor Device Data /C0068/C0101/C0115/C0105/C0103/C0110/C0101/C0114/C0039/C0115 /C0068/C0097/C0116/C0097 /C0083/C0104/C0101/C0101/C0116 /C0084/C0077/C0079/C0083 /C0069/C0045/C0070/C0069/C0084/C0046 /C0080/C0111/C0119/C0101/C0114 /C0070/C0105/C0101/C0108/C0100 /C0069/C0102/C0102/C0101/C0099/C0116 /C0084/C0114/C0097/C0110/C0115/C0105/C0115/C0116/C0111/C0114 N–Channel Enhancement–Mode Silicon Gate This high voltage M OSFE T uses an advanced termination scheme to provide enhanced voltage–blocking capability without degrading performance over time. In addition, this advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for high voltage, high speed switching applications in powe r supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.

  • Robust High Voltage Termination
  • Avalanche Energy Specified
  • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
  • Diode is Characterized for Use in Bridge Circuits
  • IDSS and VDS(on) Specified at Elevated Temperature MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–Source Voltage VDSS 400 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ ) VDGR 400 Vdc Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) ID ID IDM 2.0 1.5 6.0 Adc Apk Total Power Dissipation Derate above 25°C PD 40 0.32 Watts W/°C Operating and Storage T emperature Range TJ, Tstg –55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 Ω ) EAS 45 mJ Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient R θJC R θJA 3.13 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C Designer’s Data for “Worst Case” Conditions— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics— are given to facilitate “worst case” design. E–FET and Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. Order this document by MTP2N40E/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA /C0077/C0084/C0080/C0050/C0078/C0052/C0048/C0069 TMOS POWER FET

2.0 AMPERES

400 VOLTS

R DS(on) = 3.5 OHM Motorola Preferred Device D S G CASE 221A–06, Style 5 TO–220AB  Motorola, Inc. 1995

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2 Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS 400 451 Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 400 Vdc, VGS = 0 Vdc) (VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS 100 µAdc Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS — — 100 nAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS , ID = 250 µAdc) Temperature Coefficient (Negative) VGS(th) 2.0 3.2 7.0 4.0 Vdc mV/°C Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 1.0 Adc) R DS(on) — 3.1 3.5 Ohms Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 2.0 Adc) (ID = 1.0 Adc, TJ = 125°C) VDS(on) 7.3 8.4 7.4 Vdc Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc) gFS 0.5 1.0 — mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C iss — 229 320 pF Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C oss — 34 40 Reverse Transfer Capacitance f = 1.0 MHz) C rss — 7.3 10 SWITCHING CHARACTERISTICS (2) Turn–On Delay Time (VDD = 200 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, R G = 9.1 Ω ) td(on) — 8.0 16 ns Rise Time (VDD = 200 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, R G = 9.1 Ω ) tr — 8.4 14 Turn–Off Delay Time VGS = 10 Vdc, R G = 9.1 Ω ) td(off) — 12 26 Fall Time G = 9.1 Ω ) tf — 11 20 Gate Charge (VDS = 320 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) Q T — 8.6 12 nC (VDS = 320 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) Q 1 — 2.6 —(VDS = 320 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) Q 2 — 3.2 — Q 3 — 5.0 — SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C) VSD 0.88 0.76 1.2 Vdc Reverse Recovery Time (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) trr — 156 — ns (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) ta — 99 —(IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) tb — 57 — Reverse Recovery Stored Charge Q RR — 0.89 — µC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD 3.5 4.5 nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS — 7.5 — nH (1) Pulse Test: Pulse Width ≤/n636861720000000000000000300 µs, Duty Cycle ≤ 2%. (2)Switching characteristics are independent of operating junction temperature.

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4 Motorola TMOS Power MOSFET Transistor Device Data

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Δt) are deter- mined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculat- ing rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resis- tive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP . Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG /(VGG – VGSP ) tf = Q2 x RG /VGSP where VGG = the gate drive voltage, which varies from zero to VGG R G = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG /(VGG – VGSP )] td(off) = RG Ciss In (VGG /VGSP ) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when cal- culating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). At high switching speeds, parasitic circuit elements com- plicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a func- tion of drain current, the mathematical solution is complex. The M OSFE T output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to mea- sure and, consequently, is not specified. The resistive switching time variation versus gate resis- tance (Figure9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely op- erated into an inductive load; however, snubbing reduces switching losses. GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) VGS VDS VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) Figure 7a. Capacitance Variation Figure 7b. High Voltage Capacitance Variation TJ = 25°CVGS = 0 VVDS = 0 V C rss C iss C iss C rss C oss 500 400 300 200 100 –10 – 5 0 5 10 15 20 25 VGS = 0 V TJ = 25°C 1000 100 10 100 1000 C iss C oss C rss

6 Motorola TMOS Power MOSFET Transistor Device Data

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus Figure 13. Thermal Response Figure 14. Diode Reverse Recovery Waveform

/C0077/C0084/C0080/C0050/C0078/C0052/C0048/C0069 7Motorola TMOS Power MOSFET Transistor Device Data PACKAGE DIMENSIONS CASE 221A–06 (TO–220AB) ISSUE Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. STYLE 5: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88 F 0.142 0.147 3.61 3.73 G 0.095 0.105 2.42 2.66 H 0.110 0.155 2.80 3.93 J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27 L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33 Q 0.100 0.120 2.54 3.04 R 0.080 0.110 2.04 2.79 S 0.045 0.055 1.15 1.39 T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27 B Q H Z L V G N A K F 1 2 3 D SEATING PLANE–T– C ST U R J

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8 Motorola TMOS Power MOSFET Transistor Device Data

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