MTP12N10E MOTOROLA | Alldatasheet
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1Motorola TMOS Power MOSFET Transistor Device Data /C0068/C0101/C0115/C0105/C0103/C0110/C0101/C0114/C0039/C0115 /C0068/C0097/C0116/C0097 /C0083/C0104/C0101/C0101/C0116 /C0084/C0077/C0079/C0083 /C0069/C0045/C0070/C0069/C0084/C0046 /C0080/C0111/C0119/C0101/C0114 /C0070/C0105/C0101/C0108/C0100 /C0069/C0102/C0102/C0101/C0099/C0116 /C0084/C0114/C0097/C0110/C0115/C0105/C0115/C0116/C0111/C0114 N–Channel Enhancement–Mode Silicon Gate This advanced TMO S E –FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in powe r supplies, converters and PW M m otor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety m argin against unexpected voltage transients.
- Designed to Eliminate the Need for External Zener Transient Suppressor — Absorbs High Energy in the Avalanche Mode
- Commutating Safe Operating Area (CSOA) Specified for Use in Half and Full Bridge Circuits
- Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
- Diode is Characterized for Use in Bridge Circuits
- IDSS and VDS(on) Specified at Elevated Temperature MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–Source Voltage VDSS 100 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ ) VDGR 100 Vdc Gate–Source Voltage — Continuous Gate–Source Voltage — Single Pulse (tp ≤ 50 µs) VGS ± 20 ± 40 Vdc Drain Current — Continuous Drain Current — Single Pulse (tp ≤ 10 µs) ID IDM Adc Total Power Dissipation @ TC = 25°C Derate above 25°C PD 79 0.53 Watts W/°C Operating and Storage T emperature Range TJ, Tstg –55 to 175 °C UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ ≤ 175°C) Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 V, VGS = 10 V, L = 4.03 mH, RG = 25 Ω , Peak IL = 12 A) (See Figures 15, 16 and 17) EAS 290 mJ THERMAL CHARACTERISTICS Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient° R θJC R θJA 1.9 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C Designer’s Data for “Worst Case” Conditions— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics— are given to facilitate “worst case” design. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV 1 Order this document by MTP12N10E/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA /C0077/C0084/C0080/C0049/C0050/C0078/C0049/C0048/C0069 TMOS POWER FET
12 AMPERES
100 VOLTS
R DS(on) = 0.16 OHM Motorola Preferred Device D S G CASE 221A–06, Style 5 TO–220AB Motorola, Inc. 1996
/C0077/C0084/C0080/C0049/C0050/C0078/C0049/C0048/C0069
2 Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0, ID = 250 µAdc) Temperature Coefficient (positive) V(BR)DSS 100 110 Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 100 V, VGS = 0)° (VDS = 100 V, VGS = 0, TJ = 150°C) IDSS 100 µA Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF — — 100 nAdc Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR — — 100 nAdc ON CHARACTERISTICS* Gate Threshold Voltage (VDS = VGS , ID = 250 µAdc) Temperature Coefficient (negative)µ VGS(th) 2.0 3.0 6.0 4.0 Vdc mV/°C Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 6.0 Adc) R DS(on) — 0.125 0.16 Ohm Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 12 Adc)° (ID = 6.0 Adc, TJ = 150°C) VDS(on) 1.5 1.4 2.4 1.92 Vdc Forward Transconductance (VDS ≥ 15 V, ID = 6.0 A) gFS 4.0 5.0 — mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) See Figure 14 C iss — 600 — pF Reverse Transfer Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) See Figure 14 C rss — 70 — Output Capacitance See Figure 14 C oss — 230 — SWITCHING CHARACTERISTICS (TJ = 100°C) Turn–On Delay Time (VDD = 50 V, ID = 12 A, VGS = 10 V, RG = 12 Ω ) See Figure 7 td(on) — 10 — ns Rise Time (VDD = 50 V, ID = 12 A, VGS = 10 V, RG = 12 Ω ) See Figure 7 tr — 64 — Turn–Off Delay Time VGS = 10 V, RG = 12 Ω ) See Figure 7 td(off) — 21 — Fall Time tf — 30 — Gate Charge (VDS = 80 V, ID = 12 A, VGS = 10 Vdc) See Figures 5 and 6 Q T — 18 26 nC (VDS = 80 V, ID = 12 A, VGS = 10 Vdc) See Figures 5 and 6 Q 1 — 4.0 — VGS = 10 Vdc) See Figures 5 and 6 Q 2 — 10 — Q 3 — 8.0 — SOURCE–DRAIN DIODE CHARACTERISTICS* Forward On–Voltage (IS = 12 A, VGS = 0) (IS = 12 A, VGS = 0, TJ = 150°C) VSD — 1.0 2.5 Vdc(IS = 12 A, VGS = 0) Reverse Recovery Time (IS = 12 A, VGS = 0, dIS/dt = 100 A/µs, VR = 50 V) trr — 110 — ns INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die)″ (Measured from the drain lead 0.25″ from package to center of die) Ld 3.5 4.5 nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) Ls — 7.5 — * Pulse Test: Pulse Width ≤/n636861720000000000000000300 µs, Duty Cycle ≤ 2.0%.
Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance Variation Figure 5. Gate Charge Test Circuit
10 V 100 k
Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%. Figure 6. Gate–To–Source and
4 Motorola TMOS Power MOSFET Transistor Device Data
when it is forward biased, or when it is on, or being turned on. and Its Use” provides detailed instructions. Figure 7. Resistive Switching Time Figure 8. Maximum Rated Forward Biased Figure 9. Maximum Rated Switching Figure 10. Thermal Response
source current so dIs/dt is specified with a maximum value. stress is maximized as IS decays from IRM to zero. a second order effect on CSOA. Figure 11. Commutating Waveforms
0.25 IRM
Figure 12. Commutating Safe Operating Figure 13. Commutating Safe Operating Area associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
6 Motorola TMOS Power MOSFET Transistor Device Data
Figure 14. Capacitance Variation Figure 15. Maximum Avalanche Energy versus Figure 16. Unclamped Inductive Switching Figure 17. Unclamped Inductive Switching
- DIMENSIONING AND TOLERANCING PER ANSI
- CONTROLLING DIMENSION: INCH.
- DIMENSION Z DEFINES A ZONE WHERE ALL