MTP10N40E ONSEMI | Alldatasheet
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© Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 1
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Designer’s™ Data Sheet TMOS E−FET™ High Energy Power FET N−Channel Enhancement−Mode Silicon Gate This advanced high voltage TMOS E−FET is designed to withstand high energy in the avalanche mode and switch efficiently. This new high energy device also offers a drain −to−source diode with fast recovery time. Designed for high voltage, high speed switching applications such as power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients.
- Avalanche Energy Capability Specified at Elevated Temperature
- Low Stored Gate Charge for Efficient Switching
- Internal Source−to−Drain Diode Designed to Replace External Zener Transient Suppressor — Absorbs High Energy in the Avalanche Mode
- Source−to−Drain Diode Recovery Time Comparable to Discrete Fast Recovery Diode http://onsemi.com TMOS POWER FET
10 AMPERES, 400 VOLTS
RDS(on) = 0.55 /C0087 TO-220AB CASE 221A−06 Style 5 D S G
http://onsemi.com MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−Source Voltage VDSS 400 Vdc Drain−Gate Voltage (RGS = 1.0 MΩ) VDGR 400 Vdc Gate−Source Voltage — Continuous Gate−Source Voltage — Non −repetitive VGS VGSM ±20 ±40 Vdc Vpk Drain Current — Continuous Drain Current — Pulsed ID IDM Adc Total Power Dissipation Derate above 25°C PD 125 1.0 Watts W/°C Operating and Storage Temperature Range TJ, Tstg −65 to 150 °C UNCLAMPED DRAIN−TO−SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C) Single Pulse Drain−to−Source Avalanche Energy — T J = 25°C Single Pulse Drain−to−Source Avalanche Energy — T J = 100°C Repetitive Pulse Drain−to−Source Avalanche Energy WDSR(1) WDSR(2) 520 mJ THERMAL CHARACTERISTICS Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient ° RθJC RθJA 1.0 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds TL 275 °C (1) VDD = 50 V, ID = 10 A (2) Pulse Width and frequency is limited by TJ(max) and thermal response Designer’s Data for “Worst Case” Conditions— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
http://onsemi.com ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0, ID = 0.25 mA) V(BR)DSS 400 — — Vdc Zero Gate Voltage Drain Current (VDS = 400 V, VGS = 0) (VDS = 320 V, VGS = 0, TJ = 125°C) IDSS 0.25 1.0 mAdc Gate−Body Leakage Current — Forward (V GSF = 20 Vdc, VDS = 0) IGSSF — — 100 nAdc Gate−Body Leakage Current — Reverse (V GSR = 20 Vdc, VDS = 0) IGSSR — — 100 nAdc ON CHARACTERISTICS* Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) (TJ = 125°C) VGS(th) 2.0 1.5 4.0 3.5 Vdc Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 5.0 A) RDS(on) — 0.4 0.55 Ohms Drain−to−Source On−Voltage (VGS = 10 Vdc) (ID = 5.0 A) (ID = 2.5 A, TJ = 100°C) VDS(on) 6.0 4.75 Vdc Forward Transconductance (VDS = 15 Vdc, ID = 5.0 A) gFS 4.0 — — mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Ciss — 1570 — pF Output Capacitance Coss — 230 — Transfer Capacitance Crss — 55 — SWITCHING CHARACTERISTICS* Turn−On Delay Time (VDD = 200 V, ID ≈ 10 A, RL = 20 Ω, RG = 9.1 Ω, VGS(on) = 10 V) td(on) — 25 — ns Rise Time tr — 37 — Turn−Off Delay Time td(off) — 75 — Fall Time tf — 31 — Total Gate Charge (VDS = 320 V, ID = 10 A, VGS = 10 V) Qg — 46 63 nC Gate−Source Charge Qgs — 10 — Gate−Drain Charge Qgd — 23 — SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 10 A, di/dt = 100 A/μs) VSD — — 2.0 Vdc Forward Turn−On Time ton — ** — ns Reverse Recovery Time trr — 250 — INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) Ld 3.5 4.5 nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) Ls — 7.5 — nH * Pulse Test: Pulse Width = 300 μs, Duty Cycle ≤ 2.0%. ** Limited by circuit inductance. TYPICAL ELECTRICAL CHARACTERISTICS
Figure 12. Commutating Safe Operating Area (CSOA) Figure 13. Commutating Safe Operating Area Figure 14. Unclamped Inductive Switching Figure 15. Unclamped Inductive Switching Figure 10. Thermal Response CSOA stress is maximized as IS decays from IRM to zero. only a second order effect on CSOA. assumed to be practical minimums. Figure 11. Commutating Waveforms
0.25 IRM
Figure 16. Capacitance Variation Figure 17. Gate Charge versus Figure 18. Gate Charge Test Circuit