MTP10N10E ONSEMI | Alldatasheet

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© Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 2

1 Publication Order Number:

10 Amps, 100 Volts

N−Channel TO−220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers drain−to−source diodes with fast recovery times. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating area are critical, and offer additional safety margin against unexpected voltage transients.

  • Internal Source−to−Drain Diode Designed to Replace External Zener Transient Suppressor − Absorbs High Energy in the Avalanche Mode − Unclamped Inductive Switching (UIS) Energy Capability Specified at 100°C
  • Commutating Safe Operating Area (CSOA) Specified for Use in Half and Full Bridge Circuits
  • Source−to−Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
  • Diode is Characterized for Use in Bridge Circuits MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−Source Voltage VDSS 100 Vdc Drain−Gate Voltage (RGS = 1.0 MΩ) VDGR 100 Vdc Gate−Source Voltage VGS ±20 Vdc Drain Current − Continuous Drain Current − Pulsed ID IDM Adc Total Power Dissipation Derate above 25°C PD 75 0.6 Watts W/°C Operating and Storage Temperature Range TJ, Tstg −65 to 150 Thermal Resistance − Junction to Case − Junction to Ambient° RθJC RθJA 1.67 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds TL 275 °C

10 AMPERES

100 VOLTS

RDS(on) = 250 mΩ Device Package Shipping

ORDERING INFORMATION

MTP10N10E TO −220AB 50 Units/Rail TO−220AB CASE 221A STYLE 5 http://onsemi.com N−Channel D S G MARKING DIAGRAM & PIN ASSIGNMENT MTP10N10E = Device Code LL = Location Code Y = Year WW = Work Week MTP10N10E LLYWW Gate Source Drain Drain Preferred devices are recommended choices for future use and best overall value.

http://onsemi.com ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0, ID = 0.25 mA) V(BR)DSS 100 − Vdc Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0) (VDS = 0.8 Rated VDSS, VGS = 0, TJ = 125°C) IDSS μA Gate−Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF − 100 nAdc Gate−Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR − 100 nAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) TJ = 100°C VGS(th) 2.0 1.5 4.5 4.0 Vdc Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 5.0 Adc) RDS(on) − 0.25 Ohm Drain−Source On−Voltage (VGS = 10 V) (ID = 10 Adc)° (ID = 5.0 Adc, TJ = 100°C) VDS(on) 2.7 2.4 Vdc Forward Transconductance (VDS = 15 V, ID = 5.0 A) gFS 4.0 − mhos DRAIN−TO−SOURCE AVALANCHE CHARACTERISTICS Unclamped Drain−to−Source Avalanche Energy See Figures 14 and 15 (ID = 25 A, VDD = 25 V, TC = 25°C, Single Pulse, Non−repetitive) (ID = 10 A, VDD = 25 V, TC = 25°C, P.W. ≤ 200 μs, Duty Cycle ≤ 1%) (ID = 4.0 A, VDD = 25 V, TC = 100°C, P.W. ≤ 200 μs, Duty Cycle ≤ 1%) WDSR 100 mJ DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) See Figure 16 Ciss − 600 pF Output Capacitance Coss − 400 Reverse Transfer Capacitance Crss − 100 SWITCHING CHARACTERISTICS (Note 1) (TJ = 100°C) Turn−On Delay Time (VDD = 25 V, ID = 5.0 A, RG = 50 Ω) See Figure 9 td(on) − 50 ns Rise Time tr − 80 Turn−Off Delay Time td(off) − 100 Fall Time tf − 80 Total Gate Charge (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 V) See Figures 17 and 18 Qg 15 (Typ) 30 nC Gate−Source Charge Qgs 8.0 (Typ) − Gate−Drain Charge Qgd 7.0 (Typ) − SOURCE−DRAIN DIODE CHARACTERISTICS (Note 1) Forward On−Voltage (IS = Rated ID VGS = 0) VSD 1.4 (Typ) 1.7 Vdc Forward Turn−On Time ton Limited by stray inductance Reverse Recovery Time trr 70 (Typ) − ns INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die)″ (Measured from the drain lead 0.25″ from package to center of die) Ld 3.5 (Typ) 4.5 (Typ) nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) Ls 7.5 (Typ) − 1. Pulse Test: Pulse Width ≤300 μs, Duty Cycle ≤ 2.0%.

Figure 10. Thermal Response applications requiring CSOA data. s/dt is specified with a maximum value. conduction to reverse blocking. CSOA stress is maximized as IS decays from IRM to zero. only a second order effect on CSOA. V/ns was attained with dIs/dt of 400 A/μs. Figure 11. Commutating Waveforms

0.25 IRM

Figure 16. Capacitance Variation Figure 17. Gate Charge versus Figure 18. Gate Charge Test Circuit

10 V 100 k

http://onsemi.com PACKAGE DIMENSIONS TO−220 THREE−LEAD TO−220AB CASE 221A−09 ISSUE AA STYLE 5: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.570 0.620 14.48 15.75 B 0.380 0.405 9.66 10.28 C 0.160 0.190 4.07 4.82 D 0.025 0.035 0.64 0.88 F 0.142 0.147 3.61 3.73 G 0.095 0.105 2.42 2.66 H 0.110 0.155 2.80 3.93 J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27 L 0.045 0.060 1.15 1.52 N 0.190 0.210 4.83 5.33 Q 0.100 0.120 2.54 3.04 R 0.080 0.110 2.04 2.79 S 0.045 0.055 1.15 1.39 T 0.235 0.255 5.97 6.47 U 0.000 0.050 0.00 1.27 B Q H Z L V G N A K F 12 3 D SEATING PLANE−T− C ST U R J ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MTP10N10E/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative