MTM12N10 MOTOROLA | Alldatasheet
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MOTOROLA SC (XSTRS/R F) b&E D MM 6367254 0098578 72b MEMNOTL MOTOROLA @ SEMICONDUCTOR yy TECHNICAL DATA F 1, Designer’s Data Sheet *MTP12N10E H H “Motorola Preferred Device Power Field Effect Transistor N-Channel Enhancement-Mode Silicon Gate TMOS POWER FETs Th TMOS P% FETs designed f di Itag 12 AMPERES high speed power switching applications such as switching regu- ® Roston) = O18 lators, converters, solenoid and relay drivers. Tos: ® Silicon Gate for Fast Switching Speeds — Switching Times Specified at 100°C ® Designer's Data — Ipss, VDS(on); VGSith) and SOA Specified D at Elevated Temperature @ Rugged — SOA is Power Dissipation Limited @ Source-to-Drain Diode Characterized for Use With Inductive Loads G MAXIMUM RATINGS [ating TT Svembot [vate unit | Drain-Gate Voltage (Rgs = 1 MA) ‘ot Gate-Source Voltage ———at Continuous Ves +20 Vde Non-repetitive (tp < 50 ys} VGsm +40 Vpk peoge a | = MTM12N10 Pulsed CASE 1-07 Total Power Dissipation @ Tc = 25°C 75 Watts TO-204AA Derate above 25°C 06 wre THERMAL CHARACTERISTICS Thermal Resistance CW Junction to Case Rec 1.67 Junction to Ambient To204/ Raa [| 30 | To-220 y Maximum Lead Temperature for Soldering 70-220] T, | 260 | <c Wi, Purposes, 1/8” from case for 5 seconds TO-204 [30 Sts MTP12N10€ CASE 221-06 TO-220AB Preferred device is a Motorola recommended choice for future use and best overall value. Designer's Data for “Worst Case” Conditions — The Designer's Data Sheet permits the design of most circurts entirely from the information presented. ‘SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. aS MOTOROLA TMOS POWER MOSFET DATA 3-184
MTM12N10, MTP12N10E MOTOROLA SC (XSTRS/R F) BARE D MM 6367254 0098579 bbe MMOTL ELECTRICAL CHARACTERISTICS (Tc = 25°C unless otherwise noted) Lo ehaterste OT Symbot [min Mex [Unit] OFF CHARACTERISTICS Drain-Source Breakdown Voltage Vipr)DSs 400 = Vae (VGs = 0, !p = 0.25 mAb Zero Gate Voltage Drain Current Ade (Vps = Rated Vpss, Ves = 0) - 10 (pg = Rated Vpgs. Vag = 0, Ty = 125°C) = 100 Gate-Body Leakage Current, Forward (Vggr = 20 Vde, Vps = 0) icsse_ | — | 100 | nade | Gate-Body Leakage Current, Reverse (Vagr = 20 Vdc, Vps = 0) tgsse_ | — | 100 | nade | ON CHARACTERISTICS* Gate Threshold Voltage Vosith) 45 Vde (ps = Vos. Ip = 1 mA} 4 Ty = 100°C Static Drain-Source On-Resistance (Vgg = 10 Vde, Ip = 6 Adc) [ore [ohm | Drain-Source On-Voltage (Veg = 10 V) Vpsion) Vae (lp = 12 Adc) (lp = 6 Adc, Ty = 100°C) Forward Transconductance (Vpg - 15 V, Ip = 6A) [os | 3 | — | mos DYNAMIC CHARACTERISTICS ‘SWITCHING CHARACTERISTICS" (Ty = 100°C) Tarn On Dea Tne Pe ee Be Oe et [ = | 0 | Turn-Off Delay Time SoeFigures 9, 3and14 — |_taio) | | 200 | ee] ‘SOURCE DRAIN DIODE CHARACTERISTICS* Forward Turn-On Time | Ves = 0) [ton | __ Limited by stray inductance INTERNAL PACKAGE INDUCTANCE (TO-204) Internal Drain Inductance la 5 (Typ) nH (Measured from the contact screw on the header closer to the source pin and the center of the die) Internal Source Inductance us 125 (Typ) (Measured from the source pin, 0 25” from the package to the source bond pad) INTERNAL PACKAGE INDUCTANCE (TO-220) Internal Drain Inductance la nH {Measured from the contact screw on tab to center of die) 35 (Typ) (Measured from the drain lead 0.25” from package to center of die) 45 (Typ) | Internal Source Inductance ts 75 (Typ) (Measured from the source lead 0 25" from package to source bond pad. *Pulse Test Pulse Width < 300 ys, Duty Cycle = 2% MOTOROLA TMOS POWER MOSFET DATA 3-185
2 Ze bw = td XO
Figure 1. On-Region Characteristics Figure 2. Gate-Threshold Voltage Variation Figure 3. Transfer Characteristics Figure 4. Breakdown Voltage Variation
2 CTT Tt TTT tT itty | tt tT tt)
Figure 5. On-Resistance versus Drain Current Figure 6. On-Resistance Variation
Ser arrieeremercace Cd TLL.
2 ERR Op
2 SEH ke SSE Pty Py tT
Figure 7. Maximum Rated Forward Biased Figure 8. Maximum Rated Switching
1 TIME (ms)
Figure 10. Thermal Response
Figure 11. Capacitance Variation
4 Yeut OUTPUT, Vout / x
Figure 13. Switching Test Circuit Figure 14. Switching Waveforms