MTE50N45

MTE50N45 MOTOROLA | Alldatasheet

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MOTOROLA SC {XSTRS/R FT bY DE Bpe3e7esy 0068194 49 | T-39-15 ~ ____ MOTOROLA se] SEMICONDUCTOR ESzicc Sas eee TECHNICAL DATA . . , Designer’s Data Sheet MTES50N50 Power Field Effect Transistor MTEGON35 N-Channel Enhancement MTEGON4O Mode Silicon Gate TMOS These TMOS Power FETs are designed for high TMOS POWER FETs current, high speed power switching applications . 50 and 60 AMPERES such as switching regulators, converters, and motor DS(on) = 0.075 OHM controls. ™ ™ 350 and 400 VOLTS -, os n = 0.100 OHM © IDSs, VbS(on), SOA and VGsith) Specified at DS(on) Elevated Temperature 450 and 500 VOLTS @ Rugged — SOA is Power Dissipation Limited High di/dt Capability D © Silicon Gate for Fast Switching Speeds Multi-chip Construction << <S> @ Gates Internally Decoupled Ee. Sa 4 6 = CASE 346-01 s MO-040AA

7 MAXIMUM RATINGS 5

[sons [ son [ sone [ sono | i Drain-Gate Voltage VpGR Vde (Res = 1M) Ves Drain Current Continuous 60 Pulsed 300 Turn-Off Rate of Change See Note 4 and Figure 15 Aus in Considerations [Sate ar Pats ge Total Power Dissipation @ Tc = 25°C 500 Watts Derate above 25°C 4 wre. [Operating and Storage Tonpersefonge ——SSSS«d Tu Tog | esto Mounting Torque (To heatsink with 10-82 serewi( Dum | Cd Lead Torque (Lead to bus with 1/4-20 screw(2) cm | 2 —~«|_ in | [peruniewoit PW ora | THERMAL CHARACTERISTICS Maximum Lead Temp. for Soldering Purposes, TL 275 °c 1/8” from case for 5 seconds 2. The maximum penetration of the screw should be limited to 0.75". ‘TMOS and Designers are trademarks of Motorola Inc. _ ae oe @) MOTOROLA E3 MOTOROLA INC., 1985 Ds3678

MOTOROLA SC {XSTRS/R FF - bY DE Bese vesu 0068199 0 T-39-15 ELECTRICAL CHARACTERISTICS (Tc = 25°C unless otherwise noted) OFF CHARACTERISTICS . Drain-Source Breakdown Voltage V(BR)DSS Vac (V@s = 0, Ip = 5 mA) MTE6ON35 350 MTE6ON4O 400 MTESON45 450 MTESON50 500 Zero Gate Voltage Drain Current (Vps = 0.85 Rated Voss, Ves = 0) (Ty = 100°C) Gate-Body Leakage Current (Vgg = 20 Vdc, Vps = 0) ON CHARACTERISTICS* Gate Threshold Voltage Vesith) Vde (ip = 1 mA, Vpg = Vas) 2 (Ty = 100°C) 15 Static Drain-Source On-Resistance TDS(on) (gg = 10 Vdc, Ip = 30 Adc) MTEGON35/40 0.075 (Vgg = 10 Vdc, Ip = 25 Adc) MTESON45/60 0.100 Drain-Source On-Voltage (Vgg = 10 V) Vpston) Vde (Ip = 60 Ade) MTE6ON35/40 45 (ip = 30 Adc, Ty = 100°C) MTE6ON35/40 35 lip = 50 Ade) MTESON45/50 52 . lip = 25 Adc, Ty = 100°C) MTESON45/60 5 Forward Transconductance (ps = 18 V, Ip = 30 A) MTE6ON35/40 (pg = 15 V, Ip = 25 A) MTESONA5/50 « DYNAMIC CHARACTERISTICS o Input Capacitance [ Ciss | — | _ 12,000 pF aS SWITCHING CHARACTERISTICS* (Ty = 100°C) inductive Load, Clamped — MTE60N35 and MTEGON40 Turn-Off Delay Time (Velamp = 200 Vdc, Ip = 30 Adc, [ w | — | 130 | Current Fall Time Rgen = 50 0) See Figures 13 and 14 [ « [| — | 2 | Inductive Load, Clamped — MTESON45 and MTESON5O Turn-Off Delay Time (Welamp = 250 Vdc, Ip = 25, Adc, [ tw | -— | 4,300 Current Fall Time Rgen = 509) See Figures 13 and 14 [ wm | — | 2 | SOURCE-DRAIN DIODE CHARACTERISTICS* | Symbol | Typical | unit | ; | Forward Ture-On Time | £S."rigares ace. | ton | 0 | ns : Forward Turn-On Tima See Figures 16 and 16. 4 *Pulse Test: Pulse Width < 300 ys, Duty Cycle < 2%. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein: neither does it convey any license under its patent rights nor the rights of others. Motorola and@) are registered trademarks of Motorola, Inc. Motorola, Inc 1s an Equal Employment Opportunity/ Affirmative Action Employer. MOTOROLA MTESON45 @ MTESONSO © MTE60N35 @ MTE60N40

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Figure 1. MTESON45/50 Figure 2. MTEG0N35/40 Figure 3. MTESON45/50 Figure 4. MTE60N35/40

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Figure 5. MTESON45/50 Figure 6. MTE60N35/40

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Figure 7. Gate-Threshold Voltage

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Figure 9. MTES0N45/50 Figure 10. MTE60N35/40

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Figure 11. MTE6035/40 AND MTESON45/50

MOTOROLA SC IXSTRS7R FF bu DE | bab?254 OUbscus 4 | CONSIDERATION IN DESIGNING WITH POWER MOSFETS Depending on the frequency of operation, certain recovery time tfr, overshoot voltage VeM(DYN) precautions must be taken to insure optimum reliability. and reverse recovery time tr; should be low to When switching near the device maximum frequency, the minimize the switching stress on the transistor. high current and very fast switching capability of this Note 4 Even with good RF layout and ideal clamping device necessitates the use of the following protective below the maximum VBR)pss of the device, i significant potentials may be generated across Note 1 As in any wideband circuit, good RF layout the package drain and source parasitic techniques must be maintained, i.e., short lead inductances during rapid turn off of a large lengths. adequate ground planes and meanitude of current. ese induced voltages lecoupled power supplies. which are internal to the package add to the Note 2 All overvoltage protection circuitry — free clamp voltage. Therefore, to protect the chips wheeling diodes, zeners, MOVs, snubber from excessive voltage, the dip/dt must be tho drativsource ot eenacen the tate wcen across the torminals ef the devien, The 4 the drain- between the drain and a g 00d, low inductance ac ground. MAXIMUM ALLOWABLE dip/dt must be : oe a ” . . limited in accordance to the peak Vps Note 3 Since most “real world” loads are inductive, appearing at the device terminals as shown in the fot turn-off peak flyback voltage (e= Figure 15 L di/dt) must not exceed the Vgr(pss) rating, * an instantaneous voltage limit. The protective circuitry, including parasitics, must have For applications requiring slower switching speeds, response times commensurate with the Power increasing the gate drive impedance will increase the MOSFET switching speed, e.g., rectifiers must switching times. This can be accomplished by adding a have very short recovery times. The forward resistor in series with the gate. : os aK [IV NNNLILLLE 7 PNSNSEEEEE @q 3x : FT ORO hee 5 on ttt NNN Net wreonaa |__| ge EEE INIA gebatenes Z wtb tT 1 AMRKAL YT sf ttt. NAAN ge LL TTT AARAKAK Lt] { | | INNNN 0 100 20 300 400 500 Vos. PEAK DRAIN SOURCE VOLTAGE (VOLTS) i Figure 15. Maximum Allowable dip/dt versus | Drain Source Voltage q Foe ee FATE Tn ge re en Ee MOTOROLA MTESON45 @ MTESONS50 ¢ MTEGON35 ¢ MTEGON4O