MTD9N10E ONSEMI | Alldatasheet

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 Semiconductor Components Industries, LLC, 2001 February, 2001 – Rev. 4

1 Publication Order Number:

9 Amps, 100 Volts

N–Channel DPAK This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.

  • Avalanche Energy Specified
  • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
  • Diode is Characterized for Use in Bridge Circuits
  • IDSS and VDS(on) Specified at Elevated Temperature
  • Replaces MTD6N10 MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–Source Voltage VDSS 100 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ ) VDGR 100 Vdc Gate–Source Voltage – Continuous – Non–Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 30 Vdc Vpk Drain Current – Continuous Drain Current – Continuous @ 100°C Drain Current – Single Pulse (tp ≤ 10 µs) ID ID IDM 9.0 5.0 Adc Apk Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size PD 40 0.32 1.75 Watts W/°C Watts Operating and Storage Temperature Range TJ, Tstg –55 to 150 Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 9.0 Apk, L = 1.0 mH, RG = 25 Ω ) EAS 40 mJ Thermal Resistance – Junction to Case – Junction to Ambient – Junction to Ambient, when mounted to minimum recommended pad size R θJC R θJA R θJA 3.13 100 71.4 °C/W Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C PIN ASSIGNMENT Gate Source Drain Drain

9 AMPERES

100 VOLTS

R DS(on) = 250 mΩ Device Package Shipping

ORDERING INFORMATION

MTD9N10E DPAK 75 Units/Rail CASE 369A DPAK STYLE 2 http://onsemi.com N–Channel D S G MTD9N10E1 DPAK 75 Units/Rail Preferred devices are recommended choices for future use and best overall value. MARKING DIAGRAM Y = Year WW = Work Week T9 = MOSFET YWW N10E MTD9N10ET4 DPAK 2500 Tape & Reel 1 2

http://onsemi.com ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS 100 103 Vdc mV/°C Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS 100 µAdc Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS – – 100 nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS , ID = 250 µAdc) Temperature Coefficient (Negative) VGS(th) 2.0 6.0 4.0 Vdc mV/°C Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 4.5 Adc) R DS(on) – 0.17 0.25 Ohm Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 9.0 Adc) (ID = 4.5 Adc, TJ = 125°C) VDS(on) 2.43 2.40 Vdc Forward Transconductance (VDS = 8.0 Vdc, ID = 4.5 Adc) gFS 4.0 – – mhos DYNAMIC CHARACTERISTICS Input Capacitance (V 25 Vd V 0 Vd C iss – 610 1200 pF Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f= 1.0 MHz) C oss – 176 400 Reverse Transfer Capacitance f = 1.0 MHz) C rss – 14 30 SWITCHING CHARACTERISTICS (Note 2.) Turn–On Delay Time td(on) – 8.8 20 ns Rise Time (VDD = 50 Vdc, ID = 9.0 Adc, VGS 10 Vdc tr – 28 60 Turn–Off Delay Time VGS = 10 Vdc, R G = 9.1 Ω ) td(off) – 16 30 Fall Time R G = 9.1 Ω ) tf – 4.8 10 Gate Charge (S Fi 8) Q T – 14 21 nCg (See Figure 8) (VDS = 80 Vdc, ID = 9.0 Adc, Q 1 – 5.2 –(VDS = 80 Vdc, ID = 9.0 Adc, VGS = 10 Vdc) Q 2 – 3.2 – Q 3 – 6.6 – SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (Note 1.) (IS = 9.0 Adc, VGS = 0 Vdc) (IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125°C) VSD 0.98 0.9 1.8 Vdc Reverse Recovery Time (S Fi 14) trr – 91 – nsy (See Figure 14) (IS =90A d c VGS = 0 Vdc ta – 71 – (IS = 9.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) tb – 20 – Reverse Recovery Stored Charge dIS/dt = 100 A/µs) Q RR – 0.4 – µC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD – 4.5 – nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS – 7.5 – nH 1. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperature.

be charged by current from the generator. and Q2 and VGSP are read from the gate charge curve. on–state when calculating td(off). is difficult to measure and, consequently, is not specified. maintain a value of unity regardless of the switching speed. however, snubbing reduces switching losses. Figure 7. Capacitance Variation

subjected to a solder reflow process. DPAK device, PD is calculated as follows. Figure 15. Thermal Resistance versus Drain Pad

3.0 Watts

5.0 Watts

1.75 Watts

circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. Figure 16. Typical Stencil for DPAK and

  • Always preheat the device.
  • The delta temperature between the preheat and soldering should be 100°C or less.*
  • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.
  • The soldering temperature and time shall not exceed 260°C for more than 10 seconds.
  • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less.
  • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.
  • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

being used. This profile shows temperature versus time. degrees cooler than the adjacent solder joints.

40 TO 80 SECONDS

Figure 17. Typical Solder Heating Profile

http://onsemi.com PACKAGE DIMENSIONS STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN D A K B RV S F L G 2 PL M0.13 (0.005) T E C U J H –T– SEATING PLANE Z DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.235 0.250 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.033 0.040 0.84 1.01 F 0.037 0.047 0.94 1.19 G 0.180 BSC 4.58 BSC H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.102 0.114 2.60 2.89 L 0.090 BSC 2.29 BSC R 0.175 0.215 4.45 5.46 S 0.020 0.050 0.51 1.27 V 0.030 0.050 0.77 1.27 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 12 3 DPAK CASE 369A–13 ISSUE AA

http://onsemi.com Notes

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