MTC50150 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
1 GENERAL FEATURES
1.1 WAN modem feature set
1.2 WAN connectivity
1.3 Session Control
1.4 ATM features
1.5 LAN feature set
■ Support up to 128 MAC stations.
1.6 Configuration and Provisioning
■ Firmware update: remote upload via network.
1.7 Customization
software in object or source format.
2 APPLICATION
Figure 1. Package Table 1. Order Codes
Figure 2. Block diagram
3 DESCRIPTION
plans are available as well as a user friendly development environment.
4 HARDWARE DESCRIPTION
5 HARDWARE FEATURES
– ARM946ES RISC processor dedicated to network processing, API and DSL modem control – Hardware ATM processor: SAR function with AAL5 processing – Hardware packet processor: Ethernet MAC, learning and filter bridge – One 10/100 Base-T Ethernet MACs with MII interface for external PHY or multi-port switch – One 8 or 16-bit wide Flash port, ISA compatible for up to 16Mbyte addressable memory – One 32-bit wide SDRAM interface with 32Mbyte addressable memory – Interface to MTC20174 DynaMiTe™ ADSL analog front end (AFE) chip – Multi-channel DMA engine integrated with peripherals – Low power: 1.8V +/-10% core voltage, 3.3V +/- 10% I/O voltage – 128 instructions (32 bits) of boot ROM – GPIO with support LED – Cc-based Multi ICE/compiler support with assembler and debugger – Software chip and system simulators for software development and debug – JTAG board-level test interface – 140MHz system clock (processor cycle clock) – Sleep mode with wake on LAN wake on WAN feature – Programmable system frequency clock: 140, 105, 70, 35 and 129MHz (fall back mode).
6 SOFTWARE ARCHITECTURE
The software is organized in 5 clusters: – User interface API – System services – Network services – TCP/IP socket – ATM encapsulation A description of the cluster contents is given in the software features section.
Figure 3. Embedded software block diagram
7 SOFTWARE FEATURES
7.1 User Interface API
7.2 System Services
MIB2: RFC 1213: Management Information Bases (MIB2) is implemented in the device. through specific APIs. Alternate RTOS are planned. Startup initialization: Optional software images can be selected at startup of the device. architecture. The BSP provides a unique hardware abstraction layer model valid for the entire product line. This approach allows reuse of the custom solfware through the entire MTC-50xxx product line(*).
7.3 Network Services
7.3.1 ILMI
Embedded software provides an ILMI 4.0 implementation which handles address registration (switch to end device) and notification (end device to switch) as well as auto-configuration. ILMI uses SNMP over AAL-5 for transport.
7.3.2 UNI Signaling
Stackware includes support for standard ATM UNI signaling standards, including UNI 3.1.
7.3.3 RIP1/RIP2 IP Router
IP router software provides implementations of RIP1 and RIP2. The IP router is an IPv4 router. Support for new station discovery is provided.
7.4 TCP/IP Socket
7.4.1 TCP
Transport Control Protocol (TCP) is accessed using a standard socket interface to allow easy integration of existing Layer 3 and higher software into the basic protocol stack. 7.4.2 IP Internal protocol: IP and IP routing are both part of the network layer (layer 3). IP is actually responsible for delivering packets for which the router defines the direction.
7.4.3 DHCP RFC 2131, 2132
Dynamic Host Control Protocol (DHCP) provides both client & server functions. The client is typically used to obtain an IP address from an ISP. The DHCP server is used to assign local IP client devices with des- ignated IP addresses. The server lends addresses for a limited time. NAT registers local terminal IP ad- dresses and maintains a translation table to allow sending and receiving data on the public network by sharing only the residential gateway assigned public IP address.
7.4.4 NAT: RFC1631, 2663
The Network Address Translator (NAT) implements Network and Port Address Translation (NAT/PAT). NAT allows a single public IP address on the WAN side to be shared among many devices on the LAN side. Combined with a DHCP server local devices are assigned a private address, hidden to the public internet and changed frequently. The combination of DHCP and NAT provides a powerful isolation barrier to external assault. NAT PAT features a number of AGL.
7.5 ATM Encapsulation and spanning-tree
RFC 1483/2684 provides a simple robust method of connecting end stations over an ATM network. User data in the form of Ethernet packets are encapsulated into AAL-5 PDUs for transport over ATM. RFC 1483/2684 provides no AAA function (authentication, authorization & accounting). 7.5.1 Spanning-tree bridge (802.1d) Bridge module provides a transparent bridge between two physically disjoint networks with spanning-tree option. The spanning-tree algorithm handles redundancy and also increases robustness. It provides high performance as well as flexibility to group interfaces for example to bridge the WAN only to LAN interfaces but not to other WAN interfaces. The ATM driver passes data between application software tasks on the processor and a physical AAL5 hardware block.
7.6 Session Control
7.6.1 PPPoA (RFC 2364)
PPP over ATM provides on the CPE side a termination agent for the transportation for IP packets over an ATM segment. A PPP session is established between the CPE and the central office (DSLAM). PPP pro- vides AAA function (authentication, authorization and accounting). The PPP packets encapsulated ac- cording to RFC 2364 for transmission over an ATM segment. On the CPE side, the IP data can be delivered to the end user over such technologies as Ethernet.
7.6.2 PPPoE (RFC 2516)
The PPP over Ethernet encapsulation is used to transport Ethernet PPP traffic. The traffic is then trans- ported over the ATM link by encapsulating traffic using RFC1483/2683. There may be multiple PPP ses- sions, each terminated in the IAD client device. PPPoE relay agent works as a enhanced layer 2 bridge. It determines that which locally originated PPPoE traffic belongs. The relay agent forwards that traffic, without any unnecessary processing, only to the correct destination. Similarly, received data is immedi- ately relayed only to the appropriate LAN client.
8 DEVELOPMENT ENVIRONMENT
The MTC50150 presents a comprehensive set of software features. To allow manufacturers to further cus- tomize the system, a set of API functions are made available. This use of the API functions requires the acquisition of a development environment. The development environment is based on the following ele- ments: ■ -ARM Developer Suite (ADS) v1.1 ■ -ATI Development license ■ -ATI EDE (Embedded Development Environment) ■ -MS Developer Studio (VC++) v6.0 or higher Along with the development environment a number of tools are provided to allow the diagnostic and the downloading operation of the executable on the nonvolatile memory of the MTC50150.
9 NOMINAL CHARACTERISTICS
The MTC50150 processor is available in a 208-pin PBGA (plastic ball grid array) package. All I/Os are pins have internal pull-ups and pull-downs. Supply – Typical power supply voltage 1.8V – Typical pad power supply voltage 3.3V Threshold – Input low voltage -0.5V -1.0V – Input high voltage 2.3V- 5.5V Consumption – Core consumption: 1000mW, reduced power mode avail- able. Environment – Ambient temperature: 0C - 70C (32F - 158F) – Industrial grade: -40C - 85C. (-49F - 185F) Package – 208-pin plastic BGA package Technology – CMOS 0.18 micron
10 APPLICATION EXAMPLE
a 10/100bT Ethernet port. It utilizes a set of two ASSP available from ST. to the MTC50150 to store and execute additional (custom) application. Figure 4. Application block diagram
11 MTC50150 PIN LIST
11.1 PIN DESCRIPTION
The pin list comprises of all functional and power supply pins. A TBGA-208 package (TB208A) is used. FS = Full Scan, NA = not available as pin). Table 2. MTC50150 Pin list
Table 2. MTC50150 Pin list (continued)
Table 3. Summary of MTC50150 Pin list
Figure 5. PBGA208 (17x17x1.97mm) Mechanical Data & Package Dimensions
Table 4. Revision History September 2004 1 First Issue in EDOCS dms.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America MTC50150