MTC16

74AC138_03 FAIRCHILD | Alldatasheet

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I ICC reduced by 50% I Demultiplexing capability I Multiple input enable for easy expansion I Active LOW mutually exclusive outputs I Outputs source/sink 24 mA I ACT138 has TTL-compatible inputs Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Logic Symbols IEEE/IEC FACT  is a trademark of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74AC138SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC138PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT138SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT138PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pin Names Description A0–A2 Address Inputs E1–E2 Enable Inputs E3 Enable Input O 0–O 7 Outputs

operations and should not be used to estimate propagation delays. FIGURE 1. Expansion to 1-of-32 Decoding

3 www.fairchildsemi.com 74AC138  74ACT138 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC . Supply Voltage (VCC ) −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) −0.5V to VCC + 0.5V DC Output Diode Current (IOK ) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO ) −0.5V to VCC + 0.5V DC Output Source or Sink Current (IO ) ±50 mA DC V CC or Ground Current per Output Pin (ICC or IGND ) ±50 mA Storage Temperature (TSTG ) −65°C to +150°C Junction Temperature (TJ) PDIP 140 °C Supply Voltage (VCC ) AC 2.0V to 6.0V ACT 4.5V to 5.5V Input Voltage (V I)0 V t o V CC Output Voltage (VO )0 V t o V CC Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) AC Devices V IN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ACT Devices V IN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits 5.5 2.75 3.85 3.85 5.5 2.75 1.65 1.65 VOH Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I OUT = −50 µA 5.5 5.49 5.4 5.4 VIN = VIL or VIH 3.0 2.56 2.46 I OH = −12 mA 4.5 3.86 3.76 V I OH = −24 mA 5.5 4.86 4.76 I OH = −24 mA (Note 2) VOL Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I OUT = 50 µA 5.5 0.001 0.1 0.1 VIN = VIL or VIH 3.0 0.36 0.44 I OL = 12 mA 4.5 0.36 0.44 V I OL = 24 mA 0 5.5 0.36 0.44 I OL = 24 mA (Note 2) IIN Maximum Input 5.5 ±0.1 ±1.0 µAV I = VCC , GND (Note 4) Leakage Current IOLD Minimum Dynamic 5.5 75 mA V OLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA V OHD = 3.85V Min ICC (Note 4) Maximum Quiescent Supply Current 5.5 4.0 40.0 µAV IN = VCC or GND

www.fairchildsemi.com 4 74AC138  74ACT138 Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 V VOUT = 0.1V VIL Maximum LOW Level 4.5 1.5 0.8 0.8 V VOUT = 0.1V VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI OUT = −50 µA Output Voltage 5.5 5.49 5.4 5.4 VIN = VIL or VIH 4.5 3.86 3.76 V I OH = −24 mA 5.5 4.86 4.76 I OH = −24 mA (Note 5) VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI OUT = 50 µA Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH 4.5 0.36 0.44 V I OL 24 mA 5.5 0.36 0.44 I OL .= 24 mA (Note 5) IIN Maximum Input 5.5 ±0.1 ±1.0 µAV I = VCC , GND Leakage Current ICCT Maximum 5.5 0.6 1.5 mA V I = VCC − 2.1V ICC /Input IOLD Minimum Dynamic 5.5 75 mA V OLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA V OHD = 3.85V Min ICC Maximum Quiescent 5.5 4.0 40.0 µAV IN = VCC or GND Supply Current VCC TA = +25°CT A = −40°C to +85°C Symbol Parameter (V) C L = 50 pF C L = 50 pF Units (Note 7) Min Typ Max Min Max ns ns ns ns ns ns

5 www.fairchildsemi.com 74AC138  74ACT138 Note 8: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance VCC TA = +25°CT A = −40°C to +85°C Symbol Parameter (V) C L = 50 pF C L = 50 pF Units (Note 8) Min Typ Max Min Max tPLH Propagation Delay An to On tPHL Propagation Delay 5.0 1.5 6.5 10.5 1.5 11.5 ns An to On tPLH Propagation Delay E1 or E2 to On tPHL Propagation Delay E1 or E2 to On tPLH Propagation Delay E3 to On tPHL Propagation Delay E3 to On Symbol Parameter Typ Units Conditions C IN Input Capacitance 4.5 pF V CC = OPEN C PD Power Dissipation Capacitance 60.0 pF V CC = 5.0V

www.fairchildsemi.com 6 74AC138  74ACT138 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A

7 www.fairchildsemi.com 74AC138  74ACT138 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

www.fairchildsemi.com 8 74AC138  74ACT138 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

9 www.fairchildsemi.com 74AC138  74ACT138 1-of-8 Decoder/Demultiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com