MTC16

74LVX174 FAIRCHILD | Alldatasheet

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I Input voltage level translation from 5V to 3V I Ideal for low power/low noise 3.3V applications I Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Pin Descriptions Order Number Package Number Package Description 74LVX174M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description D 0–D 5 Data Inputs CP Clock Pulse Input MR Master Reset Input Q 0–Q 5 Outputs

www.fairchildsemi.com 2 74LVX174 Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial /c17 = LOW-to-HIGH Transition Logic Diagram Operating Mode Inputs Outputs MR CP D n Q n Reset (Clear) L X X L Load ‘1’ H /c17 HH Load ‘0’ H /c17 LL

3 www.fairchildsemi.com 74LVX174 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float. Noise Characteristics (Note 3) Note 3: (Input tr = tf = 3 ns) Supply Voltage (VCC ) −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA DC Input Voltage (VI) −0.5V to 7V DC Output Diode Current (IOK ) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO ) −0.5V to VCC + 0.5V DC Output Source or Sink Current (IO ) ±25 mA DC V CC or Ground Current (ICC or IGND ) ±50 mA Storage Temperature (TSTG ) −65°C to +150°C Power Dissipation (PD ) 180 mW Supply Voltage (VCC ) 2.0V to 3.6V Input Voltage (VI) 0V to 5.5V Output Voltage (VO )0 V t o V CC Operating Temperature (TA) −40°C to +85°C Input Rise and Fall Time (∆t/∆V) 0 ns/V to 100 ns/V Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units Conditions Min Typ Max Min Max VIH HIGH Level 2.0 1.5 1.5 Input Voltage 3.0 2.0 2.0 V 3.6 2.4 2.4 VIL LOW Level 2.0 0.5 0.5 Input Voltage 3.0 0.8 0.8 V 3.6 0.8 0.8 VOH HIGH Level 2.0 1.9 2.0 1.9 V IN = VIL or VIH IOH = −50 µA Output Voltage 3.0 2.9 3.0 2.9 V I OH = −50 µA 3.0 2.58 2.48 I OH = −4 mA VOL LOW Level 2.0 0.0 0.1 0.1 V IN = VIL or VIH IOL = 50 µA Output Voltage 3.0 0.0 0.1 0.1 V I OL = 50 µA 3.0 0.36 0.44 I OL = 4 mA IIN Input Leakage Current 3.6 ±0.1 ±1.0 µAV IN = 5.5V or GND ICC Quiescent Supply Current 3.6 4.0 40.0 µAV IN = VCC or GND Symbol Parameter VCC TA = 25°C Units C L (pF) (V) Typ Limit VOLP Quiet Output Maximum Dynamic VOL 3.3 0.3 0.5 V 50 VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.3 −0.5 V 50 VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50 VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50

www.fairchildsemi.com 4 74LVX174 Note 4: Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn |, tOSHL = |tPHLm − tPHLn | Capacitance Note 5: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Symbol Parameter VCC TA = +25°CT A = −40°C to +85°C Units C L (pF) (V) Min Typ Max Min Max ns tPHL Delay Time 10.1 18.0 1.0 21.0 50 CP to Q 8.4 12.8 1.0 14.5 50 ns MR to Qn 10.4 18.5 1.0 22.0 50 8.7 13.2 1.0 15.0 50 tS Setup Time 2.7 7.5 8.5 ns D n to CP 3.3 ± 0.3 5.0 6.0 tH Hold Time 2.7 0 0 D n to CP 3.3 ± 0.3 0 0 tREC Removal Time 2.7 4.5 4.5 ns MR to CP 3.3 ± 0.3 3.0 3.0 tW Clock Pulse 2.7 6.5 7.5 Width 3.3 ± 0.3 5.0 5.0 tW MR Pulse 2.7 6.5 7.5 ns Width 3.3 ± 0.3 5.0 5.0 fMAX Maximum Clock 2.7 65 130 55 MHz Frequency 45 60 40 50 3.3 ± 0.3 115 180 95 15 65 95 55 50 tOSLH Output to Output 2.7 1.5 1.5 ns tOSHL Skew (Note 4) 3.3 1.5 1.5 Symbol Parameter TA = +25°CT A = −40°C to +85°C Units Min Typ Max Min Max C IN Input Capacitance 4 10 10 pF C PD Power Dissipation Capacitance (Note 5) 29 pF

5 www.fairchildsemi.com 74LVX174 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A

www.fairchildsemi.com 6 74LVX174 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

7 www.fairchildsemi.com 74LVX174 Low Voltage Hex D-Type Flip-Flop with Master Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com