MT9V126IA3XTC-DR1

MT9V126 ONSEMI | Alldatasheet

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Features

MT9V126_DS Rev. J Pub. 5/15 EN 1 ©Semiconductor Components Industries, LLC 2015, 1/4-Inch Color CMOS NTSC/PAL Digital Image SOC with Distortion Correction and Overlay Processor MT9V126 Datasheet, Rev. J For the latest datasheet, please visit www.onsemi.com

• Low-power CMOS image sensor with integrated image flow processor (IFP) and video encoder  1/4-inch optical format, VGA resolution (640H x 480V)  ±2.5% additional columns and rows to compensate for lens alignment tolerances  Integrated lens distortion correction  Overlay generator for dynamic bitmap overlay  Integrated video encoder for NTSC/PAL with overlay capability and 10-bit I-DAC  Integrated microcontroller for flexibility  On-chip image flow processor performs sophisticated processing, such as color recovery and correction, sharpening, gamma, lens shading correction, on-the-fly defect correction, auto white balancing, and auto exposure  Auto black level calibration  10-bit, on-chip analog-to-digital converter (ADC)  Internal master clock generated by on-chip phase- locked loop (PLL)  Two-wire serial programming interface  Interface to low-cost Flash through SPI bus  High-level host command interface  Stand alone operation support  Comprehensive tool support for overlay generation and lens correction setup  Development system with DevWare  Overlay generation and compilation tools

Applications

 Automotive rearview camera and side mirror  Blind spot and surround view  Key parameters are continued on next page. See details of new features on page 3. See “Ordering Information” on page 3. Table 1: Key Parameters Parameter Typical Value Pixel size and type 5.6 m x 5.6 m active pinned- photodiode with high-sensitivity mode for low-light conditions Sensor format 680H x 512V (includes ±2.5% of rows and columns for lens alignment) NTSC output 720H x 480V PAL output 720H x 576V Imaging area Total array size: 3.584 mm x 2.688 mm Optical format ¼-inch Frame rate 50/60 fields/sec Sensor scan mode Progressive scan Color filter array RGB standard Bayer Shutter type Electronic rolling shutter (ERS) Automatic Functions Exposure, white balance, black level offset correction, flicker avoidance, color saturation control, on-the-fly defect correction, aperture correction Programmable Controls Exposure, white balance, horizontal and vertical blanking, color, sharpness, gamma correction, lens shading correction, horizontal and vertical image flip, zoom, windowing, sampling rates, GPIO control Lens distortion correction Maximum lens distortion supported up to 25% Flexible algorithm that can be calibrated for many wide-angle lenses through software tools Perspective correction

MT9V126_DS Rev. J Pub. 5/15 EN 2 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Notes: 1. Lens distortion correction and graphical overlay is available only in CCIR656 output format. 2. Analog output enabled; parallel output disabled. Table 2: Key Parameters (continued) Parameter Typical Value Overlay Support1 Utilizes SPI interface to load overlay data from external flash/EEPROM memory with the following features:

• Overlay Size 360 x 480 pixel rendered into 720 x 480 pixel display format
• Up to four (4) overlays may be blended simultaneously
• Selectable readout: Rotating order user selected
• Dynamic scenes by loading pre-rendered frames from external memory
• Palette of 32 colors out of 64,000
• 8 colors per bitmap
• Blend factor dynamically programmable for smooth transitions
• Fast Update rate of up to 30 fps
• Every bitmap object has independent x/y position
• Statistic Engine to calibrate optical alignment
• Number Generator External Overlay Processing Support Digital input to on-chip NTSC encoder allows for external overlay, processing by a DSP , or FPGA Windowing Programmable to any size Max analog gain 0.5–16x ADC 10-bit, on-chip Output interface Analog composite video out, single-ended or differential; 8-, 10-bit parallel digital output Output data formats

1 Digital: Raw Bayer 8-,10-bit, CCIR656, 565RGB, 555RGB, 444RGB

Parallel: 27 MB/s NTSC: 60 fields/sec PAL: 50 fields/sec Control interface Two-wire I/F for register interface plus high-level command exchange. SPI port to interface to external memory to load overlay data, register settings, or firmware extensions. Input clock for PLL 27 MHz SPI Clock Frequencies 4.5 - 9.0 - 18 MHz, programmable Supply voltage Analog: 2.8 V ±5% Core: 1.8 V ±5% IO: 2.8V ±5% Power consumption Full resolu tion at 60 fps: <350mW Package 63-BGA, 9mm x 9mm, 1mm pin pitch Ambient temperature Operating: –40 °C to 105°C Functional: –40°C to +85°C Storage: –50°C to +150°C Dark Current < 200e/s at 60°C with a gain of 1 Fixed pattern noise Column < 2% Row < 2% Responsivity 11.9 V/lux-s at 550nm Signal to noise ratio (S/N) 45 dB Pixel dynamic range 74.6 dB

MT9V126_DS Rev. J Pub. 5/15 EN 3 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor New Features New Features Integrated Lens Distortion Correction  Eliminates expensive DSP for image correction  Can be calibrated for wide-angle lenses of up to 180 degree horizontal FOV (field of view)  Distortion correction for up to 25% distortion in FOV  Perspective correction – View from elevated angle Integrated Video Encoder for PAL/NTSC with Overlay Capability  Composite analog output (NTSC/PAL)  8-bit parallel digital output ITU-R BT .656 format  Raw Bayer format  Digital input to on-chip NTSC encoder to allow additional processing functions by external DSP or FPGA On-Chip Overlay Generator  Static and dynamic overlay graphics with four overlay planes plus number plane  Support for serial SPI memory up to 16 megabytes N u m b e r g e n e r a t o r  Overlay blending and x/y positioning  Overlay position adjustment and stat istics engine to calibrate overlay  Overlay support utilizes SPI interface to load overlay data from external Serial Flash/EEPROM to support the following features: – Overlay size 360 x 480 pixel rendered into 720 x 480 pixel display format – Up to four overlays may be blended simultaneously – Selectable readout: rota ting order user selected – Dynamic scenes by loading pre-rendered frames from external memory – Palette of 32 colors out of 64,000 – Eight colors per bitmap – Blend factor dynamically programmable for smooth transitions – Fast update rate of up to 30 fps – Every bitmap object has independent x/y position – Statistics engine to calibrate optical alignment – External overlay processing supports digi tal input to on-chip NTSC encoder; this enables external overlay processing by a DSP or FPGA

Ordering Information

Table 3: Available Part Numbers Part Number Product Description Orderable Product Attribute Description MT9V126D00XTCK22BC1-200 VGA 1/4" SOC Die Sales, 200 m Thickness MT9V126IA3XTC-DP VGA 1/4" SOC Dry Pack with Protective Film MT9V126IA3XTC-DR VGA 1/4" SOC Dry Pack without Protective Film MT9V126IA3XTC-DR1 VGA 1/4" SOC Dry Pack Single Tray without Protective Film

MT9V126_DS Rev. J Pub. 5/15 EN 4 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor MT9V126IA3XTC-TP VGA 1/4" SOC Tape & Reel with Protective Film MT9V126IA3XTC-TR VGA 1/4" SOC Tape & Reel without Protective Film Table 3: Available Part Numbers Part Number Product Description Orderable Product Attribute Description

MT9V126_DS Rev. J Pub. 5/15 EN 5 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Table of Contents Table of Contents

MT9V126_DS Rev. J Pub. 5/15 EN 8 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor List of Tables List of Tables

MT9V126_DS Rev. J Pub. 5/15 EN 9 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor List of Tables

MT9V126_DS Rev. J Pub. 5/15 EN 10 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor General Description General Description The ON Semiconductor MT9V126 is a VGA-format, single-chip CMOS active-pixel digital image sensor for automotive applications. It captures high-quality color images at VGA resolution and outputs NTSC or PAL interlaced composite video. The VGA CMOS image sensor features ON Semiconductor’ s breakthrough low-noise CMOS imaging technology that achieves near-CCD image quality (based on signal-to- noise ratio and low-light sensitivity) while maintaining the inherent size, cost, low power, and integration advantages of ON Semiconductor's advanced active pixel CMOS process technology. The MT9V126 is a complete camera-on-a-chip. It incorporates sophisticated camera functions on-chip and is programmable through a simple two-wire serial interface or by an attached SPI Flash memory that contains setup information that may be loaded auto- matically at startup. The MT9V126 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, 50Hz/60Hz flicker avoidance, lens shading correction, auto white balance (AWB), and on-the-fly defect identification and correction. The MT9V126 outputs interlaced-scan images at 30 or 25 fps, supporting both NTSC and PAL video formats. The image data can be output on one or two output ports:  Composite analog video (single-end ed and differential output support)  Parallel 8-, 10-bit digital The integrated lens correction and overlay generation for steering guidance eliminates expensive overlay processing that is usually required by an external DSP; this signifi- cantly reduces overall costs.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Architecture MT9V126_DS Rev. J Pub. 5/15 EN 11 ©Semiconductor Components Industries, LLC,2015. Architecture Internal Block Diagram Figure 1: Internal Block Diagram Note: The active array is smaller than the sensor array. Image Flow Processor Color & Gamma Correction Color S pace Conversion E dge E nhancement Camera Control AWB AE Overlay Graphics Generation¼” VGA ROI @ 60 frames per sec. 640 x 480 Active Array VideoEncoder DAC SPI & 2 W I/F Interface SPI 4 2 NTSC / PAL BT -656 Optional BT -656 Input 2. 8V 1.8VTwo-Wire I/F Lens correction

MT9V126_DS Rev. J Pub. 5/15 EN 12 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor System Block Diagram System Block Diagram The system block diagram will depend on the application. The system block diagram in Figure 2 shows all components; optional peripheral components are highlighted. Control information will be received by a microcontroller through the automotive bus, such as LIN or CAN bus, to communicate with the MT9V126 through its two-wire serial bus. Optional components will vary by application. For further details, see the MT9V126 Register and Variable Reference. Figure 2: System Block Diagram SPI Serial Data Flash 10Kb - 16MB LP Filter

27 MHz

DAC _POS μC 2WIRE I/F Composite Video PAL / NTSC VAA (2.8V) VAA _PIX (2.8V ) VDD (1 .8 V) EXTCLK System Bus CAN / LIN 4.7kΩ DAC_REF 2.8V DAC _NEG LDO VDD_IO (2.8V). CCIR 656/ GPOCCIR 656/ or GPI Optional XTAL 75Ω VDD_PLL (2.8V). VDD_DAC (2.8V) RESET_BAR FRAME _SYNC PIXCLK FRAME_VALID LINE_VALID DIN _CL K DIN [7 :0 ] DOUT_LSB0 ,1 DOUT[7:0]

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor System Block Diagram MT9V126_DS Rev. J Pub. 5/15 EN 13 ©Semiconductor Components Industries, LLC,2015. Crystal Usage As an alternative to using an external oscillator, a fundamental 27 MHz crystal may be connected between EXTCLK and XTAL. Two small loading capacitors of 15–22pF of NPO dielectric should be added as shown in Figure 3. ON Semiconductor does not recommend using the crystal option for automotive appli- cations above 85 °C. A crystal oscillator with temperature compensation is recom- mended. Figure 3: Using a Crystal Instead of an External Oscillator When using Xtal as the clock source, the internal inverter circuit has a 100K bias resistor in parallel to Xtal, which can be connected or disconnected by register 0x0014 bit[14]. The clockin_bias_en bit is set to 1 by default. EXTCLK XTAL 18pF -NPO

27.000 MHz

MT9V126_DS Rev. J Pub. 5/15 EN 14 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Pin Descriptions and Assignments Pin Descriptions and Assignments Table 4: Pin Descriptions Pin Number Pin Name Type Description Clock and Reset B1 EXTCLK Input Master input clock (27MHz): This can either be a square-wave generated from an oscillator (in which case the XTAL input must be left unconnected) or connected directly to a crystal. B2 XTAL Output If EXTCLK is connected to one pin of a crystal, this signal is connected to the other pin; otherwise this signal must be left unconnected. C1 RESET_BAR Input Asynchronous active-low rese t: When asserted, the device will return all interfaces to their reset state. When released, the device will initiate the boot sequence. C2 FRAME_SYNC Input This input can be used to set the output timing of the MT9V126 to a fixed point in the frame. The input buffer associated with this input is permanently enabled. This signal should be connected to GND if not used. Register Interface G3 SCLK Input These two signals implement serial communications protocol for access to the internal registers and variables.H3 S DATA Input/OD H2 S ADDR Input This signal controls the device ID that will respond to serial communication commands. Two-wire serial interface device ID selection: 0: 0x90 1: 0xBA SPI Interface H5 SPI_SCLK Output Clock output for interfacin g to an external SPI memory such as Flash/ EEPROM. Tristate when RESET_BAR is asserted. G5 SPI_SDI Input Data in from SPI device. This signal has an internal pull-up resistor. H4 SPI_SDO Output Data out to SPI device. Tristate when RESET_BAR is asserted. G4 SPI_CS_N Output Chip selects to SPI device. Tristated when RESET_BAR is asserted. (Parallel) Pixel Data Input D1 D IN_CLK Input Pixel clock input: Data on D IN[7:0] are sampled at the rising or falling edge of this clock. (Alternatively, an internal sampling clock may be used.) H1, G1, F1, G2, F2, E1, E2, DIN[7:0] Input Data coming in on this interface is passed through the overlay blender and to the video encoder output. The input buffers associated with inputs 7 to 0 are powered down by default. This allows these signals to be left unconnected if not required. These inputs can also be used as general purpose inputs. (Parallel) Pixel Data Output E7 FRAME_VALID Input/Output Pixel data from the MT 9V126 can be routed out on this interface and processed externally. To save power, these signals are driven to a constant logic level unless the parallel pixel data output or alternate (GPIO) function is enabled for these pins. For more information see Table 16 on page 37. This interface is disabled by default. The slew rate of these outputs is programmable. These signals can also be used as general purpose input/outputs. E6 LINE_VALID Input/Output E8 PIXCLK Output C7, B6, C8, B7, B8, A6, A7, A8 D OUT[7:0] Output

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Pin Descriptions and Assignments MT9V126_DS Rev. J Pub. 5/15 EN 15 ©Semiconductor Components Industries, LLC,2015. D7 D OUT_LSB1 Input/Output When the sensor core is running in bypass mode, it will generate 10 bits of output data per pixel. These two pins make the two LSB of pixel data available externally. Leave unconnected if not used. To save power, these signals are driven to a constant logic level unless the sensor core is running in bypass mode or the alternate function is enabled for these pins. For more information see Table 16, “GPIO Bit Descriptions,” on page 37. This interface is disabled by default. The slew rate of these outputs is programmable. D8 D OUT_LSB0 Input/Output Composite Video Output B3 DAC_POS Output Positive video DAC output in differential mode. Video DAC output in single-ended mode. This interface is enabled by default using NTSC/PAL signalling. For applications where composite video output is not required, the video DAC can be placed in a power-down state under software control. A4 DAC_NEG Output Negative video DAC output in differential mode. Connect to A GND in single- ended mode. A2 DAC_REF Output External reference resistor for the video DAC. Manufacturing Test Interface D6 TDI Input JTAG Test pin (Reserved for Test Mode) C6 TDO Output JTAG Test pin (Reserved for Test Mode) F3 TMS Input JTAG Test pin (Reserved for Test Mode) F4 TCK Input JTAG Test pin (Reserved for Test Mode) F5 TRST_N Input Connect to GND. F6 ATEST1 Input Analog test input. Connect to GND in normal operation. G6 ATEST2 Input Analog test input. Connect to GND in normal operation. Power C3, D3, E3 V DD Supply Supply for V DD core: 1.8V nominal. C5, D5, E5 V DD_IO Supply Supply for digital IOs: 2.8V nominal. A5 V DD_DAC Supply Supply for video DAC: 2.8V nominal. B5 V DD_PLL Supply Supply for PLL: 2.8V nominal. G7, G8 V AA Supply Analog power: 2.8V nominal. F7, F8 V AA_PIX Supply Analog pixel array power: 2.8V nomina l. Must be at same voltage potential as VAA. A3 GND_DAC Supply Video DAC ground B4, C4, D4, E4 D GND Supply Digital ground. H6, H7, H8 A GND Supply Analog ground. Table 4: Pin Descriptions (continued) Pin Number Pin Name Type Description

MT9V126_DS Rev. J Pub. 5/15 EN 16 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Pin Descriptions and Assignments Pin Assignments Pin 1 is not populated with a ball. That allows the device to be identified by an additional marking. Table 5: Pin Assignments 1 2 3 4 5 6 7 8 A DAC_REF GND_DAC DAC_NEG V DD_DAC D OUT2D OUT1D OUT0 BE X T C L K X T A L D A C _ P O S G N D V DD_PLL D OUT6D OUT4D OUT3 C RESET_BAR FRAME_SYNC V DD GND V DD_IO TDO D OUT7D OUT5 DD IN_CLK D IN0V DD GND V DD_IO TDI D OUT_LSB1 D OUT_LSB0 ED IN2D IN1V DD GND V DD_IO LINE_VALID FRAME_VALID PIXCLK FD IN5D IN3T M ST C K T R S T _ N A T E S T 1 V AA_PIX V AA_PIX GD IN6D IN4 SCLK SPI_CS_N SPI_SDI ATEST2 V AA VAA HD IN7S ADDR SDATA SPI_SDO SPI_SCLK A GND AGND AGND Table 6: Reset/Default State of Interfaces Name Reset State Default State Notes EXTCLK Clock running or stopped Clock running Input XTAL N/A N/A Input RESET_BAR Asserted De-asserted Input SCLK N/A N/A Input. Must always be driven to a valid logic level. SDATA High impedance High impedance Input/Output. A valid logic level should be established by pull-up resistor. SADDR N/A N/A Input. Must always be driven to a valid logic level. Must be permanently tied to VDD_IO or GND. SPI_SCLK High impedance. Driven, logic 0 Output. Output enable is R0x0032[9]. SPI_SDI Internal pull-up enab led. Internal pull-up enabled Input. Internal pull-up is permanently enabled. SPI_SDO High impedance Driven, logic 0 Output enable is R0x0032[9]. SPI_CS_N High impeda nce Driven, logic 1 Output enable is R0x0032[9]. DINCLK Input buffer powered down Input buffer powered down Input. This interface is disabled by default, and the input buffers are powered down. If this interface is not required, these pins can be left unconnected (floating). D IN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Pin Descriptions and Assignments MT9V126_DS Rev. J Pub. 5/15 EN 17 ©Semiconductor Components Industries, LLC,2015. Notes: 1. The reason for defining the default state as lo gic 0 rather than high impedance is this: when wired in a system (for example, on our demo boards), these outputs will be connected, and the inputs to which they are connected will want to see a valid logic level. No current drain should result from driving these to a valid logic level (unless there is a pull-up at the system level). 2. These pads have their input circuitry powered down, but they are not output-enabled. Therefore, they can be left floating but they will not drive a valid logic level to an attached device. FRAME_VALID High impedance High impedance Input/Output. This interface disabled by default. Input buffers (used for GPIO function) powered down by default, so these pins can be left unconnected (floating). After reset, these pins are powered up, sampled, then powered down again as part of the auto- configuration mechanism. See Note 2. LINE_VALID PIXCLK High impedance Driven, logic 0 Output. This interface disabled by default. See Note 1. D OUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 DOUT_LSB1 High impedance High impedance Input/Output. This interface disabled by default. Input buffers (used for GPIO function) powered down by default, so these pins can be left unconnected (floating). After reset, these pins are powered-up, sampled, then powered down again as part of the auto- configuration mechanism. D OUT_LSB0 High impedance Driven, logic 0 DAC_POS High impedance Driven Output. Interface disabled by hardware reset and enabled by default when the device starts streaming. DAC_NEG DAC_REF TDI Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can be left unconnected (floating). TDO High impedance High impedance Output. Driven only during appropriate parts of the JTAG shifter sequence. TMS Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can be left unconnected (floating). TCK Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can be left unconnected (floating). TRST_N N/A N/A Input. Must always be driven to a valid logic level. Must be driven to GND for normal operation. FRAME_SYNC N/A N/A Input. Must always be driven to a valid logic level. Must be driven to GND for normal operation. ATEST1 Must be driven to GND for normal operation. ATEST2 Must be driven to GND for normal operation. Table 6: Reset/Default State of Interfaces (continued) Name Reset State Default State Notes

MT9V126_DS Rev. J Pub. 5/15 EN 20 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Sensor Pixel Array The active pixel array is 640 x 480 pixels. In addition, there are rows and columns for lens alignment and demosaic. Not shown in Figure 7 are pixels for black level calibration. Figure 7: Sensor Pixel Array The range of adjustment is from Row 0 to 22 and Column 0 to 30. There are 4 rows/ columns needed to calculate the RGB values. The window should be moved only at even numbers. Figure 8: Pixel Color Pattern Detail (top right corner) Lens Alignment Pixels - 16 Columns Lens Alignment Pixels - 12 Rows Lens Alignment Pixels - 12 Rows Lens Alignment Pixels - 16 Columns Demosaic Pixels - 4 Columns Demosaic Pixels - 4 Columns Demosaic Pixels - 4 Rows Demosaic Pixels - 4 Rows Active Pixels

640 Rows, 480 Columns

... Row Readout Direction R G R G B G First Active Border Pixel (64, 0) R G R G B G R G R G B G G B G G R G B G B G R G B G B G R G B G B B G B

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array MT9V126_DS Rev. J Pub. 5/15 EN 21 ©Semiconductor Components Industries, LLC,2015. Output Data Format The sensor core image data are read out in progressive scan order. Valid image data are surrounded by horizontal and vertical blanking, shown in Figure 9. For NTSC output, the horizontal size is stretched from 640 to 720 pixels. The vertical size is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of the image field. For PAL output, the horizontal size is also stretched from 640 to 720 pixels. The vertical size is 288 pixels per field. Figure 9: Spatial Illustration of Image Readout Valid Image Odd Field Horizontal Blanking Vertical Even Blanking Vertical/Horizontal Blanking Valid Image Even Field Horizontal Blanking Vertical Odd Blanking Vertical/Horizontal Blanking

MT9V126_DS Rev. J Pub. 5/15 EN 22 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Image Flow Processor Image and color processing in the MT9V126 are implemented as an image flow processor (IFP) coded in hardware logic. During normal operation, the embedded microcontroller will automatically adjust the operation parameters. The IFP is broken down into different sections, as outlined in Figure 10. Figure 10: Color Pipeline Test Pattern Generator Black Level Subtraction Color Correction Aperture Correction Gamma Correction (12-to-8 Lookup) Statistics Engine Color Kill Output Formatting YUV to RGB Raw Data 10/12-Bit RGB RAW 10 8-bit RGB 8-bit YUV Parallel Output Output Interface RGB to YUV Digital Gain Control Lens Shading Correction Defect Correction, Noise Reduction, Color Interpolation MUX IFP Parallel Output Mux Pixel Array ADC Analog Output Mux NTSC/PAL

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array MT9V126_DS Rev. J Pub. 5/15 EN 23 ©Semiconductor Components Industries, LLC,2015. Test Patterns During normal operation of the MT9V126, a stream of raw image data from the sensor core is continuously fed into the color pipeline. For test purposes, this stream can be replaced with a fixed image generated by a special test module in the pipeline. The module provides a selection of test patterns sufficient for basic testing of the pipeline. Test patterns are accessible by programming a register and are shown in Figure 11. ON Semiconductor recommends disabling the MCU before enabling test patterns. Figure 11: Color Bar Test Pattern Test Pattern Example Flat Field Vertical Ramp Color Bar Vertical Stripes Pseudo-Random

MT9V126_DS Rev. J Pub. 5/15 EN 24 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array NTSC/PAL Test Pattern Generation There is a built-in standard EIA (NTSC) and EBU (PAL) color bars to support hue and color saturation characterization. Each pattern consists of seven color bars (white, yellow, cyan, green, magenta, red, and blue). The Y, Cb and Cr values for each bar are detailed in Tables 7 and 8. The test pattern is invoked through a Host Command call to the TX Manager. See the MT9V126 Host Command Specification. Figure 12: Color Bars CCIR-656 Format The color bar data is encoded in 656 data streams. The duration of the blanking and active video periods of the generated 656 data are summarized in the following tables. Table 7: EIA Color Bars (NTSC) Nominal Range White Yellow Cyan Green Magenta Red Blue Y 16 to 235 180 162 131 112 84 65 35 Cb 16 to 240 128 44 156 72 184 100 212 Cr 16 to 240 128 142 44 58 198 212 114 Table 8: EBU Color Bars (PAL) Nominal Range White Yellow Cyan Green Magenta Red Blue Y 16 to 235 235 162 131 112 84 65 35 Cb 16 to 240 128 44 156 72 184 100 212 Cr 16 to 240 128 142 44 58 198 212 114 Table 9: NTSC Line Numbers Field Description 1-3 2 Blanking 4-19 1 Blanking 20-263 1 Active video 264-265 1 Blanking 266-282 2 Blanking 283-525 2 Active Video

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array MT9V126_DS Rev. J Pub. 5/15 EN 25 ©Semiconductor Components Industries, LLC,2015. Black Level Subtraction and Digital Gain Image stream processing starts with black level subtraction and multiplication of all pixel values by a programmable digital gain. Both operations can be independently set to separate values for each color channel (R, Gr, Gb, B). Independent color channel digital gain can be adjusted with registers. Independent color channel black level adjust- ments can also be made. If the black level subtraction produces a negative result for a particular pixel, the value of this pixel is set to 0. Positional Gain Adjustments (PGA) Lenses tend to produce images whose brightness is significantly attenuated near the edges. There are also other factors causing fixed pattern signal gradients in images captured by image sensors. The cumulative result of all these factors is known as image shading. The MT9V126 has an embedded shading correction module that can be programmed to counter the shading effects on each individual R, Gb, Gr, and B color signal. The Correction Function The correction functions can then be applied to each pixel value to equalize the response across the image as follows: (EQ 1) where P are the pixel values and f is the color dependent correction functions for each color channel. Color Interpolation In the raw data stream fed by the sensor core to the IFP , each pixel is represented by a 10-bit integer number, which can be considered proportional to the pixel's response to a one-color light stimulus, red, green, or blue, depending on the pixel's position under the color filter array. Initial data processing steps, up to and including the defect correction, preserve the one-color-per-pixel nature of the data stream, but after the defect correc- tion it must be converted to a three-colors-per-pixel stream appropriate for standard color processing. The conversion is done by an edge-sensitive color interpolation module. The module pads the incomplete color information available for each pixel with information extracted from an appropriate set of neighboring pixels. The algorithm used to select this set and extract the information seeks the best compromise between preserving edges and filtering out high frequency noise in flat field areas. The edge threshold can be set through register settings. Table 10: PAL Line Numbers Field Description 1-22 1 Blanking 23-310 1 Active video 311-312 1 Blanking 313-335 2 Blanking 336-623 2 Active video 624-625 2 Blanking Pcorrected(row,col)=P sensor(row,col)*f(row,col)

MT9V126_DS Rev. J Pub. 5/15 EN 26 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array Color Correction and Aperture Correction To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are subjected to color correction. The IFP multiplies each vector of three pixel colors by a 3 x 3 color correction matrix. The three components of the resulting color vector are all sums of three 10-bit numbers. Since such sums can have up to 12 significant bits, the bit width of the image data stream is widened to 12 bits per color (36 bits per pixel). The color correction matrix can be either programmed by the user or automatically selected by the auto white balance (AWB) algorithm implemented in the IFP . Color correction should ideally produce output colors that are corrected for the spectral sensitivity and color crosstalk characteristics of the image sensor. The optimal values of the color correction matrix elements depend on those sensor characteristics and on the spectrum of light incident on the sensor. The color correction variables can be adjusted through register settings. To increase image sharpness, a programmable 2D aperture correction (sharpening filter) is applied to color-corrected image data. The gain and threshold for 2D correction can be defined through register settings.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array MT9V126_DS Rev. J Pub. 5/15 EN 27 ©Semiconductor Components Industries, LLC,2015. Gamma Correction The MT9V126 IFP includes a block for gamma correction that can adjust its shape based on brightness to enhance the performance under certain lighting conditions. Two custom gamma correction tables may be uploaded corresponding to a brighter lighting condition and a darker lighting condition. At power-up, the IFP loads the two tables with default values. The final gamma correction table used depends on the brightness of the scene and takes the form of an interpolated version of the two tables. The gamma correction curve (as shown in Figure 13) is implemented as a piecewise linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit output. The abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit ordinates are programmable through IFP registers. Figure 13: Gamma Correction Curve RGB to YUV Conversion For further processing, the data is converted from RGB color space to YUV color space. Color Kill To remove high-or low-light color artifacts, a color kill circuit is included. It affects only pixels whose luminance exceeds a certain preprogrammed threshold. The U and V values of those pixels are attenuated proportionally to the difference between their lumi- nance and the threshold. YUV Color Filter As an optional processing step, noise suppression by one-dimensional low-pass filtering of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.

MT9V126_DS Rev. J Pub. 5/15 EN 28 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array YUV-to-RGB/YUV Conversion and Output Formatting The YUV data stream emerging from the scaling module can either exit the color pipe- line as-is or be converted before exit to an alternative YUV or RGB data format. Output Format and Timing YUV/RGB Data Ordering The MT9V126 supports swapping YCbCr mode, as illustrated in Table 11. The RGB output data ordering in default mode is shown in Table 12. The odd and even bytes are swapped when luma/chroma swap is enabled. R and B channels are bit-wise swapped when chroma swap is enabled. Uncompressed 10-Bit Bypass Output Raw 10-bit Bayer data from the sensor core can be output in bypass mode in two ways:  Using 8 data output signals (D OUT[7:0]) and GPIO[1:0]. The GPIO signals are the least significant 2 bits of data.  Using only 8 signals (D OUT[7:0]) and a special 8 + 2 data format, shown in Table 13. Readout Formats Progressive format is used for raw Bayer output. Table 11: YCbCr Output Data Ordering Mode Data Sequence Default (no swap) Cb i Yi Cri Yi+1 Swapped CbCr Cr i Yi Cbi Yi+1 Swapped YC Y i Cbi Yi+1 Cri Swapped CbCr, YC Y i Cri Yi+1 Cbi Table 12: RGB Ordering in Default Mode Mode (Swap Disabled) Byte D7D6D5D4D3D2D1D0 565RGB Odd R 7R6R5R4R3G7G6G5 Even G 4G3G2B7B6B5B4B3 555RGB Odd 0 R 7R6R5R4R3G7G6 Even G 5G4G3B7B6B5B4B3 444xRGB Odd R 7R6R5R4G7G6G5G4 Even B 7B6B5B4 0 0 0 0 x444RGB Odd 0 0 0 0 R 7R6R5R4 Even G 7G6G5G4B7B6B5B4 Table 13: 2-Byte Bayer Format Byte Bits Used Bit Sequence Odd bytes 8 data bits D 9D8D7D6D5D4D3D2 Even bytes 2 data bits + 6 unused bits 0 0 0 0 0 0 D 1D0

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Sensor Pixel Array MT9V126_DS Rev. J Pub. 5/15 EN 29 ©Semiconductor Components Industries, LLC,2015. Output Formats ITU-R BT.656 and RGB Output The MT9V126 can output processed video as a standard ITU-R BT.656 (CCIR656) stream, an RGB stream, or as unprocessed Bayer data. The ITU-R BT .656 stream contains YCbCr 4:2:2 data with fixed embedded synchronization codes. This output is typically suitable for subsequent display by standard video equipment or JPEG/MPEG compression. Colorpipe data (pre-lens correction and overlay) can also be output in YCbCr 4:2:2 and a variety of RGB formats in 640 by 480 progressive format in conjunction with LINE_VALID and FRAME_VALID. The MT9V126 can be configured to output 16-bit RGB (565RGB), 15-bit RGB (555RGB), and two types of 12-bit RGB (444RGB). Refer to Table 31 and Table 32 on page 66 for details. Bayer Output Unprocessed Bayer data are generated when bypassing the IFP completely—that is, by simply outputting the sensor Bayer stream as usual, using FRAME_VALID, LINE_VALID, and PIXCLK to time the data. This mode is called sensor stand-alone mode. Output Ports Composite Video Output The composite video output DAC is external-resistor-programmable and supports both single-ended and differential output. The DAC is driven by the on-chip video encoder output. Parallel Output Parallel output uses either 8-bit or 10-bit output. Eight-bit output is used for ITU-R BT .656 and RGB output. Ten-bit output is used for raw Bayer output.

MT9V126_DS Rev. J Pub. 5/15 EN 32 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Overlay External Overlay In addition to the on-chip overlay generator, an externally generated overlay may be superimposed onto the video output. Figure 19: External Overlay System Block Diagram SPI Serial data Flash 10Kb to 16MB LP filter VIDEO_P CVBS PAL/NTSC EXTCLK VIDEO_N DOUT [7 :0] PIXCLK Overlay FPGA/DSP DINCLK DIN [7 :0 ]

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Multicamera Support MT9V126_DS Rev. J Pub. 5/15 EN 33 ©Semiconductor Components Industries, LLC,2015. Multicamera Support Two or more MT9V126 sensors may be synchronized to a frame by asserting the FRAME_SYNC signal. At that point, the sensor and video encoder will reset without affecting any register settings. The MT9V126 may be triggered to be synchronized with another MT9V126 or an external event. Figure 20: Multicamera System Block Diagram Decoder / DSP Camera 1 Camera 2 CVBS CVBS CAN μC MT9V126 MT9V126 F_ SYNC OSC F_ S Y N C Dual Camera

MT9V126_DS Rev. J Pub. 5/15 EN 34 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing External Signal Processing An external signal processor can take data from ITU656 or raw Bayer output format and post-process or compress the data in various formats. Figure 21: External Signal Processing Block Diagram Device Configuration After power is applied and the device is out of reset by de-asserting the RESET_BAR pin, it will enter a boot sequence to configure its operating mode. There are essentially four modes, two when Flash is present and two when Flash is not present. Figure 22: “Power- Up Sequence – Configuration Options Flow Chart,” on page 36 contains more details on the configuration options. If Flash is present and:  A valid Flash device identifier is detected AND the Flash device contains valid config- uration records, then – Disable Auto-Config – Parse Flash Content – Load Flash Configuration ->Flash Configuration Mode  A valid Flash device identifier is detected BUT the Flash device DOES NOT contain valid configuration records, then – Enter Auto Configuration. If Flash is not present and:  SPI_SDI == 0, then – Enter Host Configuration.  SPI_SDI != 0, then – Enter Auto Configuration SPI Serial data Flash 10Kb to 16MB VIDEO_P CVBS PAL/NTSC EXTCLK VIDEO_N DOUT [7:0] PIXCLK Signal processor

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing MT9V126_DS Rev. J Pub. 5/15 EN 35 ©Semiconductor Components Industries, LLC,2015. Auto-Configuration The device supports an auto-configuration feature. During system start-up, the device first detects whether an SPI Flash device is attached to the MT9V126. If not, it will then sample the state of a number of GPI inputs including FRAME_VALID, LINE_VALID and DOUT_LSB0. For more information, see Table 16, “GPIO Bit Descriptions,” on page 37. The state of these inputs then determines the configuration of a number of subsystems of the device such as readout mode, pedestal and video format, respectively. The auto-configuration feature can be disabled by grounding the SPI_DIN pin. The device samples the state of this pin during the Flash device detection process. If no SPI Flash device is detected (read device ID of 0x00 or 0xFF), OR the SPI_DIN pin is grounded, then auto-configuration is disabled. Flash Configuration Mode If a valid Flash is detected (by reading device ID other than 0x00 or 0xFF) and the flash device contains valid configuration records, then these configuration records are processed. Host Configuration This mode is entered if the SPI_DIN pin is grounded. The SOC performs no configura- tion, and remains idle waiting for configuration and instruction from the host.

MT9V126_DS Rev. J Pub. 5/15 EN 36 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Power Sequence In power-up, the core voltage (1.8V) must trail the IO (2.8V) by a positive number. All 2.8V rails can be turned on at the same time or follow the power-up sequence in Figure 52: “Power Up Sequence,” on page 72. In power down, the sequence is reversed. The core voltage (1.8V) must be turned off before any 2.8V . Refer to Figure 53: “Power Down Sequence,” on page 73 for details. Figure 22: Power-Up Sequence – Configuration Options Flow Chart Supported SPI Devices Table 14 lists supported Flash devices. Devices not compatible will require a firmware patch. Contact ON Semiconductor for additional support. Table 14: SPI Flash Devices Type Density Manufacturer Device Speed (MHz) Standard Temp Range (°F) Supported Flash 8 MB Atmel AT26DF081A 70 JEDEC/Device ID –20 to +85 Yes Flash 1 MB ST M25P10-AVMB3 50 –40 to +125 Yes Power Up/R E S E T Flash Header? Auto Configuration: FRAME _ VALID , LINE_ VALID , DOUT_LSB0 SPI _SDI = 0? Wait for Host Command Wait for Host Command Disable Auto -Config Parse Flash Content Wait for Host Command yes no yes FRAME_VALID LINE _VALID DOUT_LSB0 0: Normal 1: Horizontal Mirror

0 No Pedestal

1: Pedestal 0: NTSC 1: PAL Disable Auto -Config no Flash Configuration: Host Configuration : Host Configuration:

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing MT9V126_DS Rev. J Pub. 5/15 EN 37 ©Semiconductor Components Industries, LLC,2015. Supported SPI Commands The SPI commands shown in Table 15 are supported by the MT9V126. Table 15: SPI Commands Supported Command Value Read Array 0x03 Block Erase 0xD8 Chip Erase 0xC7 Read Status 0x05 Write status 0x01 Byte Page Program 0x02 Write Enable 0x06 Write Disable 0x04 Read Manufacturer and Device ID 0x9F (Fast) Read Array 0x0B Table 16: GPIO Bit Descriptions GPI[2] (DOUT_LSB0) GPI[1] (FRAME_VALID) GPI[0] (LINE_VALID) Low (“0”) NTSC Normal No pedestal High (“1”) PAL Horizontal mirror Pedestal

MT9V126_DS Rev. J Pub. 5/15 EN 38 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Host Command Interface ON Semiconductor’ s sensors and SOCs contain numerous registers that are accessed through a two-wire interface with speeds up to 400 kHz. The MT9V126, in addition to writing or reading straight to/from registers or firmware variables, has a mechanism to write higher level commands, the Host Command Inter- face (HCI). Once a command has been written through the HCI, it will be executed by on chip firmware and the results are reported back. In general, registers shall not be accessed with the exception of registers that are marked for “User Access.” Flash memory is also available to store commands for later execution. Under DMA control, a command is written into the SOC and executed. For a complete spec on host commands, refer to the MT9V126 Host Command Interface Specification. Figure 23: Interface Structure Host Command to FW Response from FW 15 0bit command registerAddr 0x40 Addr 0xFC00 Addr 0xFC0E Addr 0xFC02 Addr 0xFC04 Addr 0xFC06 Addr 0xFC08 Addr 0xFC0A Addr 0xFC0C door bell 15 0bit Parameter 0 Parameter 7 cmd_handler_params_pool_0 cmd_handler_params_pool_1 cmd_handler_params_pool_2 cmd_handler_params_pool_3 cmd_handler_params_pool_4 cmd_handler_params_pool_5 cmd_handler_params_pool_6 cmd_handler_params_pool_7

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing MT9V126_DS Rev. J Pub. 5/15 EN 39 ©Semiconductor Components Industries, LLC,2015. Host Command Process Flow Command Flow The host issues a command by writing (through a two-wire interface bus) to the command register. All commands are encoded with bit 15 set, which automatically generates the host command (doorbell) interrupt to the microprocessor. Assuming initial conditions, the host first writes the command parameters (if any) to the parameters pool (in the command handler's logical page), then writes the command to command register. The interrupt handler then signals the command handler task to process the command. If the host wishes to determine the outcome of the command, it must poll the command register waiting for the doorbell bit to be cleared. This indicates that the firmware completed processing the command. The contents of the command register indicate the command's result status. If the command generated response parameters, the host can now retrieve these from the parameters pool. Re ad Co m m and reg ister Doo rb e ll bi t c l ear ? No Co m m and h a s p a ra mete rs ? Ye s Writ e par amete rs to Par amete r Po o l Ye s Writ e com m and to Co m m and reg ist er No Issu e Co m m and Ho st cou ld in sert an o p ti ona l d ela y here Host co u ld in sert an o p ti ona l d ela y here Wa it f or a resp on se? Re ad Co mma n d reg ist er Doo rbel l bi t clear ? Ye s No Co m m and h a s response parameters ? Ye s Re ad resp on se par amete rs from Par amete r Po o l Ye s At th is p oin t Co m m and Re g ist er con ta in s resp on se cod e Do n e No No No

MT9V126_DS Rev. J Pub. 5/15 EN 40 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Note: The host must not write to the parameters pool, nor issue another command, until the previous command completes. This is true even if the host does not care about the result of the previous command. Therefore, the host must always poll the command register to determine the state of the doorbell bit, and ensure the bit is cleared before issuing a command. For a complete command list and further information consult the Host Command Inter- face Specification. An example of how (using DevWare) a command may be initiated in the form of a “Preset” follows. Set Parallel Mode - Normal (Overlay i656) All DevWare presets supplied by ON Semiconductor poll and test the doorbell bit after issuing the command. Therefore there is no need to check if the doorbell bit is clear before issuing the next command. REG= 0xFC00, 0x1000 // CMD_HANDLER_PARAMS_POOL_0 REG= 0x0040, 0x8801 // issue command // POLL COMMAND_REGISTER::DOORBELL => 0x0 Summary of Host Commands Table 17 on page 40 through Table 23 on page 43 show summaries of the host commands. The commands are divided into the following sections: – System Manager –O v e r l a y – Dewarp (or Lens Distortion Correction) –G P I O H o s t i n t e r f a c e – Flash Manager Host – Patch Loader Interface – TX Manager Following is a summary of the Host Interface commands. The description gives a quick orientation. The “Type” column shows if it is an asynchronous or synchronous command. For a complete list of all commands including parameters, consult the Host Command Interface Specification document. Table 17: System Manager Commands System Manager Host Command Value Type Description Set State 0x8100 Asynchronous Request the system enter a new state Get State 0x8101 Synchronous Get the current state of the system Table 18: Overlay Host Commands Overlay Host Command Value Type Description Enable Overlay 0x8200 Synchronous Enable or disable the overlay subsystem Get Overlay State 0x8201 Synchronous Retrieve the state of the overlay subsystem Set Calibration 0x8202 Synchronous Set the calibration offset Set Bitmap Property 0x8203 Synchronous Set a property of a bitmap Get Bitmap Property 0x8204 Synchronous Get a property of a bitmap

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing MT9V126_DS Rev. J Pub. 5/15 EN 41 ©Semiconductor Components Industries, LLC,2015. Set String Property 0x8205 Synchronous Set a property of a character string Load Buffer 0x8206 Asynchronous Load an overlay buffer with a bitmap (from Flash) Load Status 0x8207 Synchronous Retrieve status of an active load buffer operation Write Buffer 0x8208 Synchronous Write directly to an overlay buffer Read Buffer 0x8209 Synchronous Read directly from an overlay buffer Enable Layer 0x820A Synchronous Enable or disable an overlay layer Get Layer Status 0x820B Synchronous Retrieve the status of an overlay layer Set String 0x820C Synchronous Set the character string Load String 0x820E Asynchronous Load a character string (from Flash) Table 19: Dewarp Commands Dewarp Host Command Value Type Description Enable Dewarp 0x8300 Asynchronous Enabl e or disable the dewarp subsystem Get Dewarp State 0x8301 Synchronous Retrieve the current state of the dewarp subsystem Load Config 0x8302 Asynchronous Load a pair of dewarp configuration sets from SPI Flash into local cache (and apply) Config Status 0x8303 Synchronous Retrieve th e status of a Load Config request Write Config 0x8304 Synchronous Write a dewarp config uration set under Host control into local cache Apply Config 0x8305 Asynchronous Apply a dewarp configuration set stored in local cache Read Config 0x8306 Synchronous Read a dewarp configuration set under Host control. Table 20: GPIO Host Commands GPIO Host Command Value Type Description Set GPIO Property 0x8400 Synchronous Set a property of one or more GPIO pins Get GPIO Property 0x8401 Synchronous Retrieve a property of a GPIO pin Set GPO State 0x8402 Synchronous Set the state of a GPO pin or pins Get GPIO State 0x8403 Synchronous Ge t the state of a GPI pin or pins Set GPI Association 0x8404 Synchronous Associate a GPI pin state with a Command Sequence stored in SPI Flash Table 21: Flash Manager Host Commands Flash Manager Host Command Value Type Description Get Lock 0x8500 Asynchronous Request the Flash Manager access lock Lock Status 0x8501 Synchronous Retrieve th e status of the access lock request Release Lock 0x8502 Synchronous Release the Flash Manager access lock Config 0x8503 Synchronous Configure the Flash Manager and underlying SPI Flash subsystem Read 0x8504 Asynchronous Read data from the SPI Flash Write 0x8505 Asynchronous Write data to the SPI Flash Erase Block 0x8506 Asynchronous Erase a block of data from the SPI Flash Erase Device 0x8507 Asynchrono us Erase the SPI Flash device Table 18: Overlay Host Commands Overlay Host Command Value Type Description

MT9V126_DS Rev. J Pub. 5/15 EN 42 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing Query Device 0x8508 Asynchronous Query device-specific information Status 0x8509 Synchronous Obtain status of current asynchronous operation Table 22: Sequencer Host Commands Sequencer Host Command Value Type Description Set Encoding Mode 0x8603 Synchronous Set the encoding mode Enable Horizontal Flip 0x8604 Synchronous Enable or disable horizontal flip Set Flicker Frequency 0x8605 Synchronous Set the flicker frequency Refresh Mode 0x8606 Synchronous Refr esh the Sequencer mode/context Table 21: Flash Manager Host Commands Flash Manager Host Command Value Type Description

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor External Signal Processing MT9V126_DS Rev. J Pub. 5/15 EN 43 ©Semiconductor Components Industries, LLC,2015. Table 23: TX Manager Host Commands TX Manager Host Command Value Type Description Config DAC 0x8800 Synchronous Configure the Video DAC Set Parallel Mode 0x8801 Synchronous Configure the Parallel output port

MT9V126_DS Rev. J Pub. 5/15 EN 44 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Slave Two-Wire Serial Interface Slave Two-Wire Serial Interface The two-wire serial interface bus enables read/write access to control and status regis- ters within the MT9V126. This interface is designed to be compatible with the MIPI Alli- ance Standard for Camera Serial Interface 2 (CSI-2) 1.0, which uses the electrical characteristics and transfer protocols of the two-wire serial interface specification. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a pull-up resistor in the range of 1.5 to 4.7k resistor. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low- level protocol elements, as follows:  a start or restart condition  a slave address/data direction byte  a 16-bit register address  an acknowledge or a no-acknowledge bit d a t a b y t e s  a stop condition The bus is idle when both SCLK and S DATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can gen- erate the start and stop conditions. The SADDR pin is used to select between two different addresses in case of conflict with another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave address is 0xBA. See Table 24 below. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is low and must be stable while SCLK is HIGH. Table 24: Two-Wire Interface ID Address Switching SADDR Two-Wire Interface Address ID 00 x 9 0 10 x B A

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Slave Two-Wire Serial Interface MT9V126_DS Rev. J Pub. 5/15 EN 45 ©Semiconductor Components Industries, LLC,2015. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default slave addresses used by the MT9V126 are 0x90 (write address) and 0x91 (read address). Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can be selected by asserting the SADDR input signal. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. The protocol used is outside the scope of the two-wire serial interface specification. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases S DATA. The receiver indicates an acknowl- edge bit by driving SDATA LOW . As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA low during the SCLK clock period following a data transfer. A no-acknowledge bit is used to termi- nate a read sequence. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.

MT9V126_DS Rev. J Pub. 5/15 EN 48 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Slave Two-Wire Serial Interface Sequential WRITE, Start at Random Location This sequence (Figure 29) starts in the same way as the single WRITE to random location (Figure 28). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until “L” bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 29: Sequential WRITE, Start at Random Location Slave Address 0S A Reg Address[15:8] Write Da ta A Reg Addr ess[7 :0] A Write Data Previous Re g Addre ss, N Reg Address, M M+1 M+2 M+1 M+3 A AA Write Data Write Data M+L -2 M+L -1 M+L A A P Write Da ta (15:8 ) Write Da ta (7:0) Write Da ta (15:8 ) A Write Da ta (7:0)A AA A Write Da ta A Write Da ta (15:8) A Write Da ta (7:0) A Write Da taWrite Da ta (15:8) A Write Da ta (7:0)

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Integrated Lens Distortion Correction MT9V126_DS Rev. J Pub. 5/15 EN 49 ©Semiconductor Components Industries, LLC,2015. Integrated Lens Distortion Correction Integrated lens distortion correction eliminates the need for an expensive DSP for image correction. Using software tools, a flexible algorithm can be calibrated for many wide-angle lenses. Lens Distortion Definition Automotive backup cameras typically feature a wide FOV lens so that a single camera- mounted above the center of the rear bumper can present the driver with a view of all potential obstacles immediately behind the full width of the vehicle. Lenses with a wide field of view typically exhibit at least a noticeable amount of barrel distortion. Barrel distortion is caused by a reduction in object magnification the further away from the optical axis. A barrel distortion percentage can be measured as the amount a refer- ence line is bent as a percentage of the image height. For example, the lens used to capture the image below demonstrates a barrel distortion of approximately 21 percent. The distortion of this lens is near the maximum amount of distortion that must be corrected by the MT9V126. Figure 30: Barrel Distortion Definition For the image to appear natural to the driver, the MT9V126 corrects this barrel distortion and reprocesses the image so that the resulting distortion is less than one percent. Table 25: Lens Correction Features Description Value References/Comments HFOV 60° to180° HFOV (horizontal field of view) Aperture range f#2.0 to f#4.0 Aperture range Maximum lens distortion 25% Maximum lens distortion as percentage of FOV Maximum distortion after correction 1% Maximum distortion after correction Input resolution 640 x 480 Progressive scan Output resolution 720 x 240 NTSC mode 720 x 288 PAL mode Horizontal ±10% Vertical +10% to –25% Distortion = 100 rows Image Height = 480 rows Barrel Distortion of 21% (100/480)

MT9V126_DS Rev. J Pub. 5/15 EN 50 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Integrated Lens Distortion Correction Lens Distortion Correction Distortion correction is the ability to digitally correct the lens barrel distortion and to provide a natural view of objects. In addition, with barrel distortion one can adjust the perspective view to enhance the visibility by virtually elevating the point of viewing objects. Notes: 1. This image shows the original image with the ta rgeted field of view (FOV), which is programmable, after correction. 2. The image is corrected. 3. The image is cropped to its largest usable rectangle. 4. The image is finally cropped and sc aled up to NTSC output format. 3 4 3 4

MT9V126_DS Rev. J Pub. 5/15 EN 52 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Integrated Lens Distortion Correction Figure 32: Conversion Sequence Notes: 1. A distorted NTSC output image may be taken by the MT9V126. 2. Distortion-corrected image created with ON Semiconductor’s lens distortion emulator program. 3. Perspective view adjustment also using ON Semiconductor’s lens distortion emulator program.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Overlay Adjustment MT9V126_DS Rev. J Pub. 5/15 EN 55 ©Semiconductor Components Industries, LLC,2015. Overlay Adjustment To ensure a correct position of the overlay to compensate for assembly deviation, the overlay can be adjusted with assistance from the overlay statistics engine:  The overlay statistics engine supports a windowed 8-bin luma histogram, either row- wise (vertical) or column-wise (horizontal).  The example calibration statistics firmware patch can be used to perform an auto- matic successive-approximation search of a cross-hair target within the scene.  On the first frame, the firmware performs a coarse horizontal search, followed by a coarse vertical search in the second frame.  In subsequent frames, the firmware reduces th e region-of-interest of the search to the histogram bins containing the greatest accumulator values, thereby refining the search.  The resultant X, Y location of the cross-hair target can be used to assign a calibration value of offset selected overlay graphic image positions within the output image.  The calibration statistics patch also suppo rts a manual mode, which allows the host to access the raw accumulator values directly. Note: For the overlay calibration feature to work, load the appropriate patch. See Statistics Engine document.

MT9V126_DS Rev. J Pub. 5/15 EN 56 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Overlay Adjustment Figure 35: Overlay Calibration The position of the target will be used to determine the calibration value that shifts the X,Y position of adjustable overlay graphics. Unlike the lens distortion correction and perspective correction, the overlay calibration is intended to be applied on a device by device basis “in system,” which means after the camera has been installed. ON Semiconductor provides basic programming scripts that may reside in the SPI Flash memory to assist in this effort.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Overlay Character Generator MT9V126_DS Rev. J Pub. 5/15 EN 57 ©Semiconductor Components Industries, LLC,2015. Overlay Character Generator In addition to the four overlay layers, a fifth layer exists for a character generator overlay string. There are a total of:  16 alphanumeric characters available  22 characters maximum per line  16 x 32 pixels with 1-bit color depth Any update to the character generator string requires the string to be passed in its entirety with the Host Command. Character strings have their own control properties aside from the Overlay bitmap properties. Figure 36: Internal Block Diagram Overlay Overlay Layer0 Layer1 Layer2 Layer3 BT656 Number Generator BT656 Timing control User Registers Data Bus DMA/CPU Register Bus ROM

MT9V126_DS Rev. J Pub. 5/15 EN 58 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Overlay Character Generator Character Generator The character generator can be seen as the fifth top layer, but instead of getting the source from RLE data in the memory buffers, it has a predefined 16 characters stored in ROM. All the characters are 1-bit depth color and are sharing the same YCbCr look up table. Figure 37: Example of Character Descriptor 0 Stored in ROM It can show a row of up to 22 characters of 16 x 32 pixels resolution (32 x 32 pixels when blended with the BT 656 data). R O M 1 51 41 31 21 11 0 9 8 7 6 5 4 3 2 1 0 0x00 0000000000000000 0x02 0000000000000000 0x04 0000001111000000 0x06 0000011111100000 0x08 0000111111110000 0x0a 0001111001111000 0x0c 0001110000111100 0x0e 0011110000011100 0x10 0011100000011100 0x12 0011100000011110 0x14 0111100000001110 0x16 0111000000001110 0x18 0111000000001110 0x1a 0111000000001110 0x1c 0111000000001110 0x1e 0111000000001110 0x20 0111000000001110 0x22 0111000000001110 0x24 0111000000001110 0x26 0111000000001110 0x28 0011100000001110 0x2a 0011100000011110 0x2c 0011100000011100 0x2e 0011110000011100 0x30 0001110000111000 0x32 0001111001111000 0x34 0000111111110000 0x36 0000011111100000 0x38 0000001111000000 0x3a 0000000000000000 0x3c 0000000000000000 0x3e 0000000000000000

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing MT9V126_DS Rev. J Pub. 5/15 EN 63 ©Semiconductor Components Industries, LLC,2015. Figure 43: Typical CCIR656 Vertical Bl anking Intervals for 625/50 Video System Table 29: Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System Line Number F V H (EAV) H (SAV) 1 – 2 2 0110 2 3 – 3 1 0 0010 3 1 1 – 3 1 2 0110 3 1 3 – 3 3 5 1110 3 3 6 – 6 2 3 1010 6 2 4 – 6 2 5 1110 Blanking Field 1 Active Vi deo Blanking Field 2 Active Vi deo Field 1 (F = 0) Odd Field 2 (F = 1) Even H = 1 EAV H = 0 SAV Blanking Line 1 (V = 1) Line 2 3 (V = 0) Line 311 (V = 1) Line 336 (V = 0) Line 625 (V = 1) Line 62 4 (V = 1)

MT9V126_DS Rev. J Pub. 5/15 EN 64 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing Parallel Input (DIN) The data-in port allows external CCIR656 data to be multiplexed into the NTSC or PAL output data. Figure 44 shows the timing of the data-in (DIN[7:0]) signals. Table 30 describes timing values for the parallel input waveform. Both mode 0 and mode 1 wave- forms are supported. Figure 44: Parallel Input Data Timing Waveform Using D IN_CLK Note: Setup and hold times are measured with respect to the rising or falling edge of DIN_CLK, which can be programmed by R0x0016[13]. Table 30: Parallel Input Data Timing Values Using D IN_CLK Name Conditions Min Typical Max Parameter tDIN_CLK Max ± 100 ppm – 37 – D IN_CLK Period ts 8 – 18.5 D IN Setup Time th 8 – 18.5 D IN Hold Time tDIN _CLK ts th D0 D 1 D2 D3 D4 D5DIN[7:0] MODE 0 tDIN _CLK ts th D0 D 1 D2 D3 D4 D5 DIN _ CLK MODE 1 DIN _ CLK DIN[7:0]

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing MT9V126_DS Rev. J Pub. 5/15 EN 65 ©Semiconductor Components Industries, LLC,2015. Reset and Clocks Reset Power-up reset is asserted or de-asserted with the RESET_BAR pin, which is active LOW . In the reset state, all control registers are set to default values. See “Device Configura- tion” on page 34 for more details on Auto, Host, and Flash configurations. Soft reset is asserted or de-asserted by the two-wire serial interface program. In soft- reset mode, the two-wire serial interface and the register bus are still running. All control registers are reset using default values. Clocks The MT9V126 has three primary clocks:  A master clock coming from the EXTCLK signal.  In default mode, a pixel clock (PIXCLK) ru nning at 2 * EXTCLK. In raw Bayer bypass mode, PIXCLK runs at the same frequency as EXTCLK. IN_CLK that is associated with the parallel DIN port. When the MT9V126 operates in sensor stand-alone mode, the image flow pipeline clocks can be shut off to conserve power. The sensor core is a master in the system. The sensor core frame rate defines the overall image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced by the sensor configuration, and are also a function of certain image flow pipeline func- tions. The relationship of the primary clocks is depicted in Figure 45. The image flow pipeline typically generates up to 16 bits per pixel—for example, YCbCr or 565RGB—but has only an 8-bit port through which to communicate this pixel data. To generate NTSC or PAL format images, the sensor core requires a 27 MHz clock. Figure 45: Primary Clock Relationships 10 bits/pixel 1 pixel/clock 16 bits/pixel 1 pixel/clock 16 bits/pixel (TYP) 0.5 pixel/clock Colorpipe Output Interface Sensor Pixel Clock Sensor Master Clock EXTCLK Sensor Core DIN_CLK

MT9V126_DS Rev. J Pub. 5/15 EN 66 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing Floating Inputs The following MT9V126 pins cannot be floated: D IN_CLK (tie to GND if not used) S DATA–This pin is bidirectional and should not be floated  FRAME_SYNC T R S T _ N Output Data Ordering Note: PIXCLK is 54 MHz wh en EXTCLK is 27 MHz. Note: PIXCLK is 27 MHz wh en EXTCLK is 27 MHz. Table 31: Output Data Ordering in D OUT RGB Mode Mode (Swap Disabled) Byte D7 D6 D5 D4 D3 D2 D1 D0 565RGB F i r s t R 7R 6R 5R 4R 3G 7 G 6 G 5 Second G4 G3 G2 B7 B6 B5 B4 B3 555RGB First 0 R7 R6 R5 R4 R3 G7 G6 Second G5 G4 G3 B7 B6 B5 B4 B3 444xRGB F i r s t R 7R 6R 5R 4G 7 G 6 G 5 G 4 Second B7 B6 B5 B4 0 0 0 0 x444RGB F i r s t 0000 R 7 R 6 R 5 R 4 Second G7 G6 G5 G4 B7 B6 B5 B4 Table 32: Output Data Ordering in Sensor Stand-Alone Mode Mode D7 D6 D5 D4 D3 D2 D1 D0 DOUT_LSB1 DOUT_LSB0 10-bit Output B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing MT9V126_DS Rev. J Pub. 5/15 EN 69 ©Semiconductor Components Industries, LLC,2015. I/O Timing Digital Output By default, the MT9V126 launches pixel data, FV , and LV synchronously with the falling edge of PIXCLK. The expectation is that the user captures data, FV , and LV using the rising edge of PIXCLK. The timing diagram is shown in Figure 49. As an option, the polarity of the PIXCLK can be inverted from the default by program- ming R0x0016[14]. Figure 49: Digital Output I/O Timing Note: PIXCLK can be inverted from the default by programming R0x0016[14]. Table 33: Parallel Digital Output I/O Timing fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate Signal Parameter Conditions Min Typ Max Unit EXTCLK fextclk max ±100 ppm – 27 – MHz textclk_period – 37 – ns Duty cycle 45 50 55 % PIXCLK1 fp i x c l k –2 7– M H z tpixclk_period – 37 – ns Duty cycle 45 50 55 % DATA[7:0] tpixclkf_dout –2 0 2 ns tdout_su 8 – 18.5 ns tdout_ho 8 – 18.5 ns FV/LV tpixclkf_fvlv –2 0 2 ns tfvlv_su 8 – 18.5 ns tfvlv_ho 8 – 18.5 ns EXT CL K PIXCLK D OUT [7 :0] FRAM E _VALID LINE_VALID tpixclkf _dout tpixclkf _fvlv Input Output Output Output tfvlv_su t fvlv_ho t dout_ho tdout_su textclk _period

MT9V126_DS Rev. J Pub. 5/15 EN 70 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing Slew Rate Figure 50: Slew Rate Timing Table 34: Slew Rate for PIXCLK and D OUT fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; V_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V; T = 25°C; CLOAD = 40 pF PIXCLK DOUT[7:0] UnitR0x30 [10:8] Typical Rise Time Typical Fall Time R0x30 [2:0] Typical Rise Time Typical Fall Time 000 6.5 6.3 000 6.5 6.3 ns 001 4.8 4.6 001 4.8 4.6 ns 010 3.9 3.8 010 3.9 3.8 ns 011 3.7 3.7 011 3.7 3.7 ns 100 3.6 3.6 100 3.6 3.6 ns 101 3.5 3.5 101 3.5 3.5 ns 110 3.4 3.4 110 3.4 3.4 ns 111 3.3 3.3 111 3.3 3.3 ns 90% 10% tri se tfa ll PIXCLK D OUT tri se tfa ll 90 % 10 %

MT9V126_DS Rev. J Pub. 5/15 EN 71 ©Semiconductor Components Industries, LLC,2015. Table 35. These signals are sampled once by the on-chip firmware, which yields a long

MT9V126_DS Rev. J Pub. 5/15 EN 72 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing Figure 52: Power Up Sequence Notes: 1. RESET_BAR may not exceed V DD_IO + 0.3V. 2. The 2.8V plane (V AA, VAA_PIX, VDD_PLL, VDD_DAC, VDD_IO) must remain at a higher voltage than the 1.8V core voltage at all times. Notes: 1. Xtal settling time is component-dependent (Xtal, Oscillator, etc) and usually takes about 10mS ~100mS. 2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are required for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is performed by the RC circuit, then the RC time must include the all power rail settle time and Xtal 3. This is required to load necessa ry patches via Flash mode (SPI) or Host mode (two-wire serial inter- face). Loading time varies depending on the number of patches and bus speed. Table 36: Power Up Sequence Definition Symbol Minimum Typical Maximum Unit VDD_PLL to VAA/VAA_PIX t0 0 – – S VAA/VAA_PIX to VDD_IO t1 0 – – S VDD_IO to VDD t2 0 – – S Xtal settle time tx – 30 1 –m S Hard Reset t3 10 2 –– C l o c k c y c l e Internal Initialization t4 50 – – mS Patch Load (SPI or I2C) t5 – 400 3 –m S VDD (1.8) VAA_PIX VAA (2.8) VDD_PLL VDD_DAC (2.8) EXTCLK RESET_BAR VDD_IO (2.8) t3 t4 t5 Hard Reset Internal (NTSC/PAL) Initialization Patch Config SPI or Host Streaming tx

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Modes and Timing MT9V126_DS Rev. J Pub. 5/15 EN 75 ©Semiconductor Components Industries, LLC,2015. Table 39: RESET_BAR Delay Parameters Parameter Name Condition Min Typ Max Unit Power up delay 2.8V to 1.8V 0.1 – – ms RESET_BAR HIGH to SPI_CS_N LOW tRSTH_CSL 18 – – ms RESET_BAR HIGH to SDATA LOW tRSTH_SDATAL 1.8 – – ms RESET_BAR HIGH to FRAME_VALID tRSTH_FVL 235 – – ms RESET_BAR HIGH to first Overlay tRSTH_OVL 235 – – ms RESET_BAR HIGH to AE/AWB settled tRSTH_AEAWB – 400 – ms

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications MT9V126_DS Rev. J Pub. 5/15 EN 76 ©Semiconductor Components Industries, LLC,2015. Electrical Specifications Figure 58: SPI Output Timing Table 40: SPI Data Setup and Hold Timing Parameter Description Min Typ Max Units fSPI_SCLK SPI_SCLK Frequency 1.6875 4.5 18 MHz tsu Setup time – – 110 ns tSCLK_SDO Hold time 110 ns tCS_SCLK Delay from falling edge of SPI_CS_ N to rising edge of SPI_SCLK – 230 – ns t su SPI_CS_N SPI_SCLK SPI_SDI SPI_SDO tCS_SCLK tSCLK_SDO

MT9V126_DS Rev. J Pub. 5/15 EN 77 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Caution Stresses greater than those listed in Table 41 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabil- ity. Notes: 1. V AA and VAA_PIX must all be at the same potential to avoid excessive current draw. Care must be taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together. 2. The imager operates in this temperature rang e, but image quality may degrade if it operates beyond the functional operating temperature range. 3. Image quality is not guaranteed at temperat ures equal to or greater than this range. Table 41: Absolute Maximum Ratings Symbol Parameter Rating UnitMin Max VDD Digital power (1.8V) -0.3 2.4 V VDD_IO I/O power (2.8v) -0.3 4 V VAA VAA Analog power (2.8V) -0.3 4 V VAA_PIX Pixel array power (2.8v) -0.3 4 V VDD_PLL PLL power (2.8V) -0.3 4 V VDD_DAC DAC power (2.8V) -0.3 4 V VIN DC Input Voltage -0.3 V DD_IO+0.3 V VOUT DC Output Voltage -0.3 V DD_IO+0.3 V TSTG Storage temperature -50 150 °C Table 42: Electrical Characteristics and Operating Conditions Parameter1 Condition Min Typ Max Unit Core digital voltage (VDD) – 1.7 1.8 1.9 V IO digital voltage (VDD_IO) – 2.66 2.8 2.94 V Video DAC voltage (VDD_DAC) – 2.66 2.8 2.94 V PLL Voltage (VDD_PLL) – 2.66 2.8 2.94 V Analog voltage (VAA) – 2.66 2.8 2.94 V Pixel supply voltage (VAA_PIX) – 2.66 2.8 2.94 V Leakage current EXTCLK: HIGH or LOW 10 A Imager operating temperature2 – –40 +105 °C Functional operating temperature3 –40 +85 °C Storage temperature – –50 +150 °C

MT9V126_DS Rev. J Pub. 5/15 EN 78 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Table 43: Video DAC Electrical Characteristics–Single-Ended Mode fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V Parameter Condition Min Typ Max Unit Resolution – 10 - bits DNL – 0.2 0.4 bits INL – 0.7 3.5 bits Output local load Output pad (DAC_POS) – 75 -  Unused output (DAC_NEG) – 0 -  Output voltage Single-ended mode, code 000h – .02 - V Single-ended mode, code 3FFh – 1.30 - V Output current Single-ended mode, code 000h – 0.26 - mA Single-ended mode, code 3FFh – 17.33 - mA Supply current Estimate – - 25.0 mA DAC_REF DAC Reference – 1.15 +/-0.2 - V R DAC_REF DAC Reference – 4.7 - K  Table 44: Video DAC Electrical Characteristics–Differential Mode fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V Parameter Condition Min Typ Max Unit DNL – 0.2 0.25 Bits INL – 0.8 2.5 Bits Output local load Differential mode per pad (DAC_POS and DAC_NEG) – 37.5 –  Output voltage Differential mode, code 000h, pad dacp – .02 – V Differential mode, code 000h, pad dacn – 1.30 – V Differential mode, code 3FFh, pad dacp – 1.30 – V Differential mode, code 3FFH, pad dacn – .02 – V Output current Differential mode, code 000h, pad dacp – .53 – mA Differential mode, code 000h, pad dacn – 34.7 – mA Differential mode, code 3FFh, pad dacp – 34.7 – mA Differential mode, code 3FFH, pad dacn – .53 – mA Differential output, midlevel –0 . 6 5 – V Supply current Estimate – – 50 mA DAC_REF DAC Reference – 1.15 +/-0.2 V R DAC_REF DAC Reference 2.35 K 

MT9V126_DS Rev. J Pub. 5/15 EN 79 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Notes: 1. All inputs are protected and may be active when All supplies (2.8V and 1.8V) are turned off. Table 45: Digital I/O Parameters TA = Ambient = 25°C; All supplies at 2.8V Signal Parameter Definitions Condition Min Typ Max Unit All Outputs Load capacitance 1 – 30 pF Output signal slew 2.8V, 30pF load – – – V/ns 2.8V, 5pF load – – – V/ns VOH Output high voltage – V DD_IO – V VOL Output low voltage –0.3 – – V IOH Output high current VDD = 2.8V, VOH = 2.4V –– 8 m A IOL Output low current VDD = 2.8V, VOL = 0.4V –– 8 m A All Inputs VIH Input high voltage V DD = 2.8V 0.7 * V DD_IO – V DD_IO + 0.3 V VIL Input low voltage V DD = 2.8V –0.3 – 0.3 * V DD_IO V IIN Input leakage current –2 – 2 A Signal CAP Input signal capacitance –3 . 5 – p F

MT9V126_DS Rev. J Pub. 5/15 EN 80 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Power Consumption, Operating Mode Analog output uses single-ended mode: DAC_Pos = 75, DAC_Neg = open, parallel output is disabled. Analog output uses single-ended mode: DAC_Pos = 75, DAC_Neg = open, parallel output is enabled. Table 46: Power Consumption – Condition 1 fEXTCLK = 27 MHz; VDD = 1.8V; VDD _IO = 2.8V; VAA =2.8V;VAA_PIX=2.8V; VDD _PLL = 2.8V; VDD _DAC = 2.8V Power Plane Supply Condition 1 Typ Power Max Power Unit VDD 1.8 140.4 162 mW VDD_IO 2.8 Parallel off 4.2 8.4 mW VAA 2.8 89.6 112 mW VAA_PIX 2.8 1.96 5.04 mW VDD_DAC 2.8 Single 75(1) 39.2 44.8 mW VDD_PLL 2.8 13.44 16.8 mW Total 288.8 349.04 mW Table 47: Power Consumption – Condition 2 fEXTCLK = 27 MHz; VDD = 1.8V; VDD _IO = 2.8V; VAA =2.8V;VAA_PIX=2.8V; VDD _PLL = 2.8V; VDD _DAC = 2.8V Power Plane Supply Condition 2 Typ Power Max Power Unit VDD 1.8 140.4 162 mW VDD_IO 2.8 Parallel on 42 50.4 mW VAA 2.8 89.6 112 mW VAA_PIX 2.8 1.96 5.04 mW VDD_DAC 2.8 Single 75(1) 39.2 44.8 mW VDD_PLL 2.8 13.44 16.8 mW Total 326.6 391.04 mW

MT9V126_DS Rev. J Pub. 5/15 EN 81 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications NTSC Signal Parameters Notes: 1. Black and white levels are referenced to the blanking level. 2. NTSC convention standardized by the IRE (1 IRE = 7.14mV). 3. Encoder contrast setting R0x011 = R0x001 = 0. 4. DAC ref = 2.35k , load = 37.5 Table 48: NTSC Signal Parameters fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V Parameter Conditions Min Typ Max Units Notes Line Frequency 15734.25 15734.27 15734.28 Hz Field Frequency 59.94 59.94 59.94 Hz Sync Rise Time 148 148 148 ns Sync Fall Time 148 148 148 ns Sync Width 4.74 4.74 4.74 s Sync Level 38 40 42 IRE 2, 4 Burst Level 38 40 42 IRE 2, 4 Sync to Setup (with pedestal off) 9.44 9.44 9.44 s Sync to Burst Start 5.33 5.33 5.33 s Front Porch 1.33 1.33 1.33 s Black Level 7.5 IRE 1, 2, 4 White Level 100 IRE 1, 2, 3, 4

MT9V126_DS Rev. J Pub. 5/15 EN 82 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Figure 59: Video Timing Table 49: Video Timing Signal NTSC

27 MHz Units

A H Period 1716 1728 Clocks B Hsync to burst 144 153 Clocks C burst 63 66 Clocks D Hsync to Signal 255 279 Clocks E Video Signal 1423 1413 Clocks FF r o n t 3 6 3 9 C l o c k s G Hsync Period 128 128 Clocks H Sync rising/falling edge 4 4 Clocks J Back overscan (BOS) 9 14 Clocks K Front overscan (FOS) 8 13 Clocks H F A H DE B C G J K

MT9V126_DS Rev. J Pub. 5/15 EN 83 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Figure 60: Equivalent Pulse Table 50: Equivalent Pulse Signal NTSC I H/2 Period 858 864 Clocks J Pulse width 64 64 Clocks K Pulse rising/falling edge 4 4 Clocks L Signal to pulse 38 41 Clocks L J I K K

MT9V126_DS Rev. J Pub. 5/15 EN 84 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Figure 61: V Pulse Table 51: V Pulse Signal NTSC M H/2 Period 858 864 Clocks N Pulse width 730 736 Clocks O V pulse interval 128 128 Clocks P Pulse rising/falling edge 4 4 Clocks N M O P P

MT9V126_DS Rev. J Pub. 5/15 EN 86 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Spectral Characteristics 6. A Fast-mode I 2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. Spectral Characteristics Figure 63: Quantum Efficiency 350 450 550 650 750 850 950 1050 1150 Blue Green (B) Green (R) Red Quantum Efficiency (%) Wavelength (nm)

MT9V126_DS Rev. J Pub. 5/15 EN 87 ©Semiconductor Components Industries, LLC,2015 MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Spectral Characteristics Package and Die Dimensions Figure 64: 63-Ball iBGA Package Outline Drawing

MT9V126_DS Rev. J Pub. 5/15 EN 88 ©Semiconductor Components Industries, LLC,2015. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Revision History

 Updated “Ordering Information” on page 3  Converted to ON Semiconductor template  Removed Confidential marking  Updated trademarks  Applied updated Aptina template  Updated Figure 2: “System Block Diagram,” on page 12  Added paragraph after Figure 3: “Using a Crys tal Instead of an External Oscillator,” on page 13  Updated Figure 19: “External Overlay System Block Diagram,” on page 32  Updated Figure 39: “Single-Ended Termination,” on page 60  Updated Table 36, “Power Up Sequence,” on page 72  Updated Table 37, “Power Down Sequence,” on page 73  Updated Table 48, “NTSC Signal Parameters,” on page 81  Updated capacitor value in “Crystal Usage” on page 13  Updated Note 4 in Table 48, “NTSC Signal Parameters,” on page 81  Updated Figure 62: “Two-Wire Serial Bus Timing Parameters,” on page 85  Updated Table 52, “Two-Wire Serial Bus Characteristics,” on page 85  Updated values for Sensitivity, Signal-t o-noise ratio, and Pixel dynamic range in Table 2, “Key Parameters (continued),” on page 2  Updated temperature range for 1MB Flash in Table 14, “SPI Flash Devices,” on page 36  Deleted subheading under “Parallel Output (DOUT)” on page 61 and updated first paragraph under it  Updated to Production status  Updated “Features” on page 1  Updated Table 1, “Key Parameters,” on page 1 and Table 2, “Key Parameters (continued),” on page 2  Updated Table 3, “ Available Part Numbers,” on page 3  Updated “Crystal Usage” on page 13  Updated Table 4, “Pin Descriptions,” on page 14  Updated “Pin Assignments” on page 16  Updated Table 6, “Reset/Default State of Interfaces,” on page 16  Updated “Pixel Array Structure” on page 18  Updated “Sensor Pixel Array” on page 20  Updated “Positional Gain Ad justments (PGA)” on page 25  Deleted 1D from “Color Correction and Aperture Correction” on page 26

ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SC ILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the SCILLC prod uct could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such uninte nded or unauthorized application, Buyer shall indemnify and hol d SCILLC and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor MT9V126_DS Rev. J Pub. 5/15 EN 89 ©Semiconductor Components Industries, LLC,2015 .  Deleted section on “Image Scaling”  Updated “Usage Modes” on page 30  Updated Figure 19: “External Overlay System Block Diagram,” on page 32  Moved register tables and section on “How to Access Registers and Variables” to sepa- rate document  Updated “Command Flow” on page 39  Updated Figure 28: “Single Write to Random Location,” on page 47  Updated “Integrated Lens Distortion Correction” on page 49  Updated Table 23, “TX Manager Host Commands,” on page 43  Updated “Overlay Capability” on page 53  Updated Figure 34: “Memory Partitioning,” on page 54  Updated “Overlay Adjustment” on page 55  Changed “Overlay Number Generator” to “Overlay Character Generator,” on page 57  Updated Table 30, “Parallel Input Data Timing Values Using Din_CLK,” on page 64  Updated Table 33, “Parallel Digital Output I/O Timing,” on page 69  Updated Table 41, “ Absolute Maximum Ratings,” on page 77  Added title to Table 66, “Power-Up Sequence Parameters,” on page 132 and added units for tVDD_RESET and tEXTCLK_RESET  Added typical value for leakage current for EXTCLK at V IN = 0V in Table 72, “Digital I/O Parameters,” on page 138 I n i t i a l r e l e a s e