MT9V115_17 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Superior Low-light Performance
- Ultra-low-power
- VGA Video at 30 fps
- Internal Master Clock Generated by On-chip Phase Locked Loop (PLL) Oscillator
- Electronic Rolling Shutter (ERS), Progressive Scan www.onsemi.com See detailed ordering and shipping information on page 2 of this data sheet.
ORDERING INFORMATION
ODCSP−25 CASE 570BK Features (continued)
- Integrated Image Flow Processor (IFP) for Single-die Camera Module
- One-time Programmable Memory (OTPM)
- Automatic Image Correction and Enhancement, Including Four-Channel Lens Shading Correction
- Arbitrary Image Scaling with Anti-aliasing
- Supports ITU.R.656 Format (Progressive Scan Version)
- Two-wire Serial Interface Providing Access to Registers and Microcontroller Memory
- Selectable Output Data Format: YCbCr, 565RGB, Processed Bayer, RAW8− and RAW8+2-bit, BT656*
- Parallel Data Output
- Programmable I/O Slew Rate
- MIPI Serial Mode Supporting 8-bit and 10-bit Data Streams
- Independently Configurable Gamma Correction
- Direct XDMA Access (Reducing Serial Commands)
- Integrated Hue Rotation
Applications
- Mobile Phones
- PC and Notebook Cameras
- Gaming Systems
www.onsemi.com Table 2. AVAILABLE PART NUMBERS analog-to-digital converter (ADC). inherent size, cost, and integration advantages of CMOS. functional blocks of the MT9V115. Figure 1. MT9V115 Block Diagram
www.onsemi.com Sensor Core The MT9V115 has a color image sensor with a Bayer color filter arrangement and a VGA active-pixel array with electronic rolling shutter (ERS). The sensor core readout is 10 bits. The sensor core also supports separate analog and digital gain for all four color channels (R, Gr, Gb, B). Image Flow Processor (IFP) The advanced IFP features and flexible programmability of the MT9V115 can enhance and optimize the image sensor performance. Built-in optimization algorithms enable the MT9V115 to operate with factory settings as a fully automatic and highly adaptable system-on-a-chip (SOC) for most camera systems. These algorithms include shading correction, defect correction, color interpolation, edge detection, color correction, aperture correction, and image formatting with cropping and scaling. Microcontroller Unit (MCU) The MCU communicates with all functional blocks by way of an internal ON Semiconductor proprietary bus interface. The MCU firmware executes the automatic control algorithms for exposure and white balance. System Control The MT9V115 has a phase-locked loop (PLL) oscillator that can generate the internal sensor clock from the common system clock. The PLL adjusts the incoming clock frequency up, allowing the MT9V115 to run at almost any desired resolution and frame rate within the sensor’s capabilities. Low-power consumption is a very important requirement for all components of wireless devices. The MT9V115 provides power-conserving features, including an internal soft standby mode and a hard standby mode. A two-wire serial interface bus enables read and write access to the MT9V115’s internal registers and variables. The internal registers control the sensor core, the color pipeline flow, the output interface, auto white balance (AWB) and auto exposure (AE). Output Interface The output interface block can select either raw data or processed data. Image data is provided to the host system by an 8-bit parallel port (up to 22MB/sec) or by a serial MIPI port (up tp 176 Mbps with 8-bit and 10-bit support). The parallel output port provides 8-bit YCbCr, YUV , 565 RGB, BT656, processed Bayer data or extended 10-bit Bayer data achieved using 8+2 format.
recommendation is 0.1 μF per supply in the module. internal demo camera design and verified in hardware. provided for their own designs.
- Mount 0.1 μF and 1 μF decoupling capacitors for
and place a 10 μF capacitor nearby off-module.
- If module limitations allow for only six decoupling
each of the three regulated supplies.
- If module limitations allow for only three
the three regulated supplies is preferred.
- If module limitations allow for only three
of the three regulated supplies is preferred.
- Priority should be given to the V
additional decoupling capacitors.
- Inductive filtering components are not
- Follow best practices when performing physical
Table 3. SIGNAL DESCRIPTIONS
Table 4. PAD FUNCTIONALITY BASED ON OUTPUT writing commands through the two-wire serial interface.
- A soft reset is issued by writing commands (SYSCTL R0x001A[0] = 1)through the two-wire serial interface register 0x1A bit[4:6] during normal operation.
- An internal power-on reset The output states after hard reset are shown in Table 5. A soft reset sequence to the sensor has the same effect as the hard reset and can be activated by writing to a register through the two-wire serial interface. On-chip power-onreset circuitry can generate an internal reset signal in case an external reset is not provided. The RESET_BAR signal has an internal pull-up resistor and can be left floating. Standby The MT9V115 supports two different standby modes: 1. Hard standby mode 2. Soft standby mode The hard standby mode is invoked by asserting the STANDBY pin. It then disables all of the digital logic within the image sensor, and only supports being awoken by de-asserting the STANDBY pin. The soft standby mode is enabled by a single register access, which then disables the sensor core and most of the digital logic. However, the serial interface is kept alive, which allows the image sensor to be awoken via a serial register access. All output signal status during standby are shown in Table 5.
Table 5. STATUS OF OUTPUT SIGNALS DURING RESET AND STANDBY when EXTCLK is running during hard standby mode.
- De-assert STANDBY signal (LOW).
- Assert STANDBY signal (HIGH).
- Part is now ready for streaming.
Table 7. SOFT STANDBY SIGNAL TIMING read by the host processor from register 0x001A[15:12]. The module ID is programmed through the OTPM.
variations due to scaling factor (used only in 8-bit YUV). blanking and vertical blanking are programmable. Figure 5. Pixel Data Timing Example: 8+2 Bayer format Figure 6. Frame Timing, FV, and LV Signals
- P: Frame start and end blanking time.
- Q: Horizontal blanking time.
1 A2 Q3
www.onsemi.com Serial Port This section describes how frames of pixel data are represented on the high-speed MIPI serial interface. The MIPI output transmitter implements a serial differential sub-LVDS transmitter capable of up to 176 Mb/s. It supports multiple formats, error checking, and custom short packets. When the sensor is in the hard standby system state or in the soft standby system state, the MIPI signals (CLK_P, CLK_N, DA TA_P, DA TA_N) indicate ultra low power state (ULPS) corresponding to (nominal) 0V levels being driven on CLK_P, CLK_N, DATA_P, and DATA_N. This is equivalent to signaling code LP-00. When the sensor enters the streaming state, the interface goes through the following transitions: 1. After the PLL has locked and the bias generator for the MIPI drivers has stabilized, the MIPI interface transitions from the ULPS state to the ULPS-exit state (signaling code LP–10). 2. After a delay (TWAKEUP), the MIPI interface transitions from the ULPS-exit state to the TX-stop state (signaling code LP–11). 3. After a short period of time (the programmed integration time plus a fixed overhead), frames of pixel data start to be transmitted on the MIPI interface. Each frame of pixel data is transmitted as a number of high-speed packets. The transition from the TXstop state to the high-speed signaling states occurs in accordance with the MIPI specifications. Between high-speed packets and between frames, the MIPI interface idles in the TX-stop state. The transition from the high-speed signaling states and the TX-stop state takes place in accordance with the MIPI specifications. 4. If the sensor is reset, any frame in progress is aborted immediately and the MIPI signals switch to indicate the ULPS. 5. If the sensor is taken out of the streaming system state and SYSCTL R0x0042[0] = 1 (standby end-of-frame), any frame in progress is completed and the MIPI signals switch to indicate the ULPS. If the sensor is taken out of the streaming system state and SYSCTL R0x0042[0] = 0 (standby end-of-line), any frame in progress is aborted as follows: 1. Any long packet in transmission is completed. 2. The end of frame short packet is transmitted. After the frame has been aborted, the MIPI signals switch to indicate the ULPS. Sensor Control The sensor core of the MT9V115 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. Figure 7 shows a block diagram of the sensor core. It includes the VGA active-pixel array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been selected, the data from each column is sequenced through an analog signal chain, including offset correction, gain adjustment, and ADC. The final stage of the sensor core converts the output of the ADC into 10-bit data for each pixel in the array. The pixel array contains optically active and light-shielded (dark) pixels. The dark pixels are used to provide data for the offset-correction algorithms (black level control). The sensor core contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. These registers are controlled by the MCU firmware and are also accessible by the host processor through the two-wire serial interface. The output from the sensor core is a Bayer pattern; alternate rows are a sequence of either red and green pixels or blue and green pixels. The offset and gain stages of the analog signal chain provide per-color control of the pixel data.
image data processing flow within the IFP. Figure 14. Image Flow Processor
Figure 15. Color Bar Test Pattern
individual R, Gb, Gr, and B color signal. defined through variable settings. edge threshold can be set through variable settings. variables can be adjusted through variable settings. correction can be defined through variable settings. uploaded tables or an interpolated version of the two tables. Figure 16. Gamma Correction Curve
Figure 19. +22/C0053 Hue can be scaled in size to cover any portion of the image. integration time based on scene brightness. correction matrix, digital, and sensor core analog gains. matrices and place limits on color channel gains. for these surfaces hence the word “balance”. ms for 60 Hz environment), flicker cannot be avoided. digital images’ exposure times. mechanism that greatly improves sensor data readout times. have alternating light and dark horizontal bands.
120 Hz, twice the frequency of the power line. time to an integer multiple of the light’s flicker period. used to calibrate the flicker detect settings. defined and often misused in various operating systems. There is an option where 128 is not added to U’V’. YUV spanning a range of 0 through 255. Table 8. YCbCr OUTPUT DATA ORDERING swapped when chroma swap is enabled. Table 9. RGB ORDERING IN DEFAULT MODE
Table 10. 2-BYTE BAYER FORMAT Table 11. DATA FORMATS SUPPORTED BY MIPI INTERFACE
- Data will be packed as RAW8 if the data type specified does not match any of the above data types.
data and not interlaced (R0x3C00[5] = 1). Figure 20. BT656 Image Data with Odd SAV/EAV Codes in a maximum 648 x 484 output.
Register and Variable Reference. are performed when the sequencer is in the stopped state. the host complete manual control. Table 12. SUMMARY OF MT9V115 VARIABLES access to control and status registers within the MT9V115.
- a (repeated) start condition
- a slave address/data direction byte
- a 16-bit register address (8-bit addresses are not
- an (a no) acknowledge bit
- a 16-bit data transfer (8-bit data transfers are
generate the start and stop conditions. on SDATA while SCLK is HIGH. this is known as a repeated start or restart condition. followed by an acknowledge bit or a no-acknowledge bit. slave address default is 0x7A. LOW and must be stable while SCLK is HIGH.
Figure 27. Dual Camera
- Power up Camera A (0x7A) and B (0x7A). with
- Take camera B out of HARD STANDBY
- Change the address of Camera B (0x78) by writing
- Put Camera B back to HARD STANDBY
- Take Camera A out of HARD STANDBY .
programmed when the VPP voltage is applied. Figure 28. Chief Ray Angle (CRA) vs. Image Height
Figure 29. Quantum Efficiency Table 13. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated i n the product
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 14. OPERATING CONDITIONS Table 15. DC ELECTRICAL CHARACTERISTICS Table 16. OPERATING/STANDBY CURRENT CONSUMPTION
Table 16. OPERATING/STANDBY CURRENT CONSUMPTION (continued)
- This does not include V DD_IO current.
Table 17. AC ELECTRICAL CHARACTERISTICS
Table 17. AC ELECTRICAL CHARACTERISTICS (continued)
- PIXCLK output signal can be inverted internally by programming register.
- It is only necessary to meet this spec when the PLL is bypassed. If the PLL is being using then VIH/VIL should be met.
Figure 30. Parallel Pixel Bus Timing Diagram
- FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
- FRAME_VALID trails LINE_VALID by 6 PIXCLKs.
- Propagation delay is measured from 50% of rising and falling edges.
Table 18. MIPI TIMING MEASUREMENTS: CLOCK
Figure 31. MIPI Clock Timing Table 19. MIPI TIMING MEASUREMENTS: DATA Table 20. MIPI HIGH SPEED (HS)
Table 20. MIPI HIGH SPEED (HS) (continued) Table 21. MIPI LOW POWER (LP) Figure 32. MIPI Data Timing
Table 22. TWO-WIRE SERIAL INTERFACE TIMING DATA Figure 33. Two-Wire Serial Bus Timing Parameters
for detailed timing requirement. Figure 34. Power-Up Sequence Table 23. POWER-UP SIGNAL TIMING
Figure 35. Power-Down Sequence Table 24. POWER-UP SUPPLY RALL TIMING
- t3 is required between power down and next power up time, all decoupling caps from regulators must completely discharged befo re next
Table 25. PACKAGE DIMENSION
www.onsemi.com PACKAGE DIMENSIONS ODCSP25 2.694x2.694 CASE 570BK ISSUE B ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries i n the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . A listing of ON Semiconductor’s product/patent ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the right s of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 MT9V115/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative