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MT9V111_DS Rev. N 5/15 EN 1 ©Semiconductor Components Industries, LLC 2015, 1/4-Inch SOC VGA CMOS Active-Pixel Digital Image Sensor MT9V111 Datasheet, Rev. N For the latest data sheet revision, please visit www.onsemi.com
- System-On-a-Chip (SOC)—Completely integrated camera system Ultra low-power, low cost CMOS image sensor Superior low-light performance Up to 30 fps progressive scan at 27 MHz for high- quality video at VGA resolution On-chip Image Flow Pr ocessor (IFP) performs sophisticated processing: color recovery and correction, sharpening, gamma, lens shading correction, on-the-fly defect correction, 2X fixed zoom Image decimation to arbi trary size with smooth, continuous zoom and pan Automatic exposure, white balance and black compensation, flicker avoidance, color saturation, and defect identification and correction, auto frame rate, back light compensation Xenon and LED-type flash support Two-wire serial programming interface ITU_R BT.656 (YCbCr), YUV , 565RGB, 555RGB, and 444RGB output data formats
Applications
Cellular phones P D A s P C C a m e r a Toys and other battery-powered products General Description The ON SemiconductorMT9V111 is a 1/4-inch VGA-for- mat CMOS active-pixel digital image sensor, the result of combining the MT9V011 image sensor core with ON Semiconductor's third-generation digital image flow processor technology. The MT9V111 has an active imag- ing pixel array of 649 x 489, capturing high-quality color images at VGA resolution. The sensor is a complete camera-on-a-chip solution and is designed specifically to meet the demands of battery-powered products such as cellular phones, PDAs, and toys. It incorporates sophisticated camera functions on-chip and is pro- grammable through a simple two-wire serial interface. Table 1: Key Performance Parameters Parameter Value Optical Format 1/4-inch (4:3) Active Imager Size 3.58mm(H) x 2.69mm(V) 4.48mm (Diagonal) Active Pixels 640H x 480V (VGA) Pixel Size 5.6 um x 5.6 um Color Filter Array RGB Bayer Pattern Shutter Type Electronic Rolling Shutter (ERS) Maximum Data Rate/ Master Clock 12 13.5 MPS/2427 MHz Frame Rate VGA (640 x 480) 15 fps at 12 MHz (default), programmable up to 30 fps at 27 MHz CIF (352 x 288) Programmable up to 60 fps QVGA (320 x 240) Programmable up to 90 fps ADC Resolution 10-bit, on-chip Responsivity 1.9 V/lux-sec (550nm) Dynamic Range 60 dB SNR MAX 45 dB Supply Voltage 2.8V + 0.25V Power Consumption <80 mW at 2.8 V, 15 fps at 12 MHz Operating Temperature -20°C to +60°C Packaging 44-Ball ICSP , wafer or die
MT9V111_DS Rev. N 5/15 EN 2 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Ordering Information
Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description MT9V111D00ATCK82AC1-305 VGA 1/4" SOC Die Sales, 305 m Thickness MT9V111D00STCK82AC1K-305 VGA 1/11" SOC Die Sales, 305 m Thickness MT9V111IA7ATC-DP VGA 1/13" SOC Dry Pack with Protective Film MT9V111IA7ATC-DR VGA 1/4" SOC Dry Pack without Protective Film MT9V111IA7ATC-TP VGA 1/4" CIS SOC Tape & Reel with Protective Film MT9V111IA7ATC-TR VGA 1/4" SOC Tape & Reel without Protective Film
MT9V111_DS Rev. N 5/15 EN 3 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Table of Contents Table of Contents Two-wire Serial Interface Sample Write and Read Sequences
MT9V111_DS Rev. N 5/15 EN 5 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor List of Tables List of Tables
MT9V111_DS Rev. N 5/15 EN 8 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Ball Assignment Ball Assignment Figure 4: 44-Ball ICSP Package Table 2: Ball Description Ball Numbers Name Type Description G2 CLKIN Input Master Clock into sensor. Default is 12 MHz (27 MHz maximum). F3 SCLK Input Serial Clock. F4 S ADDR Input Serial Interface address select: Reg0xB8 when HIGH (default). Reg0x90 when LOW. F6 ADC_TEST Input Tie to VAAPIX (factory use only). E6 RESET# Input Asynchronous reset of sensor when LOW. All registers assume factory defaults. E7 STANDBY Input When HIGH puts the imag er in ultra-low power standby mode. D6 OE# Input Output_Enable_Bar pin. When HIGH tri-state all outputs except SDATA (tie LOW for normal operation). C6 SCAN_EN Input Tie to Digital ground. G3 S DATA I/O Serial data I/O. E2 FLASH Output Flash Strobe. E1 PIXCLK Output Pixel Clock Out. Pixel data output are valid during rising edge of this clock. IFP Reg0x08 [9] inverts polarity. Frequency = Master Clock. E3 LINE_VALID Output Active HIGH during line of selectable valid pixel data. F1 FRAME_VALID Output Active HIGH during frame of valid pixel data. B5 D OUT7 Output ITU_R BT.656/RGB data bit 7 (MSB). A B C D E F G DOUT2 VDD DOUT0 NC FLASH VDD CLKIN DOUT4 DOUT3 DOUT5 LINE_ SCLK SDATA DGND DOUT1 NC DGND PIXCLK FRAME_ VALID DGND DGND VDD SADDR DGND VDD VDD SCAN OE# RESET# ADC_ VAA DGND VDD DGND DGND STAND VAAPIX AGND DOUT6 DOUT7 VDD VDD AGND VAA Top View (Ball Down) BYVALID _EN TEST
MT9V111_DS Rev. N 5/15 EN 9 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Ball Assignment A5 D OUT6 Output ITU_R BT.656/RGB data bit 6. C3 D OUT5 Output ITU_R BT.656/RGB data bit 5. A3 D OUT4 Output ITU_R BT.656/RGB data bit 4. B3 D OUT3 Output ITU_R BT.656/RGB data bit 3. A2 D OUT2 Output ITU_R BT.656/RGB data bit 2. B1 D OUT1 Output ITU_R BT.656/RGB data bit 1. C2 D OUT0 Output ITU_R BT.656/RGB data bit 0 (LSB). A6,B2,B4,B6 B7,C5,E5,F2 VDD Supply Digital Power (2.8V). G5,G6 V AA Supply Analog Power (2.8V). F7 VAAPIX Supply Pixel Array Power (2.8V). F5,G7 A GND Supply Analog Ground. A1,D1,A4,A 7,C7,D7,G1, DGND Supply Digital Ground. C1,D2 NC No connect. Table 2: Ball Description (continued) Ball Numbers Name Type Description
MT9V111_DS Rev. N 5/15 EN 10 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Image Flow Processor Image Flow Processor Overview of Architecture The image flow processor consists of a color processing pipeline and a measurement and control logic block as shown in Figure 5. The stream of raw data from the sensor enters the pipeline and undergoes a number of transformations. Image stream processing starts from conditioning the black level and applying a digital gain. The lens shading block compensates for signal loss caused by the lens. Next, the data is interpo- lated to recover missing color components for each pixel and defective pixels are corrected. The resulting interpolated RGB data passes through the current color correc- tion matrix (CCM), gamma, and saturation corrections and is formatted for final output. The measurement and control logic continuously accumulates statistics about image brightness and color. Indoor 50/60 Hz flicker is detected and automatically updated when possible. Based on these measurements the IFP calculates updated values for exposure time and sensor analog gains, which are sent to the sensor core via the communication bus. Color correction is achieved through linear transformation of the image with a 3 x 3 color correction matrix. Color saturation can be adjusted in the range from zero (black and white) to 1.25 (125% of full color saturation). Gamma correction compensates for non-linear dependence of the display device output Output and Formatting Processed video can be output in the form of a standard ITU_R BT.656 or RGB stream. ITU_R BT .656 (default) stream contains 4:2:2 data with optional embedded synchroniza- tion codes. This kind of output is typically suitable for subsequent display by standard video equipment. For JPEG/MPEG compression, YUV/ encoding is suitable. RGB func- tionality is provided to support LCD devices. The MT9V111 can be configured to output 16-bit RGB (RGB565), 15-bit RGB (RGB555) as well as two types of 12-bit RGB (RGB444). The user can configure internal registers to swap odd and even bytes, chrominance channels and luminance and chrominance components to facilitate interface to appli- cation processors.
MT9V111_DS Rev. N 5/15 EN 11 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Image Flow Processor Figure 5: Image Flow Processor Block Diagram The MT9V111 features smooth, continuous zoom and pan. This functionality is avail- able when the IFP output is downsized in the decimation block. The decimation block can downsize the original VGA image to any integer size, including QVGA, QQVGA, CIF and QCIF with no loss to the field of view. The user can program the desired size of the output image in terms of horizontal and vertical pixel count. In addition the user can program the size of a region for downsizing. Continuous zoom is achieved every time the region of interest is less than the entire VGA image. The maximum zoom factor is equal to the ratio of VGA to the size of the region of interest. For example, an image rendered on a 160x120 display can be zoomed by 640/160=480/120=4 times. Continuous pan is achieved by adjusting the starting coordinates of the region of interest. Also a fixed 2X up-zoom is implemented by means of windowing down the sensor core. In this mode the IFP receives a QVGA-sized input data and outputs a VGA-size image. The sub-window can be panned both vertically and horizontally by programming sensor core registers. The MT9V111 supports both LED and Xenon-type flash light sources using a dedicated output pad. For Xenon devices the pad generates a strobe to fire when the imager's shutter is fully open. For LED the pad can be asserted or de-asserted asynchronously. Flash modes are configured and engaged over the two-wire serial interface using IFP Reg0x98. IMAGE SENSOR GAMMA CORRECTION COLOR CORRECTION DEMOSAICING OUTPUT FORMATTING FLASH CONTROL AE, AWB, FLICKER AVOIDANCE LENS CORRECTION
MT9V111_DS Rev. N 5/15 EN 12 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Output Data Ordering Output Data Ordering In YCbCr the first and second bytes can be swapped. Luma/chroma bytes can be swapped as well. R and B channels are bit-wise swapped when chroma swap is enabled. See IFP Reg0x3A for channel swapping configuration. Table 4: RGB Output Data Ordering in Default Mode A bypass mode is available whereby raw Bayer 10-bits data is output as two bytes. See IFP Reg8[7]. Table 5: Byte Ordering in 8 + 2 Bypass Mode Table 3: YUV/YCbCr Output Data Ordering Mode 1st Byte 2nd Byte 3rd Byte 4th Byte Default (no swap) Cb i Yi Cri Yi+1 Swapped CrCb Cr i Yi Cbi Yi+1 Swapped YC Y i Cbi Yi+1 Cri Swapped CrCb, YC Y i Cri Yi+1 Cbi Mode (Swap Disabled) Byte D7 D6 D5 D4 D3 D2 D1 D0 RGB 565 First R7 R6 R5 R4 R3 G7 G6 G5 Second G4 G3 G2 B7 B6 B5 B4 B3 R G B 5 5 5 F i r s t0 R 7R 6R 5R 4R 3G 7 G 6 Second G4 G3 G2 B7 B6 B5 B4 B3 RGB 444x First R7 R6 R5 R4 G7 G6 G5 G4 S e c o n d B 7 B 6 B 5 B 4 0000 RGB x444 First 0 0 0 0 R7 R6 R5 R4 Second G7 G6 G5 G4 B7 B6 B5 B4 Byte Ordering 8 + 2 B y p a s s F i r s t D 9D 8D 7D 6D 5D 4D 3D 2 S e c o n d 000000 D 1 D 0
MT9V111_DS Rev. N 5/15 EN 15 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Electrical Specifications Electrical Specifications The recommended die operating temperature ranges from -20°C to +40°C. The sensor image quality may degrade above +40°C. Notes: 1. To place the chip in standby mode, first raise STANDBY to V DD, then wait two master clock cycles before turning off the master clock. Two master clock cycles are required to place the analog cir- cuitry into standby, low-power mode. 2. When STANDBY is de-asserted, standby mode is ex ited immediately (within several master clocks), but the current frame and the next two frames will be invalid. The fourth frame will contain a valid image. Table 6: DC Electrical Characteristics VDD = VAA = 2.8 ± 0.25V; TA = 25°C Symbol Definition Condition MIN TYP MAX Unit VIH Input High Voltage V DD - 0.25 V DD + 0.25 V VIL Input Low Voltage -0.3 0.8 V IIN Input Leakage Current No Pull-up Resistor; VIN = VDD or DGND -5 5.0 A VOH Output High Voltage V DD - 0.2 V VOL Output Low Voltage 0.2 V IOH Output High Current 15.0 mA IOL Output Low Current 20.0 mA IOZ Tri-state Output Leakage Current 5.0 A IAA Analog Operating Supply Current Default settings, CLOAD = 10pF CLKIN = 12 MHz CLKIN = 27 MHz 10.0 10.0 20.0 20.0 25.0 25.0 mA IDD Digital Operating Supply Current Default settings, CLOAD = 10pF CLKIN = 12 MHz CLKIN = 27 MHz 5.0 10.0 8.0 15.0 20.0 20.0 mA IAA Standby Analog Standby Supply Current STDBY = V DD 0.0 2.5 5.0 A IDD Standby Digital Standby Supply Current STDBY = V DD 0.0 2.5 5.0 A
MT9V111_DS Rev. N 5/15 EN 16 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Electrical Specifications Notes: 1. For 30 fps operation with a 27 MHz clock, it is very important to have a precise duty cycle equal to 50%. With a slower frame rate and a slower clock the clock duty cycle can be relaxed. Table 7: AC Electrical Characteristics VDD = VAA = 2.8 ± 0.25V; TA = 25°C Symbol Definition Condition MIN TYP MAX Unit fCLKIN Input Clock Frequency 12 27 MHz Clock Duty Cycle 45 50 55 % tR Input Clock Rise Time 2.0 ns tF Input Clock Fall Time 2.0 ns tPLHP tPHLP CLKIN to PIXCLK propagation delay: LOW-to-HIGH HIGH-to-LOW CLOAD = 10pF ns tDSETUP tDHOLD PIXCLK to DOUT(7:0) at 27 MHz Setup Time Hold Time CLOAD = 10pF 13.0 13.0 ns tDSETUP tDHOLD PIXCLK to DOUT(7:0) at 12 MHz Setup Time Hold Time CLOAD = 10pF 25.0 25.0 ns tOH Data Hold Time from PIXCLK falling edge 9.0 ns tPLHF,L tPHLF,L CLKIN to FRAME_VALID and LINE_VALID propagation delay: LOW-to-HIGH HIGH-to-LOW C LOAD = 10pF 9.0 7.5 ns tOUTRO u t p u t R i s e T i m e C LOAD = 10pF 7.0 ns tOUTF Output Fall Time C LOAD = 10pF 9.0 ns
MT9V111_DS Rev. N 5/15 EN 18 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Propagation Delays Figure 12: Data Output Timing Diagram Note: PIXCLK = MAX 27 MHz tFVSETUP = / setup time for FRAME_VALID before rising edge of PIXCLK / = 18ns tFVHOLD = / hold time for FRAME_VALID after rising edge of PIXCLK / = 18ns tLVSETUP = / setup time for LINE_VALID before rising edge of PIXCLK / = 18ns tLVHOLD = / hold time for LINE_VALID after rising edge of PIXCLK / = 18ns tDSETUP = / setup time for DOUT before rising edge of PIXCLK / = 13ns tDHOLD = / hold time for DOUT after rising edge of PIXCLK / = 13ns Frame start: FF00 00A0 Line start: FF00 0080 Line end: FF00 0090 Frame end: FF00 00B0 PIXCLK FRAME_VALID LINE_VALID DOUT(7:0) tDSETUP tDHOLD tFVHOLD tLVHOLD Cb0 Y1Cr0 YlastYlast Cb0 Cb0Y0 tFVSETUP tLVSETUP
MT9V111_DS Rev. N 5/15 EN 20 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Appendix A – Sensor Timing Appendix A – Sensor Timing Figure 15: Row Timing and FRAME_VALID/LINE_VALID Signals Note: The signals in Figure 15 are defined in Table 8. Note: In order to avoid flicker, frame time is 65.65ms. Sensor timing is shown above in terms of master clock cycle. The vertical blanking and total frame time equations assume that the number of integration rows (bits 11 through 0 of Reg0x09) is less than the number of active row plus blanking rows (Reg0x03 + 1 + Reg0x06 + 1). If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 9. Table 8: Frame Time Parameter Name Equation (Master Clocks) Default Timing At 12 MHz A Active Data Time (Reg0x04 - 7) x 2 = 1,280 pixel clocks = 1,280 master clocks = 106.7us P1 Frame Start Blanking (Reg0x05 + 112) x 2 = 300 pixel clocks = 300 master clocks = 25.0us P2 Frame End Blanking 14 CLKS = 14 pixel clocks = 14 master clocks = 1.17us Q Horizontal Blanking (Reg0x05 + 121) x 2 (MIN Reg0x05 value = 9) = 318 pixel clocks = 318 master clocks = 26.5us A + Q Row Time (Reg0x04 + Reg0x05 +114) x 2 = 1,598 pixel clocks = 1,598 master clocks = 133.2us V Vertical Blanking (Reg0x06 + 9) x (A + Q) + (Q - P1 - P2) = 20, 778 pixel clocks = 20,778 master clocks = 1.73ms Nrows x (A + Q) Frame Valid Time (Reg0x03 - 7) x (A + Q) - (Q - P1 - P2) = 767,036 pixel clocks = 767,036 master clocks = 63.92ms F T otal Frame Time (Reg0x03 + Reg0x06 + 2) x (A + Q) = 787,814 pixel clocks = 787,814 master clocks = 65.65ms Table 9: Frame Time — Larger than One Frame Parameter Name Equation (Master Clocks) Default Timing V’ Vertical Blanking (long integration time) (Reg0x09 - Reg0x03) x (A + Q) – F’ Total Frame Time (long integration time) (Reg0x09 + 1) x (A + Q) – P1 A Q A Q AP 2Number of master clocks FRAME_VALID LINE_VALID ... ... ...
MT9V111_DS Rev. N 5/15 EN 21 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Serial Bus Description Serial Bus Description Registers are written to and read from the MT9V111 through the two-wire serial inter- face bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out of the MT9V111 through the serial data (S DATA) line. The SDATA line is pulled up to 2.8V off- chip by a 1.5K resistor. Either the slave or master device can pull the SDATA line down— the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. The registers are 16 bits wide and can be accessed through 16- bit or eight-bit two-wire serial bus sequences. Protocol The two-wire serial interface defines several different transmission codes, as follows: a s t a r t b i t the slave device eight-bit address. S ADDR is used to select between two different addresses in case of conflict with another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave address is 0xB8. a(n) (no) acknowledge bit an eight-bit message a s t o p b i t Sequence A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's eight-bit address. The last bit of the address determines if the request will be a read or a write, where a "0" indicates a write and a "1" indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9V111 uses 16-bit data for its internal registers, thus requiring two eight-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and eight-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data eight bits at a time. The master sends an acknowledge bit after each eight- bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. The MT9V111 allows for eight-bit data transfers through the two-wire serial interface by writing (or reading) the most significant eight bits to the register and then writing (or reading) the least significant eight bits to Reg0x7F (127). Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits.
MT9V111_DS Rev. N 5/15 EN 22 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Serial Bus Description Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of seven bits of address and 1 bit of direction. A “0” in the least significant bit (LSB) of the address indicates write mode, and a “1” indicates read mode. The write address of the sensor is 0xB8, while the read address is 0xB9; this only applies when S ADDR is set HIGH. Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the serial clock—it can only change when the two-wire se rial interface clock is LOW. Data is trans- ferred eight bits at a time, followed by an acknowledge bit. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.
MT9V111_DS Rev. N 5/15 EN 27 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Appendix B – Overview of Programming Appendix B – Overview of Programming Default Sensor Configuration In its default configuration, the sensor outputs up to 15 fps at 12 MHz master clock frequency. Auto exposure, automatic white balance, 60Hz flicker avoidance, defect correction, and automatic noise suppression in low light conditions are enabled. The frame rate is controlled by AE and can be slowed down to 5 fps in low light. Lens shading correction is disabled. Gamma correction uses gamma = 0.6. Image data are output in YCbCr ITU_R.BT .656 VGA format, with Y, Cb, and Cr values ranging from 16 to 240. The use of the non-default register settings shown in Table 10 are recommended to opti- mize sensor performance in the above configuration. Note: Non-default register settings required for an optimal 30 fps, 27 MHz operation are shown in Table 11 Note: To obtain register settings for other frame ra tes and clock speeds, please contact a ON Semicon- ductor FAE. Auto Exposure Target image brightness and accuracy of AE are set by IFP R46[7:0] and R46[15:8], respectively. For example, to overexpose images, set IFP R46[7:0] = 120. To change image brightness on LCD in RGB preview mode, use IFP R52[15:8]. AE logic can be programmed to keep the frame rate constant or vary it within certain range, by writing to IFP R55[9:5] one of the values tabulated in Table 12. The speed of AE is set using IFP R47. The speed should be high in preview modes and lower for video output to avoid sudden changes in brightness between frames. Auto exposure is disabled by setting IFP R6[14] = 0. When AE, AWB, and flicker avoidance are all disabled (IFP R6[14] = 0, IFP R6[1] = 0, and IFP R8[11] = 0), exposure and analog gains can be adjusted manually (see core registers R9, R12, and R43 through R46). Table 10: Non-Default Register Settings Optimizing 15 fps at 12 MHz Operation Core: R5 = 46, R7[4] = 0, R33 = 58369, R47 = 63414 IFP: R51= 5137, R56 = 2168, R57= 290, R59 = 1068, R62 = 4095, R64 = 7696, R65 = 5143, R66 = 4627, R67 = 4370, R68 = 28944, R69 = 29811 Table 11: Non-Default Register Settings Optimizing 30 fps at 27 MHz Operation Core: R5 = 132, R6 = 10, R7[4] = 0, R33 = 58369 IFP: R51 = 5137, R57 = 290, R59 = 1068, R62 = 4095, R89 = 504, R90 = 605, R92 = 8222, R93 = 10021, R100 = 4477 Table 12: Relation Between IFP R55[9:5] Setting and Frame Rate Range Minimum Frame Rate Maximum Frame Rate = 15 fps Maximum Frame Rate = 30 fps 30 fps N/A 4 15 fps 8 8 7.5 fps 16 16 5 fps 24 24
MT9V111_DS Rev. N 5/15 EN 28 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Appendix B – Overview of Programming Automatic White Balance AWB can be disabled by setting IFP R6[1]=0. Use IFP R37[2:0] and R37[6:3] to speed up AWB response. Please note that speeding AWB up may result in color oscillation. If necessary, AWB range can be restricted by changing the upper limit in IFP R36[14:8] and lower limit in IFP R36[6:0]. Flicker Avoidance Use IFP R91 to choose automatic/manual, 50Hz/60Hz flicker avoidance and IFP R8[11] = 0 to disable this feature. Flash For flash programming, see IFP R152 description. Decimation, Zoom, and Pan For output decimation programming, see IFP R165 description. Table 13 provides a few examples. Note: For fixed 2x upsize zoom, set core R30[0] = 1. Interpolation Use IFP R5[2:0] to adjust image sharpness. By default, sharpness is automatically reduced in low-light conditions (see IFP R5[3]). For RGB565 16-bit capture, set IFP R6[12] = 0 and IFP R5[3] = 0 to avoid contouring. Special Effects To switch from color to gray scale output, set IFP R8[5] = 1. Contact a ON Semiconductor FAE for register settings producing other special effects (e.g. sepia output). Image Mirroring To mirror images horizontally, set core R32[14] = 1 and IFP R8[0] = 1. To flip images verti- cally, set core R32[15] = 1 and IFP R8[1] = 1. Test Pattern See IFP R72 and IFP Reg58[5:3] description. Table 13: Decimation, Zoom, and Pan Ifp Registers CIF Output (Correct Aspect Ratio) QVGA Output 2:1 Zoom QVGA Output 1:1 Zoom R165 26 160 0 R166 586 320 640 R167 352 320 320 R168 0 120 0 R169 480 240 480 R170 288 240 240
MT9V111_DS Rev. N 5/15 EN 29 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Appendix B – Overview of Programming Gamma Correction See Table 14 and Table for register settings required to setup non-default gamma correc- tion. Please note that these settings determine output signal range. Use YCbCr settings with ITU_R BTU-compatible devices. Use YUV settings for JPEG capture and RGB preview; switching to YUV mode requires setting IFP R52 = 0 and IFP R53 = 65281. Table 14: YCbCr Settings Gamma 0.45 0.5 0.55 0.6 (Default) 0.7 1.0 IFP R83 12836 10781 8984 7700 5389 2052 IFP R84 23876 21563 19508 17709 14627 8208 IFP R85 39039 37495 35952 34409 31581 24640 IFP R86 49326 48553 47780 47008 45207 41088 IFP R87 57552 57551 57549 57548 57545 57536 Table 15: YUV Settings IFP R83 14377 12321 10267 8726 6159 2308 IFP R84 26957 24643 22331 20276 16680 9234 IFP R85 44432 42631 40831 39031 35945 27720 IFP R86 56005 54976 54202 53173 51371 46481 IFP R87 65260 65259 65257 65255 65252 65241
MT9V111_DS Rev. N 5/15 EN 30 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor Appendix B – Overview of Programming Figure 26: 44-Ball ICSP Package Outline Drawing Notes: 1. All dimensions in millimeters. 2. ICSP package information is preliminary. SEATING PLANE 7.00 ±0.075 3.50 ±0.052.25 2.25 ENCAPSULANT: EPOXY IMAGE SENSOR DIE LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS OPTICAL AREA OPTICAL CENTER PACKAGE CENTER 1.17 ±0.10 0.22 (FOR REFERENCE ONLY) 0.100 (FOR REFERENCE ONLY) 0.95 (FOR REFERENCE ONLY)
5.30 CTR
4.50
3.584 CTR
3.500 ±0.075 BALL A1 CORNER 5.30 CTR 2.688 CTR
0.75 TYP
7.00 ±0.075 0.375 ±0.075 0.575 ±0.050 0.175 (FOR REFERENCE ONLY) C L C L 4.50 SUBSTRATE MATERIAL: PLASTIC LAMINATE SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag OR 96.5% Sn, 3%Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: Ø 0.27 MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES: 1º MAXIMUM TILT OF OPTICAL AREA RELATIVE TO : 0.3º
0.10 A A
BALL A744X Ø0.35 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE- REFLOW DIAMETER IS Ø0.33 PIXEL (0,0) B B MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS: 0.3º
MT9V111_DS Rev. N 5/15 EN 31 ©Semiconductor Components Industries, LLC,2015. MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Revision History
Updated “Ordering Information” on page 2 Converted to ON Semiconductor template Updated trademarks Applied updated template Updated to non-confidential Updated to Aptina template Transfered registers to a separate document Updated Table 6, “IFP Register List,” on page 12 M o d i f i e d tOH definition in Table 7, “ AC Electrical Characteristics,” on page 16 Updated Figure 10, Propagation Delays for PIXCLK and Data Out Signals, on page 17 Updated 44-Ball ICSP Package Outline Drawing Replaced 28-Pin PLCC package information with the 44-Ball ICSP Updated Table 12 (Frame Time) Updated Electrical Specifications Modify for external web posting - streamlined register descriptions A d d A p p e n d i x B Added Key Performance Parameter Table, Update Register Tables, Update Electrical Specification Table, Added Figures (Image Center Offset, Die Placement, 28-Pin PLCC Package Outline Drawing and Spectral Response) Format edits on 1/15/04
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