MT9V032

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Technical content

Features

• Array Format: Wide−VGA, Active 752H x 480V (360,960 Pixels)
• Global Shutter Photodiode Pixels; Simultaneous Integration And Readout
• Monochrome Or Color: Near_IR Enhanced Performance For Use With Non−Visible NIR Illumination
• Readout Modes: Progressive Or Interlaced
• Shutter Efficiency: >99%
• Simple Two−Wire Serial Interface
• Register Lock Capability
• Window Size: User Programmable To Any Smaller Format (QVGA, CIF, QCIF, etc.). Data Rate Can Be Maintained Independent Of Window Size
• Binning: 2 x 2 And 4 x 4 Of The Full Resolution
• ADC: On−Chip, 10−bit Column−Parallel (Option To Operate In 12−bit To 10−bit Companding Mode)
• Automatic Controls: Auto Exposure Control (AEC) And Auto Gain Control (AGC); Variable Regional And Variable Weight AEC/AGC www.onsemi.com See detailed ordering and shipping information on page2 of this data sheet.

ORDERING INFORMATION

• Support For Four Unique Serial Control Register IDs To Control Multiple Imagers On The Same Bus
• Data Output Formats:
• Single Sensor Mode: 10−bit Parallel/Stand−Alone 8−bit Or 10−bit Serial LVDS
• Stereo Sensor Mode: Interspersed 8−bit Serial LVDS

Applications

• Security
• High Dynamic Range Imaging
• Unattended Surveillance
• Stereo Vision
• Video As Input
• Machine Vision
• Automation CLCC48 11.43 × 11.43 CASE 848AQ

www.onsemi.com Table of Contents Ordering Information 3 General Description 4 Pixel Data Format 8 Color Device Limitations 9 Output Data Format 10 Serial Bus Description 12 Two−Wire Serial Interface Sample Read and Write Sequences 14 Registers 16 Feature Description 31 On−Chip Biases 34 Window Control 35 Blanking Control 36 Pixel Integration Control 37 Gain settings 40 Read Mode Options 45 Electrical Specifications 50 Temperature Reference 55 Appendix A − Serial Configurations 57 Appendix B − Power−On Reset and Standby Timing 60

www.onsemi.com Table 2. AVAILABLE PART NUMBERS Specification Brochure, BRD8011/D. please visit our web site at www.onsemi.com.

variety of imaging applications in real−world environments. simple two−wire serial interface. wide−VGA−size image at 60 frames per second (fps). accurate digitization for darker areas in the image. stereo−slave sensor into one serial LVDS stream. Figure 1. Block Diagram

Figure 2. 48-Pin CLCC Pinout Diagram Table 3. PIN DESCRIPTIONS (Only pins DOUT0 through DOUT9 may be tri−stated) up (to 3.3V) in non−stereoscopy mode. 3.3V) in non−stereoscopy mode. 23 EXPOSURE Input Rising edge starts exposure in slave mode. even when no other two−wire serial interface peripheral is attached. 30 S_CTRL_ADR0 Input Two−wire serial interface slave address bit 3. 31 S_CTRL_ADR1 Input Two−wire serial interface slave address bit 5. 32 RESET# Input Asynchronous reset. All registers assume defaults. 33 STANDBY Input Shut down sensor operation for power saving.

47 SYSCLK Input Master clock (26.6 MHz). even when no other two−wire serial interface peripheral is attached.

22 STLN_OUT I/O Output in master mode— start line sync to drive slave chip in−

26 STFRM_OUT I/O Output in master mode— start frame sync to drive a slave chip in−

20 LINE_VALID Output Asserted when DOUT data is valid. 21 FRAME_VALID Output Asserted when DOUT data is valid. 15 DOUT5 Output Parallel pixel data output 5. 16 DOUT6 Output Parallel pixel data output 6. 17 DOUT7 Output Parallel pixel data output 7.

18 DOUT8 Output Parallel pixel data output 8

19 DOUT9 Output Parallel pixel data output 9. 27 LED_OUT Output LED strobe output. 41 DOUT4 Output Parallel pixel data output 4. 42 DOUT3 Output Parallel pixel data output 3. 43 DOUT2 Output Parallel pixel data output 2. 44 DOUT1 Output Parallel pixel data output 1. 45 DOUT0 Output Parallel pixel data output 0. 46 PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock. 2 SHFT_CLKOUT_N Output Output shift CLK (differential negative). 3 SHFT_CLKOUT_P Output Output shift CLK (differential positive). 4 SER_DATAOUT_N Output Serial data out (differential negative). 5 SER_DATAOUT_P Output Serial data out (differential positive). 1, 14 VDD Supply Digital power 3.3V. 35, 39 VAA Supply Analog power 3.3V. 40 VAAPIX Supply Pixel power 3.3V. 6 VDDLVDS Supply Dedicated power for LVDS pads. 7, 12 LVDSGND Ground Dedicated GND for LVDS pads. 13, 48 DGND Ground Digital GND. 34, 38 AGND Ground Analog GND.

1. Pin 29 (RSVD) must be tied to GND
2. Output Enable (OE) tri −states signals DOUT0–DOUT9. No other signals are tri−stated with OE.
3. No connect. These pins must be left floating for proper operation.

Figure 3. Typical Configuration (Connection)−Parallel Output Mode NOTE: LVDS signals are to be left floating. NOTE: LVDS signals are to be left floating.

www.onsemi.com COLOR DEVICE LIMITATIONS The color version of the MT9V032 does not support or offers reduced performance for the following functionalities. Pixel Binning Pixel binning is done on immediate neighbor pixels only; no facility is provided to skip pixels according to a Bayer pattern. Therefore, the result of binning combines pixels of different colors. For more information, see “Pixel Binning”. Interlaced Readout Interlaced readout yields one field consisting only of red and green pixels and another consisting only of blue and green pixels. This is due to the Bayer pattern of the CFA. Automatic Black Level Calibration When the color bit is set (R0x0F[2]=1), the sensor uses GREEN1 pixels black level correction value, which is applied to all colors. To use calibration value based on all dark pixels offset values, the color bit should be cleared. Other Limiting Factors Black level correction and row−wise noise correction are applied uniformly to each color. Automatic exposure and gain control calculations are made based on all three colors, not just the green luma channel. High dynamic range does operate; however, ON Semiconductor strongly recommends limiting use to linear operation if good color fidelity is required.

Figure 8. Row Timing and FRAME_VALID/LINE_VALID Signals Table 4. FRAME TIME − LARGER THAN ONE FRAME Table 5. FRAME TIME − LONG INTEGRATION TIME

1. The MT9V032 uses column parallel analog −to−digital converters, thus short row timing is not possible. The minimum total row time is 660

blanking must be increased. The frame rate will not increase for row times less than 660 columns.

www.onsemi.com SERIAL BUS DESCRIPTION Registers are written to and read from the MT9V032 through the two−wire serial interface bus. The MT9V032 is a serial interface slave with four possible IDs (0x90, 0x98, 0xB0,and 0xB8) determined by the S_CTRL_ADR0 and S_CTRL_ADR1 input pins. Data is transferred into the MT9V032 and out through the serial data (S DATA) line. The SDATA line is pulled up to VDD off−chip by a 1.5K/C0087 resistor. Either the slave or master device can pull the S DATA line down—the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. The registers are 16 −bit wide, and can be accessed through 16− or 8−bit two−wire serial interface sequences. Protocol The two −wire serial interface defines several different transmission codes, as follows:

• a start bit
• the slave device 8−bit address
• a(n) (no) acknowledge bit
• an 8−bit message
• a stop bit Sequence A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device’s 8−bit address. The last bit of the address determines if the request is a read or a write, where a “0” indicates a write and a “1” indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8−bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9V032 uses 16 −bit data for its internal registers, thus requiring two 8−bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write mode slave address and 8−bit register address, just as in the write request. The master then sends a start bit and the read mode slave address. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8 −bit transfer. The register address is auto −incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no−acknowledge bit. The MT9V032 allows for 8−bit data transfers through the two −wire serial interface by writing (or reading) the most significant 8 bits to the register and then writing (or reading) the least significant 8 bits to R0xF0 (240). Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH−to−LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW−to−HIGH transition of the data line while the clock line is HIGH. Slave Address The 8−bit address of a two −wire serial interface device consists of 7 bits of address and 1 bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates read mode. As indicated above, the MT9V032 allows four possible slave addresses determined by the two input pins, S_CTRL_ADR0 and S_CTRL_ADR1.

Table 6. SLAVE ADDRESS MODES time, followed by an acknowledge bit. during the acknowledge clock pulse.

Figure 12. Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284 mode register—register 13 only) can be locked. interface writes to the register are committed.

Table 8 provides detailed descriptions of the registers. Table 7. DEFAULT REGISTER DESCRIPTIONS (1 = always 1;0 = always; d = programmable; ? = read only)

Table 7. DEFAULT REGISTER DESCRIPTIONS (continued)(1 = always 1;0 = always; d = programmable; ? = read only)

is defined as the point at which the first dark row is read out. “Shadowed” column in Table 8.

• Shadowed N = No. The register value is updated and used immediately. Y = Yes. The register value is updated at next frame start. Frame start is defined as when the first dark row is read out. By default this is four rows before FRAME_V ALID goes HIGH.
• Read/Write R = Read−only register/bit. W = Read/Write register/bit. Table 8 provides a detailed description of the registers. Bit fields that are not identified in the table are read only.

Table 8. REGISTER DESCRIPTIONS

1 Y 1–752 W

4 Y 4–482 W

any dark rows or border rows that may be read). any dark columns or border columns that may be read). equal to or larger than four.

2:0 Scan Mode 0 = Progressive scan. read first, and followed by odd−numbered rows. read out. Effective image size is decreased by half.

0 Y 0, 2, 3 W

3 Sensor Master/Slave

0 = Slave mode. Initiating exposure and readout is allowed.

1 Y 0,1 W

4 Sensor Snapshot Mode 0 = Snapshot disabled. slave mode should be set to logic 1 to turn on this mode.

0 Y 0,1 W

PLL generates a 320 MHz (x12) clock.

6 Stereoscopic

7 Parallel Output Enable 0 = Disable parallel output. DOUT(9:0) are in High−Z.

8 Simultaneous/

only after exposure is complete. place in conjunction with exposure. made does not take effect until the following new frame. t3 = Total integration – Shutter width 2. t2 = Total integration × (½)t2_ratio.

4 N 0–15 W

t3 = Total integration × (½)t3_ratio. Note: t1 = Total integration − t2 − t3.

6 N 0–15 W

8 Exposure Knee Point

1 N 0,1 W

9 Single Knee Enable 0 = Single knee disabled.

0 N 0,1 W

take effect until the following new frame.

0 Soft Reset Setting this bit causes the sensor to abandon the current

0 N 0, 1 W

1 Auto Block Soft Reset Setting this bit causes the sensor to reset the automatic

0 Y 0, 1 W

1:0 Row Bin 0 = Normal operation. 1 = Row bin 2. Two pixel rows are read per row output. frame rate is increased by 2. 2 = Row bin 4. Four pixel rows are read per row output. frame rate is increased by 4.

0 Y 0, 1, 2 W

3:2 Column Bin 0 = Normal operation.

6 Show Dark Rows When set, the programmed dark rows is output before the

normal. This has no effect on integration time or frame rate. definition frame start is before the dark rows are read out.

7 Show Dark Columns When set, the programmed dark columns are output before

0 Monitor Mode Enable Setting this bit puts the sensor into a cycle of sleeping for

2 Color/Mono Should be set according to sensor type:

6 High Dynamic Range 0 = Linear operation. be correctly set for saturation control to operate.

2 Y 2, 3 W

4 N 0–7 W

Usage: V_Step1 HiDy voltage.

Usage: V_Step2 HiDy voltage. Usage: V_Step3 HiDy voltage. blooming when V_Step is disabled.

4 N 0–31 W

used in the black level algorithm calculations. 0 Manual Override Manual override of black level correction. 0 = Normal operation (default). frame ave)/2n + (new frame ave)/ 2n.

formula: Sign = bit 7 (0 is positive, 1 is negative). If positive offset value: Magnitude = bit 6:0. If negative offset value: Magnitude = not (bit 6:0) + 1. obtained from the calibration algorithm.

0 N –127 to

negatively) from frame to frame. 1 calib LSB = ½ ADC LSB, assuming analog gain = 1.

2 N 0–31 W

See “Row−wise Noise Correction” for additional information.

4 Y 0, 1, 2,

5 Enable noise correction 0 = Normal operation.

1 Y 0, 1 W

11 Use black level average 1 = Use black level frame average from the dark rows in the

DAC for that frame, so it might be slightly off. used in the row−wise noise correction algorithm. logic “0” when frame is valid.

2 XOR Line Valid 1 = Line valid = ”Continuous” Line Valid XOR Frame Valid

3 Continuous Line Valid 1 = ”Continuous” Line Valid (continue producing line valid

and DOUT is set up to the rising edge of pixel clock, PIXCLK. When clear, they are set up to the falling edge of PIXCLK. use two−wire serial interface (bit 10) must be set.

0 N 0–1023 W

10 Use Two−wire Serial In-

0 = Use Gray Shade Test Pattern as test data.

0 N 0–3 W

13 Test Enable Enable the use of test data/gray shaded test pattern in the

values and the result is not accurate.

14 Flip Two−Wire Serial In-

test data is used on even columns. additional information on digital gain.

4 Y 1–15 W

gain/exposure control algorithm.

ing the exposure register (R0xBB).

2 Y 0–15 W

2 Y 0–2 WX

ing the gain register (R0xBA).

Actual new gain = Current gain+ (calculated new gain/4).

2 Y 0–2 W

0 AEC Enable 0 = Disable Automatic Exposure Control

1 AGC Enable 0 = Disable Automatic Gain Control. 1 = Enable Automatic Gain Control. 0 PLL Bypass 0 = Internal shift−CLK is driven by PLL. 1 LVDS Power−down 0 = Normal operation. 2 PLL Test Mode 0 = Normal operation. 3 LVDS Test Mode 0 = Normal operation.

0 Y 0–7 W

4 LVDS Receiver Power−

4 LVDS Driver Power−

0 LVDS Internal Sync En-

all zeros except start bit) on LVDS_SER_DATA_OUT.

0 Use 10−bit Pixel Enable When set, all 10 pixel data bits are output in stand−alone

mat” for additional information.

0 Enable Stereo Error

1 Enable Stick Stereo Er-

error is detected unless clear stereo error flag (bit 2) is set.

2 Clear Stereo Error Flag Set this bit to clear the stereoscopy error flag (R0xB8

a reserved byte and slave has not. threshold, the exposure is increased. 8:0 Field Vertical Blank The number of blank rows between odd and even fields. Note: For interlaced (both field) mode only. See R0x07[2:0]. period when monitor mode is enabled.

1 N 0–7 W

0 Extend Frame Valid When set, frame valid is extended for half−line in length at

1 Replace FV/LV with

7:0 Front porch width The front porch width in number of master clock cycle. 15:8 Sync Width The sync pulse width in number of master clock cycle. NTSC standard is 4.7/C0109sec ±0.1/C0109sec. standard is 2.3/C0109sec ±0.1/C0109sec. standard is 4.7/C0109sec ±0.1/C0109sec. ignored until two−wire serial interface is unlocked. this register only is ignored until register is unlocked.

www.onsemi.com ON−CHIP BIASES ADC Voltage Reference The ADC voltage reference is programmed through R0x2C, bits 2:0. The ADC reference ranges from 1.0V to 2.1V . The default value is 1.4V . The increment size of the voltage reference is 0.1V from 1.0V to 1.6V (R0x2C[2:0] values 0 to 6). At R0x2C[2:0] = 7, the reference voltage jumps to 2.1V . The effect of the ADC calibration does not scale with V REF. Instead it is a fixed value relative to the output of the analog gain stage. At default, one LSB of calibration equals two LSB in output data (1LSB Offset = 2mV , 1LSBADC = 1mV). It is very important to preserve the correct values of the other bits in R0x2C. The default register setting is 0x0004. V_Step Voltage Reference This voltage is used for pixel high dynamic range operations, programmable from R0x31 through R0x34. Chip Version Chip version registers R0x00 and R0xFF are read−only.

www.onsemi.com WINDOW CONTROL Registers R0x01 column start, R0x02 Row Start, R0x03 window height (row size), and R0x04 window width (column size) control the size and starting coordinates of the window. The values programmed in the window height and width registers are the exact window height and width out of the sensor. The window start value should never be set below four. To read out the dark rows set bit 6 of R0x0D. In addition, bit 7 of R0x0D can be used to display the dark columns in the image.

www.onsemi.com BLANKING CONTROL Horizontal blanking and vertical blanking registers R0x05 and R0x06 respectively control the blanking time in a row (horizontal blanking) and between frames (vertical blanking).

• Horizontal blanking is specified in terms of pixel clocks.
• Vertical blanking is specified in terms of numbers of rows. The actual imager timing can be calculated using Table4 and Table 5 which describe “Row Timing and FRAME_V ALID/LINE_V ALID signals.” The minimum number of vertical blank rows is 4.

• The number of rows integration is equal to the result of automatic exposure control (AEC) which may vary from frame to frame, or, if AEC is disabled, the value in R0x0B
• Row time = (R0x04 + R0x05) master clock periods
• Overhead = (R0x04 + R0x05 – 255) master clock periods Typically, the value of R0x0B (total shutter width) is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. If R0x0B is increased beyond the total number of rows per frame, it is required to add additional blanking rows using R0x06 as needed. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60Hz flicker, this means frame time must be a multiple of 1/120 of a second. Under 50Hz flicker, frame time must be a multiple of 1/100 of a second. Changes to Integration Time With automatic exposure control disabled (R0xAF, bit 0 is cleared to LOW), and if the total integration time (R0x0B) is changed through the two −wire serial interface while FRAME_V ALID is asserted for frame n, the first frame output using the new integration time is frame ( n + 2). Similarly, when automatic exposure control is enabled, any change to the integration time for frame n first appears in frame (n + 2) output. The sequence is as follows: 1. During frame n, the new integration time is held in the R0x0B live register. 2. At the start of frame (n + 1), the new integration time is transferred to the exposure control module. Integration for each row of frame (n + 1) has been completed using the old integration time. The earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame (n + 1). The actual time that rows start integrating using the new integration time is dependent on the new value of the integration time. 3. When frame (n + 1) is read out, it is integrated using the new integration time. If the integration time is changed (R0x0B written) on successive frames, each value written is applied to a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. However, when automatic exposure control is disabled, if the integration time is changed through the two−wire serial interface after the falling edge of FRAME_V ALID for frame n, the first frame output using the new integration time becomes frame (n+3 ). FRAME_VALID LED_OUT New Integration Programmed Actual Integration Image Data Frame Start

Figure 20. Latency When Changing Integration

adjust must also be enabled. By default, ADC resolution of the sensor is 10 −bit. Figure 23. 12−to 10−Bit Companding Chart

changed, the gain is updated on the next frame start. depends on the automatic gain control. changed for frame n first appears in frame (n + 2). the integration time is also changed simultaneously. Figure 24. Latency of Analog Gain Change When AGC Is Disabled

• R0x35 global gain The formula for gain setting is: Gain /C0043Bits[6 : 0] x 0.0625 (eq. 8) The analog gain range supported in the MT9V032 is 1X–4X with a step size of 6.25 percent. To control gain manually with this register, the sensor must NOT be in AGC mode. When adjusting the luminosity of an image, it is recommended to alter exposure first and yield to gain increases only when the exposure value has reached a maximum limit. Analog gain /C0043bits (6 : 0) x 0.0625 for values16/C004231 (eq. 9) Analog gain /C0043bits (6 : 0) /C03242x 0.125 for values 32 /C004264 (eq. 10) For values 16–31: each LSB increases analog gain For values 32–64: each 2 LSB increases analog gain 0.125v/v (that is, double the gain increase for 2 LSB). Range: 2X to 4X. Odd values do not result in gain increases; the gain increases by 0.125 for values 32, 34, 36, and so on. Digital Gain Digital gain is controlled by:
• R0x99–R0xA4 tile coordinates
• R0x80–R0x98 tiled digital gain and weight In the MT9V032, the image may be divided into 25 tiles, as shown in Figure 25, through the two−wire serial interface, and apply digital gain individually to each tile. X0/5 X1/5 X2/5 X3/5 X4/5 X5/5 Y0/5 Y2/5 Y1/5 Y3/5 Y4/5 Y5/5

Figure 25. Tiled Sample

• R0x4C
• R0x42
• R0x46–R0x48 The MT9V032 has automatic black level calibration on−chip, and if enabled, its result may be used in the offset correction shown in Figure 26.

Figure 26. Black Level Calibration Flow Chart random instabilities associated with this measurement. voltage is decreased by 2 LSB (default). the difference is at least two times the offset DAC step size. 6) if using an external black level calibration circuit.

• R0x70 row noise control
• R0x72 row noise constant
• R0x73 dark column start When the row −wise noise cancellation algorithm is enabled, the average value of the dark columns read out is used as a correction for the whole row. The row −wise correction is in addition to the general black level correction applied to the whole sensor frame and cannot be used to replace the latter. The dark average is subtracted from each pixel belonging to the same row, and then a positive constant is added (R0x72, bits 7:0). This constant should be set to the dark level targeted by the black level algorithm plus the noise expected on the measurements of the averaged values from dark columns; it is meant to prevent clipping from negative noise fluctuations. Pixel value /C0043ADC value /C0042dark column average /C0041row noise constant (eq. 14) On a per−row basis, the dark column average is calculated from a programmable number of dark columns (pixels) values (R0x70, bits 3:0). The default is 10 dark columns. Of these, the maximum and minimum values are removed and then the average is calculated. If R0x70, bits 3:0 are set to “0” (2 pixels), it is essentially equivalent to disabling the dark average calculation since the average is equal to “0” after the maximum and minimum values are removed. R0x73 is used to indicate the starting column address of dark pixels that the row−noise correction algorithm uses for calculation. In the MT9V032, dark columns which may be used are 759–776. R0x73 is used to select the starting column for the calculation. One additional note in setting the row −noise correction register: 777 /C0116(R0x73, bits9 : 0) /C0041number of dark pixels programmed in R0x70, bits3 : 0 /C00421 (eq. 15)

the limit the MT9V032 can support. computed and updated every frame. Figure 27. Controllable and Observable AEC/AGC Registers and “Column Binning” for additional information.

• R0x0C reset Bit 0 is used to reset the digital logic of the sensor while preserving the existing two −wire serial interface configuration. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. Bit 1 is a shadowed reset control register bit to explicitly reset the automatic gain and exposure control feature. These two bits are self−resetting bits and also return to “0” during two−wire serial interface reads. STANDBY Control The sensor goes into standby mode by setting STANDBY to HIGH. Once the sensor detects that STANDBY is asserted, it completes the current frame before disabling the digital logic, internal clocks, and analog power enable signal. To release the sensor from the standby mode, reset

www.onsemi.com STANDBY back to LOW. The LVDS must be powered to ensure that the device is in standby mode. See “Appendix B – Power−On Reset and Standby Timing” for more information on standby. Monitor Mode Control Monitor mode is controlled by:

• R0x0E monitor mode enable
• R0xC0 monitor mode image capture control The sensor goes into monitor mode when R0x0E bit 0 is set to HIGH. In this mode, the sensor first captures a programmable number of frames (R0xC0), then goes into a sleep period for five minutes. The cycle of sleeping for five minutes and waking up to capture a number of frames continues until R0x0E bit 0 is cleared to return to normal operation. In some applications when monitor mode is enabled, the purpose of capturing frames is to calibrate the gain and exposure of the scene using automatic gain and exposure control feature. This feature typically takes less than 10 frames to settle. In case a larger number of frames is needed, the value of R0xC0 may be increased to capture more frames. During the sleep period, none of the analog circuitry and a very small fraction of digital logic (including a five −minute timer) is powered. The master clock (SYSCLK) is therefore always required.

FRAME_V ALID are always embedded in the pixel data. Figure 34. Serial Output Format for 6x2 Frame NOTES: 1. External pixel values of 0, 1, 2, 3, are reserved (they only convey control information). Any raw pixel of value 0, 1, 2 and 3 will be substituted with 4.

1. The external pixel sequence 1023, 0 1023 is a reserved sequence (conveys control

information). Any raw pixel sequence of 1023, 0, 1023 will be substituted with 1023, 4, 1023. 10−bit pixel data, and the stop bit. Table 9. LVDS PACKET FORMAT IN STAND−ALONE MODE (Stereoscopy Mode Bit De−Asserted)

12 Bit Packet

Table 10. LVDS PACKET FORMAT IN STEREOSCOPY MODE (Stereoscopy Mode Bit Asserted) data in the form of reserved words. Table 11. RESERVED WORDS IN THE PIXEL DATA STREAM

0 Precedes frame valid assertion

1 Precedes line valid assertion

2 Succeeds line valid de−assertion

3 Succeeds frame valid de−assertion

• For bin 2, LVDS outputs double the expected data (pixel 0,0 is output twice in sequence, followed by pixel 0,1 twice, . . .).
• For bin 4, LVDS outputs 4 times the expected data (pixel 0,0 is output 4 times in sequence followed by pixel 0,1 times 4, . . .). The receiving hardware will need to undersample the output stream getting data either every 2 clocks (bin 2) or every 4 (bin 4) clocks. If the sensor provides a pixel whose value is 0,1, 2, or 3 (that is, the same as a reserved word) then the outgoing serial pixel value is switched to 4

Table 12. DC ELECTRICAL CHARACTERISTICS (VPWR = 3.3V +0.3V; TA = Ambient = 25°C)

Table 13. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.

1. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Table 14. AC ELECTRICAL CHARACTERISTICS (VPWR = 3.3V ±0.3V; TA = Ambient = 25°C; Output Load = 10pF)

1. The frequency range specified applies only to the parallel output mode of operation.

falling edge and the data output transition is typically 7ns. approximately the same time as the data output transitions. See Table 14 for data setup and hold times. output of the last valid pixel’s data.

Figure 45. Package Mechanical Drawing (CASE 848AQ)

0.8 TYP

NOTES: 1. All dimensions in millimeters.

1. Optical center = Package center

LINE_V ALID and FRAME_V ALID.

26.6 Mhz

Figure 46. Stand−Alone Topology

1. Enable LVDS driver (set R0xB3[4]= 0).
2. De−assert LVDS power−down (set R0xB1[1] = 0.
3. Issue a soft reset (set R0x0C[0] = 1 followed by
4. Force sync patterns for the deserializer to lock (set
5. Stop applying sync patterns (set R0xB5[0] = 0).

same system clock frequency).

Figure 47. Stereoscopic Topology

1. Broadcast WRITE to de−assert LVDS

power−down (set R0xB1[1] = 0).

1. Individual WRITE to master sensor putting its

internal PLL into bypass mode (set R0xB1[0] = 1).

1. Broadcast WRITE to both sensors to set the

stereoscopy bit (set R0x07[5] = 1).

1. Make sure all resolution, vertical blanking,
2. Broadcast WRITE to enable LVDS driver (set
3. Broadcast WRITE to enable LVDS receiver (set
4. Individual WRITE to master sensor, putting its

internal PLL into bypass mode (set R0xB1[0] = 1).

1. Individual WRITE to slave sensor, enabling its

internal PLL (set R0xB1[0] = 0).

1. Individual WRITE to slave sensor, setting it as a

stereo slave (set R0x07[6] = 1).

1. Individual WRITEs to master sensor to minimize
2. Broadcast WRITE to issue a soft reset (set

sensor’s codes at this reserved byte must match). until the stereo_error_flag remains cleared. arrive at the same time at each sensor.

• system clock
• system reset
• two−wire serial interface clk − SCL
• two−wire serial interface data − SDA

All system clock lengths (L) must be equal. SCL and SDA lengths to each sensor (from the host) must also be equal. Figure 48. Two−Wire Serial Interface Configuration in Stereoscopic Mode S_CTRL_ADR input bit for both slave and master sensor. S_CTRL_ADR input bit for both slave and master sensor.

to Figure 49 for the power−up, reset, and standby sequences. Figure 49. Power−up, Reset, Clock and Standby Sequence

1. All output signals are defined during initial power−up with RESET# held LOW without SYSCLK being active. To properly
2. Before using two −wire serial interface,wait for 10 SYSCLK rising edges after RESET# is de−asserted.
3. Once the sensor detects that STANDBY has been asserted, it completes the current frame readout before entering
4. In standby, all video data and synchronization output signals are High −Z.
5. In standby, the two −wire serial interface is not active.

image sensor to default startup conditions.

1. Asserting STANDBY during the valid frame
2. Asserting STANDBY at the end of valid frame

+ 5] row−times after the falling edge of FRAME_V ALID.

Figure 50. STANDBY Restricted Location ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries i n the United States and/or other countries. arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. literature is subject to all applicable copyright laws and is not for resale in any manner.