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Technical content
Features
- Array Format: Wide−VGA, Active 752 H x 480 V (360,960 pixels)
- Global Shutter Photodiode Pixels; Simultaneous Integration and Readout
- RGB Bayer, Monochrome, or RCCC: NIR Enhanced Performance for Use with Non−visible NIR Illumination
- Readout Modes: Progressive or Interlaced
- Shutter Efficiency: >99%
- Simple Two−Wire Serial Interface
- Real−Time Exposure Context Switching−Dual Register Set
- Register Lock Capability www.onsemi.com See detailed ordering and shipping information on page2 of this data sheet.
ORDERING INFORMATION
Features (continued)
- Window Size: User Programmable to Any Smaller Format (QVGA, CIF, QCIF). Data Rate Can Be Maintained Independent of Window Size
- Binning: 2 x 2 and 4 x 4 of The Full Resolu- tion
- ADC: On−Chip, 10−bit Column−Parallel (Option to Operate in 12−bit to 10−bit Companding Mode)
- Automatic Controls: Auto Exposure Control (AEC) and Auto Gain Control (AGC); Vari- able Regional and Variable Weight AEC/ AGC
- Support for Four Unique Serial Control Register IDs to Control Multiple Imagers on the Same Bus
- Data Output Formats: ♦ Single Sensor Mode: 10−bit Parallel/Stand−Alone 8−bit or 10−bit Serial LVDS ♦ Stereo Sensor Mode: Interspersed 8−bit Serial LVDS
- High Dynamic Range (HDR) Mode IBGA52 CASE 503AA
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Applications
- Automotive
- Unattended Surveillance
- Stereo Vision
- Smart vision
- Automation
- Video as input
- Machine vision
Table 2. AVAILABLE PART NUMBERS a simple two−wire serial interface. a wide−VGA−size image at 60 frames per second (fps). accurate digitization for darker areas in the image. stereo−slave sensor into one serial LVDS stream.
752 H x 480 V
Figure 1. Block Diagram Figure 2. Top View (Ball Down)
Table 3. BALL DESCRIPTIONS
- Pin H7 (RSVD) must be tied to GND.
- Output enable (OE) tri −states signals DOUT0−DOUT9, LINE_VALID, FRAME_VALID, and PIXCLK.
- No connect. These pins must be left floating for proper operation.
Figure 3. Typical Configuration (Connection)−Parallel Output Mode NOTE: LVDS signals are to be left floating.
green pixels. This is due to the Bayer pattern of the CFA. be acceptable for some applications. correction algorithm does not work well in color sensors. linear operation where good color fidelity is required. by horizontal and vertical blanking, as shown in Figure 7. the description of FV timing. Figure 7. Spatial Illustration of Image Readout 10−bit pixel datum is output every PIXCLK period.
Figure 8. Timing Example of Pixel Data causes the MT9V024 to invert the polarity of the PIXCLK. Table 4. FRAME TIME Table 3. In this example, it is assumed that the coarse shutter shutter width total is zero.
but it may extend the readout time. Table 5. FRAME TIME − LONG INTEGRATION TIME
- The MT9V024 uses column parallel analog −digital converters; thus short row timing is not possible. The minimum total row time is 704
SDATA line is pulled up to VDD off−chip by a 1.5 k/C0087 resistor. 8−bit two−wire serial interface sequences.
- the slave device 8−bit address
- a(n) (no) acknowledge bit
the data line while the clock line is HIGH. during the acknowledge clock pulse. the data line while the clock line is HIGH. acknowledge bit back to the master. 8−bit register address to which a WRITE should take place. master stops writing by sending a start or stop bit.
will show up in the n+2 image. Table 7. REAL−TIME CONTEXT−SWITCHABLE REGISTERS
Table 8. RECOMMENDED REGISTER SETTINGS AND PERFORMANCE IMPACT R0x2B 0x0004 0x0003 Improves column FPN. R0x2F 0x0004 0x0003 Improves FPN at near−saturation. The MT9V024 works in master, snapshot, or slave mode. AND9255/D Master Exposure Mode Operation. Figure 14. Simultaneous Master Mode Synchronization Waveforms #1
www.onsemi.com The values programmed in the window height and width registers are the exact window height and width out of the sensor. The window start value should never be set below four. To read out the dark rows set bit 6 of R0x0D. In addition, bit 7 of R0x0D can be used to display the dark columns in the image. Note that there are Show Dark settings only for context A. BLANKING CONTROL Horizontal blank and vertical blank registers R0x05 and R0x06 (B: 0xCD and R0xCE), respectively, control the blanking time in a row (horizontal blanking) and between frames (vertical blanking).
- Horizontal blanking is specified in terms of pixel clocks.
- Vertical blanking is specified in terms of numbers of rows. The actual imager timing can be calculated using Table 2 and Table 3, which describe “Row Timing and FV/LV signals.” The minimum number of vertical blank rows is 4. PIXEL INTEGRATION CONTROL Total Integration Total integration time is the result of coarse shutter width and fine shutter width registers, and depends also on whether manual or automatic exposure is selected. The actual total integration time, t INT is defined as: tINT /C0043tINTCoarse /C0041tINTint (eq. 1) = (number of rows of integration × row time) + (number of pixels of integration × pixel time) where:
- Number of Rows of Integration (Auto Exposure Control: Enabled) When automatic exposure control (AEC) is enabled, the number of rows of integration may vary from frame to frame, with the limits controlled by R0xAC (minimum coarse shutter width) and R0xAD (maximum coarse shutter width).
- Number of Rows of Integration (Auto Exposure Control: Disabled) If AEC is disabled, the number of rows of integration equals the value in R0x0B. or If context B is enabled, the number of rows of integration equals the value in R0xD2.
- Number of pixels of Integration The number of fine shutter width pixels is independent of AEC mode (enabled or disabled): ♦ Context A: the number of pixels of integration equals the values in R0xD5. ♦ Context B: the number of pixels of integration equals the value in R0xD8. Row Timing Context A: Row time /C0043(R0x04 /C0041R0x05)master clock periods (eq. 2) Context B: Row time /C0043(R0xCC /C0041R0xCD) master clock periods (eq. 3) Typically, the value of the Coarse Shutter Width Total registers is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. If the Coarse Shutter Width Total is increased beyond the total number of rows per frame, the user must add additional blanking rows using the Vertical Blanking registers as needed. See descriptions of the Vertical Blanking registers, R0x06 and R0xCE in Table 1and Table 2 of the MT9V024 register reference. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60Hz flicker, this means the frame time must be a multiple of 1/120 of a second. Under 50Hz flicker, the frame time must be a multiple of 1/100 of a second. Changes to Integration Time With automatic exposure control disabled (R0xAF[0] for context A, or R0xAF[8] for context B) and if the total integration time (R0x0B or R0xD2) is changed through the two−wire serial interface while FV is asserted for frame n, the first frame output using the new integration time is frame (n + 2). Similarly, when automatic exposure control is enabled, any change to the integration time for frame n first appears in frame (n + 2) output. Additional details on this latency can be found in AND9251/D − Latency of Exposure or Gain Switch.
- R0x35 Global Gain context A
- R0x36 Global Gain context B The formula for gain setting is: Gain /C0043Bits[6 : 0] x 0.0625 (eq. 16) The analog gain range supported in the MT9V024 is 1X–4X with a step size of 6.25 percent. To control gain manually with this register, the sensor must NOT be in AGC mode. When adjusting the luminosity of an image, it is recommended to alter exposure first and yield to gain increases only when the exposure value has reached a maximum limit. Analog gain = bits (6:0) x 0.0625 for values 16–31 Analog gain = bits (6:0)/2 x 0.125 for values 32–64 For values 16–31: each LSB increases analog gain 0.0625v/v. A value of 16 = 1X gain. Range: 1X to 1.9375X. For values 32–64: each 2 LSB increases analog gain 0.125v/v (that is, double the gain increase for 2 LSB). Range: 2X to 4X. Odd values do not result in gain increases; the gain increases by 0.125 for values 32, 34, 36, and so on. Digital Gain Digital gain is controlled by:
- R0x99−R0xA4 Tile Coordinates
- R0x80−R0x98 Tiled Digital Gain and Weight In the MT9V024, the gain logic divides the image into 25 tiles, as shown in Figure 27. The size and gain of each tile can be adjusted using the above digital gain control registers. Separate tile gains can be assigned for context A and context Registers 0x99–0x9E and 0x9F–0xA4 represent the coordinates X0/5–X5/5 and Y0/5–Y5/5 in Figure 27 on page 31, respectively. Digital gains of registers 0x80–0x98 apply to their corresponding tiles. The MT9V024 supports a digital gain of 0.25–3.75X. When binning is enabled, the tile offsets maintain their absolute values; that is, tile coordinates do not scale with row or column bin setting. Digital gain is applied as soon as register is written. NOTE: There is one exception, for the condition when Column Bin 4 is enabled (R0x0D[3:2] or R0x0E[3:2] = 2). For this case, the value for Digital Tile Coordinate X–direction must be doubled. The formula for digital gain setting is: Digital Gain /C0043Bits[3 : 0] x 0.25 (eq. 17) X0/5 X1/5 X2/5 X3/5 X4/5 X5/5 Y0/5 Y2/5 Y1/5 Y3/5 Y4/5 Y5/5
Figure 27. Tiled Sample
- Frame Dark Average: R0x42
- Dark Average Thresholds: R0x46
- Black Level Calibration Control: R0x47
- Black Level Calibration Value: R0x48
- Black Level Calibration Value Step Size: R0x4C The MT9V024 has automatic black level calibration on−chip, and if enabled, its result may be used in the offset correction shown in Figure 28.
Figure 28. Black Level Calibration Flow Chart random instabilities associated with this measurement. voltage is decreased by 2 LSB (default). the difference is at least two times the offset DAC step size. external black level calibration circuit. its nearest−neighbor pixel, depending on pixel location. correction should be disabled (R0x07[9] = 0).
- R0x70 Row Noise Control
- R0x72 Row Noise Constant Row−wise noise cancellation is performed by calculating a row average from a set of optically black pixels at the start of each row and then applying each average to all the active pixels of the row. Read Dark Columns register bit and Row Noise Correction Enable register bit must both be set to enable row−wise noise cancellation to be performed. The behavior when Read Dark Columns register bit = 0 and Row Noise Correction Enable register bit = 1 is undefined. The algorithm works as follows: Logical columns 755−790 in the pixel array provide 36 optically black pixel values. Of the 36 values, two smallest value and two largest values are discarded. The remaining 32 values are averaged by summing them and discarding the
from negative noise fluctuations. Note that this algorithm does not work in color sensor. computed and updated every frame. “Pixel Integration Control” for more information. Figure 29. Controllable and Observable AEC/AGC Registers exposure is limited by AEC Minimum Exposure, R0xAC. gain are then calculated from this for subsequent frame. R0xA5, may be adjusted as required.
- R0x0C Reset
the topologies for both stand−alone and stereoscopic modes. required to extract LV and FV from the 8 −bit pixel data. FV are always embedded in the pixel data. merged. The combo_reg is used for out−of−sync diagnosis. Figure 36. Serial Output Format for 6x2 Frame NOTES: 1. External pixel values of 0, 1, 2, 3, are reserved (they only convey control information). Any raw pixel of value 0, 1, 2 and 3 will be substituted with 4.
- The external pixel sequence 1023, 0 1023 is a reserved sequence (conveys control
information). Any raw pixel sequence of 1023, 0, 1023 will be substituted with 1023, 4, 1023. 10−bit pixel data, and the stop bit.
Table 10. LVDS PACKET FORMAT IN STAND−ALONE MODE (Stereoscopy Mode Bit De−Asserted)
12 Bit Packet
- In stereoscopic mode, the packet size is 18 bits (2 frame bits and 16 payload bits). The packet consists of a start bit, the master pixel byte
Table 11. LVDS PACKET FORMAT IN STEREOSCOPY MODE (Stereoscopy Mode Bit Asserted)
Table 12. RESERVED WORDS IN THE PIXEL DATA STREAM
0 Precedes frame valid assertion
1 Precedes line valid assertion
2 Succeeds line valid de−assertion
3 Succeeds frame valid de−assertion
- For bin 2, LVDS outputs double the expected data (pixel 0,0 is output twice in sequence, followed by pixel 0, 1 twice, …).
- For bin 4, LVDS outputs 4 times the expected data (pixel 0,0 is output 4 times in sequence followed by pixel 0, 1 times 4, …). The receiving hardware will need to undersample the output stream,getting data either every 2 clocks (bin 2) or every 4 (bin 4) clocks. If the sensor provides a pixel whose value is 0, 1, 2, or 3 (that is, the same as a reserved word) then the outgoing serial pixel value is switched to 4. LVDS Enable and Disable The Table 10 and Table 11 further explain the state of the LVDS output pins depending on LVDS control settings. When the LVDS block is not used, it may be left powered down to reduce power consumption.
**Table 13. SER_DATAOUT_*STATE** **Table 14. SER_DATAOUT_*STATE**
- ERROR pin: When the sensor is not in stereo mode, the ERROR pin is at LOW.
specifications are shown in Table 12 and Figure 37. Figure 37. LVDS Timing Table 15. LVDS AC TIMING SPECIFICATIONS
Table 16. DC ELECTRICAL CHARACTERISTICS OVER TEMPERATURE performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 17. DC ELECTRICAL CHARACTERISTICS (VPWR = 3.3 V ± 0.3 V; TA = Ambient = 25 °C)
Table 18. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- This is a stress rating only, and functional operation of the device at these other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 19. AC ELECTRICAL CHARACTERISTICS (VPWR = 3.3 V ± 0.3 V; TJ = −40°C to + 105°C; Output Load = 10pF) falling edge and the data output transition is typically 7 ns. approximately the same time as the data output transitions. See Table 16 for data setup and hold times. Figure 38. Propagation Delays for PIXCLK and Data Out Signals
Table 20. TWO−WIRE SERIAL BUS CHARACTERISTICS (VPWR = 3.3V +0.3V; TA = Ambient = 25°C)
- This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
- Two -wire control is I2C-compatible.
- A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
12.The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. I2C−bus specification) before the SCLK line is released. 14.Cb = total capacitance of one bus line in pF. certain minimum master clock cycles between transitions.
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