MT9P401I12STC-DP

MT9P401_17 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

• High Frame Rate
• Superior Low−light Performance
• Low Dark Current
• Global Reset Release, which Starts the Exposure of all Rows Simultaneously
• Bulb Exposure Mode, for Arbitrary Exposure Times
• Snapshot Mode to Take Frames on Demand
• Horizontal and Vertical Mirror Image
• Column and Row Skip Modes to Reduce Image Size without Reducing Field−of−view (FOV)
• Column and Row Binning Modes to Improve Image Quality when Resizing www.onsemi.com See detailed ordering and shipping information on page 2 of this data sheet.

ORDERING INFORMATION

Features (continued)

• Simple Two−wire Serial Interface
• Programmable Controls: Gain, Frame Rate, Frame Size, Exposure
• Automatic Black Level Calibration
• On−chip Phase−locked Loop (PLL)
• 720p HDTV Video at 60 fps

Applications

• Digital Still Cameras
• Digital Video Cameras
• PC Cameras
• Converged DSCs/camcorders
• Cellular Phones
• PDAs

CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com Table 2. AVAILABLE PART NUMBERS programmable through a simple two−wire serial interface. full resolution image at 15 frames per second (fps). clock that is synchronous with valid data. a block diagram of the sensor. Figure 1. Block Diagram

96 Mp/s, in addition to frame and line synchronization

Table 3. PIN DESCRIPTION OE Input When HIGH, the PIXCLK, DOUT, FV, LV, and STROBE outputs enter a High−Z.

after binning, as shown in the Table 6. DR is included in the vertical blank period. Table 6. DARK ROWS SAMPLED AS A FUNCTION set of columns read is shown in Table 7. bin, skip, and column mirror settings are read out. Table 7. DARK COLUMNS SAMPLED AS

Figure 10. Frame Timing defined by equations in Table 8. Table 8. FRAME TIME

Table 9. HBMIN VALUES FOR ROW_BIN VS. COLUMN_BIN SETTINGS Table 10. STANDARD RESOLUTIONS

14 N/A 2591 1943 <1943 0 0 0 0

63 Skipping 2047 1535 0 1 0 1

47 Binning 2047 1535 1 1 1 1

90 Skipping 1599 1199 0 1 0 1

65 Binning 1599 1199 1 1 1 1

123 Skipping 2559 1919 0 3 0 3

53 Binning 2559 1919 3 3 3 3

Table 11. WIDE SCREEN (16:9) RESOLUTIONS

1. It is assumed that the minimum horizontal blanking and the minimum vertical blanking conditions are met, and that all other r egisters are

set to default values. Please refer to TN09111 for instructions on how to configure 720p HDTV.

CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com SERIAL BUS DESCRIPTION Registers are written to and read from the MT9P401 through the two−wire serial interface bus. The MT9P401 is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out of the MT9P401 through the serial data (S DATA) line. The S DATA line is pulled up to V DD_IO off−chip by a 1.5 kΩ resistor. Either the slave or master device can pull the S DATA line LOW—the serial interface protocol determines which device is allowed to pull the S DATA line down at any given time. Protocol The two-wire serial defines several different transmission codes, as follows: 1. a start bit 2. the slave device 8-bit address 3. an (a no) acknowledge bit 4. an 8-bit message 5. a stop bit Sequence A typical READ or WRITE sequence begins by the master sending a start bit. After the start bit, the master sends the slave device’s 8−bit address. The last bit of the address determines if the request is a READ or a WRITE, where a “0” indicates a WRITE and a “1” indicates a READ. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request is a WRITE, the master then transfers the 8−bit register address to which a WRITE should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9P401 uses 16−bit data for its internal registers, thus requiring two 8 −bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical READ sequence is executed as follows. First the master sends the write −mode slave address and 8 −bit register address, just as in the WRITE request. The master then sends a start bit and the read−mode slave address. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8 −bit transfer. The register address is automatically −incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no−acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH−to−LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW−to−HIGH transition of the data line while the clock line is HIGH. Slave Address The 8−bit address of a two −wire serial interface device consists of 7 bits of address and 1 bit of direction. A “0” in the LSB (least significant bit) of the address indicates write mode (0xBA), and a “1” indicates read mode (0xBB). Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two−wire serial interface clock −it can only change when the serial clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no−acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no −acknowledge bit is used to terminate a read sequence.

Table 12 lists sensor registers and their default values. Table 12. REGISTER LIST AND DEFAULT VALUES

Table 12. REGISTER LIST AND DEFAULT VALUES (continued)

Table 13 lists sensor register descriptions. Table 13. REGISTER DESCRIPTION will be used. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. The width of the field of view minus one. If this register is set to an even value, the next higher odd value will be used.

Table 13. REGISTER DESCRIPTION (continued)

15 X Reserved

13 X Reserved

When set, pixels will be sent through the output FIFO before being sent off chip. draws minimal power. When set, the chip operates according to the current mode. until the bit is clear. When cleared, all the delayed writes will happen immediately. When set, LV, FV, and D_OUT should be captured on the rising edge of PIXCLK. relative to DOUT (and thus relative to the internal array/datapath clock).

7 X Reserved

mode. The sense of this bit is NOT affected by Invert Trigger.

When set, produce a LV signal that is the XOR of FV and the normal line_valid. When set, the STROBE signal will be active LOW (during exposure). When set, a strobe signal will be generated by the digital logic during integration.

Determines the timepoint when the strobe is asserted. than Strobe_Start, the width of the strobe pulse will be t_ROW. See Strobe_Start.

11 X Reserved

be 1; for Bin 4X, it should be 3. Writes are synchronized to frame boundaries.

3 X Reserved

Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. The number of columns to be read and averaged per column output minus one.

increments of 1/8. Writes are synchronized to frame boundaries. (Red_Analog_Gain/8)). Writes are synchronized to frame boundaries. crements of 1/8. Writes are synchronized to frame boundaries. (Green2_Analog_Gain/8)). Writes are synchronized to frame boundaries. Writing the Global_Gain sets all four individual gain registers R43−R46 to the value. This register should not be read.

CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com The MT9P401 may be reset by using RESET_BAR (active LOW) or the reset register. Hard Reset Assert (LOW) RESET_BAR, it is not necessary to clock the device. All registers return to the factory defaults. When the pin is negated (HIGH), the chip resumes normal operation. Soft Reset Set the Reset register field to “1” (R0x0D[0] = 1). All registers except the following will be reset:

• Chip_Enable
• Synchronize_Changes
• Reset
• Use_PLL
• Power_PLL
• PLL_m_Factor
• PLL_n_Divider
• PLL_p1_Divider When the field is returned to “0”, the chip resumes normal operation. Power Up and Power Down When first powering on the MT9P401, follow this sequence: 1. Ensure RESET_BAR is asserted (LOW) 2. Bring up the supplies. If both the analog and the digital supplies cannot be brought up simultaneously, ensure the digital supply comes up first 3. Negate RESET_BAR (HIGH) to bring up the sensor When powering down, be sure to follow this sequence to ensure that I/Os do not load any buses that they are connected to. 1. Assert RESET_BAR 2. Remove the supplies Clocks The MT9P401 requires one clock (EXTCLK), which is nominally 96 MHz. By default, this results in pixels being output on the D OUT pins at a maximum data rate of 96 Mp/s. With V DD_IO = 1.8 V , maximum master clock and maximum data rate become 48 MHz and 48 Mp/s, respectively. The EXTCLK clock can be divided down internally by setting Divide_Pixel_Clock to a non −zero value. This slows down the operation of the chip as though EXTCLK had been divided externally. fEXTCLK if Divide_Pixel_Clock = 0 fPIXCLK= { fEXTCLK / (2 × Divide_Pixel_Clock) otherwise The DOUT, LV , FV , and STROBE outputs are launched on the rising edge of PIXCLK, and should be captured on the falling edge of PIXCLK. The specific relationship of PIXCLK to these other outputs can be adjusted in two ways. If Invert_Pixel_Clock is set, the sense of PIXCLK is inverted from that shown in Figure 8. In addition, if the pixel clock has been divided by Divide_Pixel_Clock, it can be shifted relative to the other outputs by setting Shift_Pixel_Clock. PLL-Generated Master Clock The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler output, and another divider stage to generate the output clock. The clocking structure is shown in Figure 13. PLL control registers can be programmed to generate desired master clock frequency. NOTE: The PLL control registers must be programmed while the sensor is in the software Standby state. The effect of programming the PLL divisors while the sensor is in the streaming state is undefined.

Figure 13. PLL-Generated Master Clock

CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com PLL Setup The MT9P401 has a PLL which can be used to generate the pixel clock internally. To use the PLL: 1. Bring the MT9P401 up as normal, make sure that fEXTCLK is between 6 and 27 MHz and then power on the PLL by setting Power_PLL (R0x10[0] = 1) 2. Set PLL_m_Factor, PLL_n_Divider, and PLL_p1_Divider based on the desired input fEXTCLK) and output (fPIXCLK) frequencies. Determine the M, N, and P1 values to achieve the desired fPIXCLK using this formula: fPIXCLK = (fEXTCLK × M) / (N × P1) where M = PLL_m_Factor N = PLL_n_Divider + 1 P1 = PLL_p1_Divider + 1 NOTE: If P1 is odd (that is, PLL_p1_Divider is even), the duty cycle of the internal system clock will not be 50:50. In this case, it is important that either a slower clock is used or all clock enable bits are set in R101.

2 MHz <

fEXTCLK / N < 13.5 MHz

180 MHz < (fEXTCLK × M) / N < 360 MHz

It is desirable to keep (fEXTCLK / n) as large as possible within the limits. Also, “m” must be between 16 and 255, inclusive. 3. Wait 1ms to ensure that the VCO has locked 4. Set Use_PLL (R0x10[1] = 1) to switch from EXTCLK to the PLL−generated clock Standby and Chip Enable The MT9P401 can be put in a low−power Standby state by either method below: 1. Hard Standby: By pulling STANDBY_BAR LOW, or 2. Soft Standby: By clearing the Chip_Enable register field (R0x07[1] = 0) When the sensor is put in standby, all internal clocks are gated, and analog circuitry is put in a state that it draws minimal power. The two −wire serial interface remains minimally active so that the Chip_Enable bit can subsequently be cleared. Reads cannot be performed and only the Chip_Enable and Invert_Standby registers are writable. If the sensor was in continuous mode when put in standby, it resumes from where it was when standby was deactivated. Naturally, this frame and the next frame are corrupted, though the sensor itself does not realize this. As this could affect automatic black level calibration, it is recommended that either the chip be paused (by setting Restart_Pause) before being put in standby mode, or it be restarted (setting Restart) upon resumption of operation. For maximum power savings in standby mode, EXTCLK should not be toggling. When standby mode is entered, either by clearing Chip_Enable or by asserting STANDBY_BAR, the PLL is disabled automatically or powered down. It must be manually re−enabled when leaving standby as needed. Full-Array Readout The entire array, including dark pixels, can be read out without digital processing or automatic black level adjustments. This can be accomplished as follows: 1. Set Row_Start and Column_Start to 0 2. Set Row_Size to 2003 3. Set Column_Size to 2751 4. Set Manual_BLC to 1 5. Set Row_BLC to 0 6. Set Row_Black_Default_Offset to 0 7. Set Show_Dark_Rows and Show_Dark_Columns to 0 If automatic analog (coarse) BLC is desired, but no digital processing, modify the above settings as follows: 1. Set Row_Start to 12 2. Set Row_Size to 1993 3. Set Manual_BLC to 0 These settings result in the same array layout as above, but only 22 dark rows are available at the top of the array; the first eight are used in the black level algorithm, and there should be a two−row buffer between the black region and the active region. Window Control The output image window of the pixel (the FOV) is defined by four register fields. Column_Start and Row_Start define the X and Y coordinates of the upper−left corner of the FOV . Column_Size defines the width of the FOV , and Row_Size defines the height of the FOV in array pixels. The Column_Start and Row_Start fields must be set to an even number. The Column_Size and Row_Size fields must be set to odd numbers (resulting in an even size for the FOV). The Row_Start register should be set no lower than 12 if either Manual_BLC is clear or Show_Dark_Rows is set. If no special resolution modes are set (see below), the width of the output image, W, is Column_Size + 1) and the height, H, is (Row_Size + 1). Readout Modes Subsampling By default, the resolution of the output image is the full width and height of the FOV as defined in “Window Control”. The output resolution can be reduced by two methods: Skipping and Binning. Row and column skip modes use subsampling to reduce the output resolution without reducing FOV . The MT9P401 also has row and column binning modes, which can reduce the impact of aliasing introduced by the use of skip modes.

CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com the first output row in bin 2x + row mirror was 1997, pixels on rows 1997 and 1999 would be averaged together. The next pixel output would be from rows 1996 and 1998, followed by the average of 1993 and 1995. For column mirroring plus binning, the span of pixels used should be the same as with non−mirror mode. Maintaining a Constant Frame Rate Maintaining a constant frame rate while continuing to have the ability to adjust certain parameters is the desired scenario. This is not always possible, however, because register updates are synchronized to the read pointer, and the shutter pointer for a frame is usually active during the readout of the previous frame. Therefore, any register changes that could affect the row time or the set of rows sampled causes the shutter pointer to start over at the beginning of the next frame. By default, the following register fields cause a “bubble” in the output rate (that is, the vertical blank increases for one frame) if they are written in continuous mode, even if the new value would not change the resulting frame rate:

• Row_Start
• Row_Size
• Column_Size
• Horizontal_Blank
• Vertical_Blank
• Shutter_Delay
• Mirror_Row
• Row_Bin
• Row_Skip
• Column_Skip The size of this bubble is (SW × tROW), calculating the row time according to the new settings. The Shutter_Width_Lower and Shutter_Width_Upper fields may be written without causing a bubble in the output rate under certain circumstances. Because the shutter sequence for the next frame often is active during the output of the current frame, this would not be possible without special provisions in the hardware. Writes to these registers take effect two frames after the frame they are written, which allows the shutter width to increase without interrupting the output or producing a corrupt frame (as long as the change in shutter width does not affect the frame time). Synchronizing Register Writes to Frame Boundaries Changes to most register fields that affect the size or brightness of an image take effect on the frame after the one during which they are written. These fields are noted as “synchronized to frame boundaries” in Table 12: Register List and Default Values. To ensure that a register update takes effect on the next frame, the write operation must be completed after the leading edge of FV and before the trailing edge of FV . As a special case, in Snapshot modes (see “Operating Modes”), register writes that occur after FV but before the next trigger will take effect immediately on the next frame, as if there had been a Restart. However, if the trigger for the next frame in ERS Snapshot mode occurs during FV, register writes take effect as with continuous mode. Additional control over the timing of register updates can be achieved by using synchronize_changes. If this bit is set, writes to certain register fields that affect the brightness of the output image do not take effect immediately. Instead, the new value is remembered internally. When synchronize_changes is cleared, all the updates simultaneously take effect on the next frame (as if they had all been written the instant synchronize_changes was cleared). Register fields affected by this bit are identified in Table 13: Register Description. Fields not identified as being frame −synchronized or affected by synchronize_changes are updated immediately after the register write is completed. The effect of these registers on the next frame can be difficult to predict if they affect the shutter pointer. Restart To restart the MT9P401 at any time during the operation of the sensor, write a “1” to the restart register (R0x0B[0] = 1). This has two effects: first, the current frame is interrupted immediately. Second, any writes to frame −synchronized registers and the shutter width registers take effect immediately, and a new frame starts (in continuous mode). Register updates being held by synchronize_changes do not take effect until that bit is cleared. The current row and one following row complete before the new frame is started, so the time between issuing the Restart and the beginning of the next frame can vary by about tROW. If Pause_Restart is set, rather than immediately beginning the next frame after a restart in continuous mode, the sensor pauses at the beginning of the next frame until Pause_Restart is cleared. This can be used to achieve a deterministic time period from clearing the Pause_Restart bit to the beginning of the first frame, meaning that the controller does not need to be tightly synchronized to LV or FV . NOTE: When Pause_Restart is cleared, be sure to leave Restart set to “1” for proper operation. The Restart bit will be cleared automatically by the device. Image Acquisition Modes Electronic Rolling Shutter The ERS modes take pictures by scanning the rows of the sensor twice in the order described in “Full−Array Readout”. On the first scan, each row is released from reset, starting the exposure. On the second scan, the row is sampled, processed, and returned to the reset state. The exposure for any row is therefore the time between the first and second

exposure of all rows simultaneously. than tALLRESET after the previous frame is read out. offset will increase by the length of the shutter sequence. (and thus Shutter_Delay) has no effect. or it can be controlled using the external TRIGGER signal. The various operating modes are summarized in Table 15. Table 15. OPERATING MODE ERS Continuous Default Frames are output continuously at the frame rate defined by tFRAME. ERS Snapshot Snapshot = 1 Frames are output one at a time, with each frame initiated by a trigger. Frames are output one at a time, with each frame’s exposure initiated by a trigger. Frames are output one at a time, with each frame initiated by a trigger. Frames are output one at a time, with each frame initiated by a trigger.

1. In ERS bulb mode, SW must be greater than 4 (use trigger wider than tROW x 4).

Figure 24. GRR Snapshot Timing Table 16. STROBE TIMEPOINTS

1. To use strobe as a flash in snapshot modes or with

The signal chain and datapath are shown in Figure 25.

12−bit pixel value is then output on the DOUT[11:0] ports. Figure 25. Signal path Table 17. GAIN INCREMENT SETTINGS

1. Analog gain should be maximized before applying digital gain

The combined gain for a color C is given by: GC = AGC x DGC. image data in a number of ways.

applied instead. This offset has a resolution of 1 LSB. level falls within the specified target thresholds.

1. If necessary, adjust the analog offset

different sample or adjustment methods at the same time. Red_Offset is used for both the red and blue channels. sampling or adjusting takes place for any color. active columns for all rows, including dark rows. Table 18. TEST PATTERN MODES

0 Color field (normal operation)

1 Horizontal gradient

2 Vertical gradient

3 Diagonal gradient

4 Classic test pattern

5 Walking 1s

6 Monochrome horizontal bars

7 Monochrome vertical bars

8 Vertical color bars

through the digital pipeline. based on a counter which increments on every active pixel. on a counter which increments on every active row.

CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com Diagonal Gradient When selected, a diagonal gradient will be produced based on the counter used by the horizontal and vertical gradients. Walking 1s When selected, a walking 1s pattern will be sent through the digital pipeline. The first value in each row is 1. Monochrome Vertical Bars When selected, vertical monochrome bars will be sent through the digital pipeline. The width of each bar can be set in Test_Pattern_Bar_Width and the intensity of each bar is set by Test_Pattern_Green for even bars and Test_Pattern_Blue for odd bars. Monochrome Horizontal Bars When selected, horizontal monochrome bars will be sent through the digital pipeline. The width of each bar can be set in Test_Pattern_Bar_Width and the intensity of each bar is set by Test_Pattern_Green for even bars and Test_Pattern_Blue for odd bars.

Figure 28. Two-Wire Serial Bus Timing Parameters NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 19. TWO-WIRE SERIAL BUS CHARACTERISTICS

Figure 29. I/O Timing Diagram Table 20. I/O TIMING CHARACTERISTICS

The DC electrical characteristics are shown in Table 21. Table 21. DC ELECTRICAL CHARACTERISTICS performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Table 22. POWER CONSUMPTION Table 23. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.

1. Exposure to absolute maximum rating conditions for extended periods may affect reliability
2. To keep dark current and shot noise artifacts from impacting image quality, care should be taken to keep TOP at a minimum

CONFIDENTIAL AND PROPRIETARY NOT FOR PUBLIC RELEASE www.onsemi.com ILCC48 10x10 CASE 847AA ISSUE O 4.50 10.000 ±0.075 3.85 7.70 3.85 0.70 TYP 0.70 TYP 7.70 481 1.4047X 0.80 48X 0.40 4.50 10.000 ±0.075C L C L LEAD FINISH: GOLD PLATING,

0.50 MICRONS

4.20 SEATING PLANE IMAGE SENSOR DIE LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS 1.250 ±0.125 0.725 ±0.075 0.525 ±0.050 0.125 (FOR REFERENCE ONLY) A D 7.571.455 5.702 CTR 7.024.277 CTR 1.45 5.000 ±0.075 OPTICAL CENTER C B OPTICAL AREA MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES B AND C : 1º MAXIMUM TILT OF OPTICAL AREA RELATIVE TO SEATING PLANE A : 25 MICRONS RELATIVE TO TOP OF COVER GLASS D : 50 MICRONS ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ 5.000 ±0.075 OPTICAL CENTER FIRST CLEAR PIXEL NOTE: All dimensions in millimeters SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC

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