MT9M034_17 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Superior Low−light performance
- HD Video (720p60)
- Linear or High Dynamic Range Capture
- Video/Single Frame Modes
- On−chip AE and Statistics Engine
- Parallel and Serial Output
- Auto Black Level Calibration
- Context Switching
- Temperature Sensor www.onsemi.com See detailed ordering and shipping information on page 2 of this data sheet.
ORDERING INFORMATION
Applications
- Video Surveillance
- 720p60 Video Applications
- High Dynamic Range Imaging
www.onsemi.com Table 2. AVAILABLE PART NUMBERS control, windowing, and both video and single frame modes. or in single frame trigger mode. be embedded in first and last 2 lines of the image frame. a block diagram of the sensor. Figure 1. Block Diagram
on−chip to produce a single image at 20−bit per pixel value. and line synchronization signals. Figure 2. Typical Configuration: Parallel Pixel Data Interface
- All power supplies should be adequately decoupled.
- ON Semiconductor recommends a resistor value of 1.5 kΩ, but a greater value may be used for slower two-wire speed.
- The serial interface output pads and V DDSLVS can be left unconnected if the parallel output interface is used.
- ON Semiconductor recommends that 0.1 μF and 10 μF decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Check the demo headboard schematics for circuit recommendations.
- ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
- I/O signals voltage must be configured to match V
DD_IO voltage to minimize any leakage currents.
- The serial interface output pads and VDDSLVS can be left unconnected if the parallel output interface is used.
Figure 3. 48 iLCC Package, Parallel Output
Table 3. PIN DESCRIPTION
1 DOUT4 Output Parallel pixel data output
2 DOUT5 Output Parallel pixel data output
3 DOUT6 Output Parallel pixel data output
4 VDD_PLL Power PLL power
5 EXTCLK Input External input clock
6 DGND Power Digital ground
7 DOUT7 Output Parallel pixel data output
8 DOUT8 Output Parallel pixel data output
9 DOUT9 Output Parallel pixel data output
10 DOUT10 Output Parallel pixel data output
11 DOUT11 Output Parallel pixel data output (MSB)
12 VDD_IO Power I/O supply power
14 VDD Power Digital power
15 SCLK Input Two−Wire Serial clock input
16 SDATA I/O Two−Wire Serial data I/O
18 VDD_IO Power I/O supply power
19 VDD Power Digital power
22 STANDBY Input Standby−mode enable pin (active HIGH)
23 OE_BAR Input Output enable (active LOW)
24 SADDR Input Two−Wire Serial address select
25 TEST Input Manufacturing test enable pin (connect to DGND)
26 FLASH Output Flash output control
27 TRIGGER Input Exposure synchronization input
28 FRAME_VALID Output Asserted when DOUT frame data is valid
29 LINE_VALID Output Asserted when DOUT line data is valid
30 DGND Power Digital ground
31 Reserved NC
32 Reserved NC
33 Reserved NC
34 VAA Power Analog power
35 AGND Power Analog ground
36 VAA Power Analog power
37 VAA_PIX Power Pixel power
38 VAA_PIX Power Pixel power
39 AGND Power Analog ground
Table 3. PIN DESCRIPTION (continued)
40 VAA Power Analog power
44 DGND Power Digital ground
45 DOUT0 Output Parallel pixel data output (LSB)
46 DOUT1 Output Parallel pixel data output
47 DOUT2 Output Parallel pixel data output
48 DOUT3 Output Parallel pixel data output
dummy pixels or barrier pixels can be read out. Figure 4. Pixel Array Description
row time (in clocks) is programmable through R0x300C. Figure 7. Spatial Illustration of Image Readout
Table 6. FRAME TIME: LONG INTEGRATION TIME
- The MT9M034 uses column parallel analog −digital converters; thus short line timing is not possible. The minimum total line time is 1650
columns (horizontal width + horizontal blanking) for HDR mode and 1400 for linear mode. The minimum horizontal blanking is 370. refer to the Register Reference document. called “HDR Specific Exposure Settings”. mode, this would be the coarse integration time (R0x3012). time to 1 row may result in non−uniformity between rows.
Figure 11. HDR Data Compression below show the knee points for the different modes.
Table 7. KNEE POINTS FOR COMPRESSION TO 14 BITS Table 8. KNEE POINTS FOR COMPRESSION TO 12 BITS coarse integration time possible is equal to 42 × T1 / T2 lines. integration lines is 42 × 16 = 672 lines. ratio internally,enabling the linearization to be performed. exposure lines in relation to the frame_length_lines register. coarse_integration time is frame_length_lines − 45.
(R0x3082[5:4]) may not be achievable. Table 9. DIGITAL GAIN SETTING FOR EACH T1 / T2 AND T2 / T3 RATIO potentially be visible and might look like a ghosting effect. and corrects the image accordingly. There are two motion compensation options available.
Table 10. REAL−TIME CONTEXT−SWITCH REGISTERS
www.onsemi.com See the MT9M034 Register Reference for additional details. Reset The MT9M034 may be reset by using RESET_BAR (active LOW) or the reset register. Hard Reset of Logic The RESET_BAR pin can be connected to an external RC circuit for simplicity. The recommended RC circuit uses a 10 kΩ resistor and a 0.1 μF capacitor. The rise time for the RC circuit is 1 μs maximum. Soft Reset of Logic Soft reset of logic is controlled by the R0x301A Reset register. Bit 0 is used to reset the digital logic of the sensor while preserving the existing two −wire serial interface configuration. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. This bit is a self−resetting bit and also returns to “0” during two−wire serial interface reads. Clocks The MT9M034 requires one clock input (EXTCLK). PLL−Generated Master Clock The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler output, and two divider stages to generate the output clock. The clocking structure is shown in Figure 12. PLL control registers can be programmed to generate desired master clock frequency. NOTE: The PLL control registers must be programmed while the sensor is in the software Standby state. The effect of programming the PLL divisors while the sensor is in the streaming state is undefined. Figure 12. PLL−Generated Master Clock PLL Setup
- Bring the MT9M034 up as normal; make sure that
- Set pll_multiplier, pre_pll_clk_div, vt_sys_clk_siv,
EXTCLK) and output (fPIXCLK) frequencies.
- Wait 1 ms to ensure that the VCO has locked.
- Set R0x301A[2] = 1 to enable streaming and to
- The PLL can be bypassed at any time (sensor will
- The following restrictions apply to the PLL tuning
- The VCO frequency, defined as f
M / N must be within 384−768 MHz.
- When PLL_Multiplier is odd, 2 MHz <= fEXTCLK
supplied input clock and desired output frequency.
www.onsemi.com Spread−Spectrum Clocking To facilitate improved EMI performance, the external clock input allows for spread spectrum sources, with no impact on image quality. Limits of the spread spectrum input clock are:
- 5% maximum clock modulation
- 35 KHz maximum modulation frequency
- Accepts triangle wave modulation, as well as sine or modified triangle modulations. Stream/Standby Control The sensor supports two standby modes: Hard Standby and Soft Standby. In both modes, external clock can be optionally disabled to further minimize power consumption. If this is done, then the “Power −Up Sequence” must be followed. Soft Standby Soft Standby is a low power state that is controlled through register R0x301A[2]. Depending on the value of R0x301A[4], the sensor will go to standby after completion of the current frame readout (default behavior) or after the completion of the current row readout. When the sensor comes back from Soft Standby, previously written register settings are still maintained. Soft standby will not occur if the TRIGGER pin is held high. A specific sequence needs to be followed to enter and exit from Soft Standby. Entering Soft Standby: 1. Set R0x301A[2] = 0 and drive the TRIGGER pin LOW 2. External clock can be turned off to further minimize power consumption (Optional) Exiting Soft Standby: 1. Enable external clock if it was turned off 2. R0x301A[2] = 1 or drive the TRIGGER pin HIGH Hard Standby Hard Standby puts the sensor in lower power state; previously written register settings are still maintained. A specific sequence needs to be followed to enter and exit from Hard Standby. Entering Hard Standby: 1. R0x301A[8] = 1 2. Assert STANDBY pin 3. External clock can be turned off to further minimize power consumption (Optional) Exiting Hard Standby: 1. Enable external clock if it was turned off 2. De−assert STANDBY pin 3. Set R0x301A[8] = 0 Window Control Registers x_addr_start, x_addr_end, y_addr_start, and y_addr_end control the size and starting coordinates of the image window. The exact window height and width out of the sensor is determined by the difference between the Y address start and end registers or the X address start and end registers, respectively. The MT9M034 allows different window sizes for context A and context B. Blanking Control Horizontal blank and vertical blank times are controlled by the line_length_pck and frame_length_lines registers, respectively.
- Horizontal blanking is specified in terms of pixel clocks. It is calculated by subtracting the X window size from the line_length_pck register. The minimum horizontal blanking is 370 pixel clocks.
- Vertical blanking is specified in terms of numbers of lines. It is calculated by subtracting the Y window size from the frame_length_lines register. The minimum vertical blanking is 26 lines. The actual imager timing can be calculated using Table 5 and Table 6, which describe the Line Timing and FV/LV signals. When in HDR mode, the maximum size is 1280 × 960. Readout Modes Digital Binning By default, the resolution of the output image is the full width and height of the FOV as defined above. The output resolution can be reduced by digital binning. For RGB and monochrome mode, this is set by the register R0x3032. For Context A, use bits [1:0], for Context B, use bits [5:4]. Available settings are: 00 = No binning 01 = Horizontal binning 10 = Horizontal and vertical binning Binning gives the advantage of reducing noise at the cost of reduced resolution. When both horizontal and vertical binning are used, a 2x improvement in SNR is achieved, therefore improving low light performance. Binning results in a smaller resolution image, but the FOVs between the binned and unbinned images are the same. Bayer Space Resampling All of the pixels in the FOV contribute to the output image in digital binning mode. This can result in a more pleasing output image with reduced subsampling artifacts. It also improves low −light performance. For RGB mode, resampling can be enabled by setting of register 0x306E[4] = 1.
www.onsemi.com Synchronizing Register Writes to Frame Boundaries Changes to most register fields that affect the size or brightness of an image take effect on two frames after the one during which they are written. These fields are noted as “synchronized to frame boundaries” in the MT9M034 Register Reference. To ensure that a register update takes effect on the next frame, the write operation must be completed after the leading edge of FV and before the trailing edge of FV . Fields not identified as being frame −synchronized are updated immediately after the register write is completed. The effect of these registers on the next frame can be difficult to predict if they affect the shutter pointer. Restart To restart the MT9M034 at any time during the operation of the sensor, write a “1” to the Restart register (R0x301A[1] = 1). This has two effects: first, the current frame is interrupted immediately. Second, any writes to frame−synchronized registers and the shutter width registers take effect immediately, and a new frame starts (in video mode). The current row completes before the new frame is started, so the time between issuing the Restart and the beginning of the next frame can vary by about t ROW. Image Acquisition Modes The MT9M034 supports two image acquisition modes: video(master) and single frame. Video The video mode takes pictures by scanning the rows of the sensor twice. On the first scan, each row is released from reset, starting the exposure. On the second scan, the row is sampled, processed, and returned to the reset state. The exposure for any row is therefore the time between the first and second scans. Each row is exposed for the same duration, but at slightly different point in time, which can cause a shear in moving subjects as is typical with electronic rolling shutter sensors. Single Frame The single −frame mode operates similar to the video mode. It also scans the rows of the sensor twice, first to reset the rows and second to read the rows. Unlike video mode where a continuous stream of images are output from the image sensor, the single−frame mode outputs a single frame in response to a high state placed on the TRIGGER input pin. As long as the TRIGGER pin is held in a high state, new images will be read out. After the TRIGGER pin is returned to a low state, the image sensor will not output any new images and will wait for the next high state on the TRIGGER pin. The TRIGGER pin state is detected during the vertical blanking period (i.e. the FV signal is low). The pin is level sensitive rather than edge sensitive. As such, image integration will only begin when the sensor detects that the TRIGGER pin has been held high for 3 consecutive clock cycles. If the trigger signal is applied to multiple sensors at the same time, the single frame output of the sensors will be synchronized to within 1 PIXCLK if is PLL disabled or 2 PIXCLKs if PLL is enabled. During integration time of single−frame mode and video mode, the FLASH output pin is at high. Continuous Trigger In certain applications, multiple sensors need to have their video streams synchronized (E.g. surround view or panorama view applications). The TRIGGER pin can also be used to synchronize output of multiple image sensors together and still get a video stream. This is called continuous trigger mode. Continuous trigger is enabled by holding the TRIGGER pin high. Alternatively, the TRIGGER pin can be held high until the stream bit is enabled (R0x301A[2] = 1) then can be released for continuous synchronized video streaming. If the TRIGGER pins for all connected MT9M034 sensors are connected to the same control signal, all sensors will receive the trigger pulse at the same time. If they are configured to have the same frame timing, then the usage of the TRIGGER pin guarantees that all sensors will be synchronized within 1 PIXCLK cycle if PLL is disabled, or 2 PIXCLK cycles if PLL is enabled. With continuous trigger mode, the application can now make use of the video streaming mode while guaranteeing that all sensor outputs are synchronized. As long as the initial trigger for the sensors takes place at the same time, all subsequent video streams will be synchronous. Temperature Sensor The MT9M034 sensor has a built −in PTAT −based temperature sensor, accessible through registers, that is capable of measuring die junction temperature. The temperature sensor can be enabled by writing R0x30B4[0] = 1 and R0x30B4[4] = 1. After this, the temperature sensor output value can be read from R0x30B2[10:0]. The value read out from the temperature sensor register is an ADC output value that needs to be converted downstream to a final temperature value in degrees Celsius. Since the PTAT device characteristic response is quite linear in the temperature range of operation required, a simple linear function in the format of listed in the equation below can be used to convert the ADC output value to the final temperature in degrees Celsius. Temperature /C0043slope /C0032R0x30B2[10 : 0] /C0041T0 (eq. 5) For this conversion, a minimum of 2 known points are needed to construct the line formula by identifying the slope and y−intercept “T0”. These calibration values can be read from registers R0x30C6 and R0x30C8 which correspond to value read at 70 °C and 55 °C respectively. Once read, the slope and y−intercept values can be calculated and used in the above equation.
refer to the MT9M034 Register Reference. can be enabled or disabled by R0x3100[0]. registers and the manual gain value in the gain registers.
- Embedded Data: If enabled, these are displayed on
- Embedded Statistics: If enabled, these are
enabled or disabled together. Figure 15. Frame Format with Embedded Data Lines Enabled NOTE: All non −defined registers will have a value of 0. bit data aligned to the MSB of the 12−bit pixel.
www.onsemi.com The statistics embedded in these rows are as follows: Line 1:
- 0x0B0 − (identifier)
- Register 0x303A − frame_count
- Register 0x31D2 − frame ID
- Histogram data − histogram bins 0−243 Line 2:
- 0x0B0 (identifier)
- Mean
- Histogram Begin
- Histogram End
- Low End Histogram Mean
- Percentage of Pixels Below Low End Mean
- Normal Absolute Deviation Gain Digital Gain Digital gain can be controlled globally by R0x305E (Context A) or R0x30C4 (Context B). There are also registers that allow individual control over each Bayer color (GreenR, GreenB, Red, Blue). The format for digital gain setting is xxx.yyyyy where 0b00100000 represents a 1x gain setting and 0b00110000 represents a 1.5x gain setting. The step size for yyyyy is 0.03125 while the step size for xxx is 1. Therefore to set a gain of 2.09375 one would set digital gain to 01000011. Analog Gain The MT9M034 has a column parallel architecture and therefore has an Analog gain stage per column. There are 2 stages of analog gain, the first stage can be set to 1x, 2x, 4x or 8x. This can be set in R0x30B0[5:4] (Context A) or R0x30B0[9:8] (Context B). The second stage is capable of setting an additional 1x or 1.25x gain which can be set in R0x3EE4[9:8]. This allows the maximum possible analog gain to be set to 10x. Black Level Correction Black level correction is handled automatically by the image sensor. No adjustments are provided except to enable or disable this feature. Setting R0x30EA[15] disables the automatic black level correction. Default setting is for automatic black level calibration to be enabled. The automatic black level correction measures the average value of pixels from a set of optically black lines in the image sensor. The pixels are averaged as if they were light−sensitive and passed through the appropriate gain. This line average is then digitally low −pass filtered over many frames to remove temporal noise and random instabilities associated with this measurement. The new filtered average is then compared to a minimum acceptable level, low threshold, and a maximum acceptable level, high threshold. If the average is lower than the minimum acceptable level, the offset correction value is increased by a predetermined amount. If it is above the maximum level, the offset correction value is decreased by a predetermined amount. The high and low thresholds have been calculated to avoid oscillation of the black level from below to above the targeted black level. Row−wise Noise Correction Row (Line) −wise Noise Correction is handled automatically by the image sensor. No adjustments are provided except to enable or disable this feature. Clearing R0x3044[10] disables the row noise correction. Default setting is for row noise correction to be enabled. Row−wise noise correction is performed by calculating an average from a set of optically black pixels at the start of each line and then applying each average to all the active pixels of the line. Column Correction The MT9M034 uses column parallel readout architecture to achieve fast frame rate. Without any corrections, the consequence of this architecture is that different column signal paths have slightly different offsets that might show up on the final image as structured fixed pattern noise. MT9M034 has column correction circuitry that measures this offset and removes it from the image before output. This is done by sampling dark rows containing tied pixels and measuring an offset coefficient per column to be corrected later in the signal path. Column correction can be enabled/disabled via R0x30D4[15]. Additionally, the number of rows used for this offset coefficient measurement is set in R0x30D4[3:0]. By default this register is set to 0x7, which means that 8 rows are used. This is the recommended value. Other control features regarding column correction can be viewed in the MT9M034 Register reference. Any changes to column correction settings need to be done when the sensor streaming is disabled and the appropriate triggering sequence must be followed as described below. Column Correction Triggering Column correction requires a special procedure to trigger depending on which state the sensor is in. Column Triggering on Startup When streaming the sensor for the first time after powerup, a special sequence needs to be followed to make sure that the column correction coefficients are internally calculated properly. 1. Follow proper power up sequence for power supplies and clocks 2. Apply sequencer settings if needed (Linear or HDR mode) 3. Apply frame timing and PLL settings as required by application
- Set analog gain to 1x and low conversion gain
- Enable column correction and settings
- Disable auto re−trigger for change in conversion
- Enable streaming (R0x301A[2] = 1) or drive the
- Wait 9 frames to settle (First frame after coming
- Disable streaming (R0x301A[2] = 0)
correction coefficients and the sensor is ready for streaming. affecting column correction. mirror, changes to column correction settings.
- Disable streaming (R0x301A[2] = 0) or drive the
- Enable streaming (R0x301A[2] = 1) or drive the
nearest neighbor in the same color plane. conditions, the performance of this function can degrade. Table 11. TEST PATTERN MODES
0 No test pattern (normal operation)
1 Solid color test pattern
3 Fade−to−gray color bar test pattern
256 Walking 1s test pattern (12−bit)
color bar pattern will be sent through the digital pipeline.
www.onsemi.com TWO−WIRE SERIAL REGISTER INTERFACE The two −wire serial interface bus enables read/write access to control and status registers within the MT9M034. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (S DATA). SDATA is pulled up to VDD_IO off−chip by a 1.5 kΩ resistor. Either the slave or master device can drive S DATA LOW −the interface protocol determines which device is allowed to drive S DATA at any given time. The protocols described in the two−wire serial interface specification allow the slave device to drive SCLKLOW; the MT9M034 uses SCLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two −wire serial interface bus are performed by a sequence of low−level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both S CLK and S DATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH −to−LOW transition on S DATA while S CLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Stop Condition A stop condition is defined as a LOW−to−HIGH transition on S DATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no−acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each S CLK clock period. SDATA can change when S CLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The default slave addresses used by the MT9M034 are 0x20 (write address) and 0x21 (read address) in accordance with the specification. Alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the S ADDR input. An alternate slave address can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8−bit data transfer is followed by an acknowledge bit or a no−acknowledge bit in the S CLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases S DATA. The receiver indicates an acknowledge bit by driving S DATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No−Acknowledge Bit The no−acknowledge bit is generated when the receiver does not drive S DATA LOW during the S CLK clock period following a data transfer. A no−acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8 −bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indicates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16−bit register address to which the WRITE should take place. This transfer takes place as two 8−bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8 −bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8 −bit write slave address/data direction byte and 16 −bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8−bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8−bit transfer. The slave’s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no−acknowledge bit.
Figure 26. Two-Wire Serial Bus Timing Parameters Note: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 12. TWO-WIRE SERIAL BUS CHARACTERISTICS
- This table is based on I 2C standard (v2.1 January 2000). On Semiconductor.
- Two −wire control is I2C−compatible.
- A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
- The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
- A Fast −mode I2C−bus device can be used in a Standard−mode I2C−bus system, but the requirement tSU;DAT 250 ns must then be met.
Standard−mode I2C−bus specification) before the SCLK line is released.
- Cb = total capacitance of one bus line in pF.
of PIXCLK. This can be changed using register R0x3028. Figure 27. I/O Timing Diagram Table 13. I/O TIMING CHARACTERISTICS (2.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C at 2.5 V, and −30°C at 3.1 V. All values
are taken at the 50% transition point. The loading used is 10 pF.
- Jitter from PIXCLK is already taken into account as the data of all the output parameters.
Table 14. I/O TIMING CHARACTERISTICS (1.8 V VDD_IO) (Note 1)
Table 14. I/O TIMING CHARACTERISTICS (1.8 V VDD_IO) (Note 1) (continued)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C at 1.7 V, and −30°C at 1.95 V. All values
are taken at the 50% transition point. The loading used is 10 pF.
- Jitter from PIXCLK is already taken into account as the data of all the output parameters.
Table 15. I/O RISE SLEW RATE (2.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C at 2.5 V, and −30°C at 3.1 V. The loading
Table 16. I/O FALL SLEW RATE (2.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C at 2.5 V, and −30°C at 3.1 V. The loading
Table 17. I/O RISE SLEW RATE (1.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C at 1.7 V, and −30°C at 1.95 V. The loading
Table 18. I/O FALL SLEW RATE (1.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C at 1.7 V, and −30°C at 1.95 V. The loading
Table 19. DC ELECTRICAL CHARACTERISTICS performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 20. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- Exposure to absolute maximum rating conditions for extended periods may affect reliability.
- To keep dark current and shot noise artifacts from impacting image quality, keep operating temperature at a minimum.
Table 21. OPERATING CURRENT CONSUMPTION IN PARALLEL OUTPUT AND LINEAR MODE
Table 21. OPERATING CURRENT CONSUMPTION IN PARALLEL OUTPUT AND LINEAR MODE (continued)
- Operating currents are measured at the following conditions:
Table 22. OPERATING CURRENT CONSUMPTION IN PARALLEL OUTPUT AND HDR MODE
- Operating currents are measured at the following conditions:
Table 23. STANDBY CURRENT CONSUMPTION
- Analog – V AA + VAA_PIX + VDD_PLL
Figure 28. Power Supply Rejection Ratio
- Turn on VDD_PLL power supply
- After 0–10 μs, turn on VAA and VAA_PIX power
- After 0–10 μs, turn on VDD_IO power supply
- After the last power supply is stable, enable
- Assert RESET_BAR for at least 1 ms
- Wait 850000 EXTCLKs (for internal initialization
- Configure PLL, output, and image settings to
- Wait 1ms for the PLL to lock
- Set streaming mode (R0x301A[2] = 1)
Figure 29. Power Up Table 24. POWER−UP SEQUENCE
- Xtal settling time is component −dependent, usually taking about 10–100 ms.
- Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
- It is critical that V DD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
current draw on this supply.
- Disable streaming if output is active by setting
- The soft standby state is reached after the current
Figure 30. Power Down Table 25. POWER−DOWN SEQUENCE
- t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
www.onsemi.com ILCC48 10x10 CASE 847AD ISSUE O
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