MT9M021_17 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Superior Low-light Performance
- HD Video (720p60)
- Global Shutter
- Video/Single Frame Mode
- Flexible Row-skip Modes
- On-chip AE and Statistics Engine
- Parallel and Serial Output
- Support for External LED or Flash
- Auto Black Level Calibration
- Context Switching
Applications
- Scene Processing
- Scanning and Machine Vision
- 720p60 Video Applications See detailed ordering and shipping information on page 2 of this data sheet.
ORDERING INFORMATION
MT9M021, MT9M031 www.onsemi.com Table 2. AVAILABLE PART NUMBERS please visit our web site at www.onsemi.com. video (master) mode or in frame trigger mode. dedicated pins, along with a synchronized pixel clock. external LED or flash exposure illumination. temperature sensor, and row skip and digital binning modes. that generates a stream of pixel data at a constant frame rate. a single master input clock running between 6 and 50MHz. a block diagram of the sensor. Figure 1. Block Diagram
MT9M021, MT9M031 www.onsemi.com User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 1.2 Mp Active-Pixel Sensor array. The MT9M021/MT9M031 features global shutter technology for accurate capture of moving images. The exposure of the entire array is controlled by programming the integration time by register setting. All rows simultaneously integrate light prior to readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog-to-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The pixel data are output at a rate of up to 74.25 Mp/s, in parallel to frame and line synchronization signals. FEATURES OVERVIEW The MT9M021/MT9M031 Global Sensor shutter has a wide array of features to enhance functionality and to increase versatility. A summary of features follows. Please refer to the MT9M021/MT9M031 Developer Guide for detailed feature descriptions, register settings, and tuning guidelines and recommendations.
- Operating Modes The MT9M021/MT9M031 works in master (video), trigger (single frame), or Auto Trigger modes. In master mode, the sensor generates the integration and readout timing. In trigger mode, it accepts an external trigger to start exposure, then generates the exposure and readout timing. The exposure time is programmed through the two-wire serial interface for both modes. NOTE: Trigger mode is not compatible with the HiSPi interface.
- Window Control Configurable window size and blanking times allow a wide range of resolutions and frame rates. Digital binning and skipping modes are supported, as are vertical and horizontal mirror operations.
- Context Switching Context switching may be used to rapidly switch between two sets of register values. Refer to the MT9M021/MT9M031 Developer Guide for a complete set of context switchable registers.
- Gain The MT9M021/MT9M031 Global Shutter sensor can be configured for analog gain of up to 8x, and digital gain of up to 8x.
- Automatic Exposure Control The integrated automatic exposure control may be used to ensure optimal settings of exposure and gain are computed and updated every other frame. Refer to the MT9M021/MT9M031 Developer Guide for more details.
- HiSPi The MT9M021/MT9M031 Global Shutter image sensor supports two or three lanes of Streaming-SP or Packetized-SP protocols of ON Semiconductor’s High-Speed Serial Pixel Interface.
- PLL An on chip PLL provides reference clock flexibility and supports spread spectrum sources for improved EMI performance.
- Reset The MT9M021/MT9M031 may be reset by a register write, or by a dedicated input pin.
- Output Enable The MT9M021/MT9M031 output pins may be tri-stated using a dedicated output enable pin.
- Temperature Sensor
- Black Level Correction
- Row Noise Correction
- Column Correction
- Test Patterns Several test patterns may be enabled for debug purposes. These include a solid color, color bar, fade to grey, and a walking 1s test pattern.
Figure 2. Serial 4-lane HiSPi Interface
- All power supplies must be adequately decoupled.
- ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two-wire speed.
- This pull-up resistor is not required if the controller drives a valid logic level on S CLK at all times.
- The parallel interface output pads can be left unconnected if the serial output interface is used.
- ON Semiconductor recommends that 0.1 /C0109F and 10 /C0109F decoupling capacitors for each power supply are mounted as close as possible
headboard schematics for circuit recommendations.
- ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is
- Although 4 serial lanes are shown, the MT9M021/MT9M031 supports only 2- or 3-lane HiSPi.
Figure 3. Parallel Pixel Data Interface
- All power supplies must be adequately decoupled.
- ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two-wire speed.
- This pull-up resistor is not required if the controller drives a valid logic level on S CLK at all times.
- The serial interface output pads can be left unconnected if the parallel output interface is used.
- ON Semiconductor recommends that 0.1 /C0109F and 10 /C0109F decoupling capacitors for each power supply are mounted as close as possible
headboard schematics for circuit recommendations.
- ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes i s
Figure 4. 9 /C0121 9 mm 63-ball iBGA Package Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE
Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE (continued)
Figure 5. 10 /C0121 10 mm 48-pin iLCC Package, Parallel Output Table 4. PIN DESCRIPTIONS − 48-PIN ILCC PACKAGE, PARALLEL
1 DOUT4 Output Parallel pixel data output
2 DOUT5 Output Parallel pixel data output
3 DOUT6 Output Parallel pixel data output
4 VDD_PLL Power PLL power
5 EXTCLK Input External input clock
6 DGND Power Digital ground
7 DOUT7 Output Parallel pixel data output
8 DOUT8 Output Parallel pixel data output
9 DOUT9 Output Parallel pixel data output
Table 4. PIN DESCRIPTIONS − 48-PIN ILCC PACKAGE, PARALLEL (continued)
10 DOUT10 Output Parallel pixel data output
11 DOUT11 Output Parallel pixel data output (MSB)
12 VDD_IO Power I/O supply power
14 VDD Power Digital power
15 SCLK Input Two-Wire Serial clock input
16 SDATA I/O Two-Wire Serial data I/O
18 VDD_IO Power I/O supply power
19 VDD Power Digital power
20 NC No connection
21 NC No connection
22 STANDBY Input Standby-mode enable pin (active HIGH)
23 OE_BAR Input Output enable (active LOW)
24 SADDR Input Two-Wire Serial address select
25 TEST Input Manufacturing test enable pin (connect to DGND)
26 FLASH Output Flash output control
27 TRIGGER Input Exposure synchronization input
28 FRAME_VALID Output Asserted when DOUT frame data is valid
29 LINE_VALID Output Asserted when DOUT line data is valid
30 DGND Power Digital ground
31 Reserved N/A Reserved (do not connect)
32 Reserved N/A Reserved (do not connect)
33 Reserved N/A Reserved (do not connect)
34 VAA Power Analog power
35 AGND Power Analog ground
36 VAA Power Analog power
37 VAA_PIX Power Pixel power
38 VAA_PIX Power Pixel power
39 AGND Power Analog ground
40 VAA Power Analog power
41 NC No connection
42 NC No connection
43 NC No connection
44 DGND Power Digital ground
45 DOUT0 Output Parallel pixel data output (LSB)
46 DOUT1 Output Parallel pixel data output
47 DOUT2 Output Parallel pixel data output
48 DOUT3 Output Parallel pixel data output
Figure 6. Two-Wire Serial Bus Timing Parameters NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 5. TWO-WIRE SERIAL BUS CHARACTERISTICS
Table 6. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (1.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of VDD_IO, and −30°C
at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20 pF.
- Jitter from PIXCLK is already taken into account in the data for all of the output parameters.
Table 7. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (2.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of VDD_IO, and −30°C
at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20 pF.
- Jitter from PIXCLK is already taken into account in the data for all of the output parameters.
Table 8. I/O RISE SLEW RATE (2.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of VDD_IO, and −30°C
at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20 pF.
Table 9. I/O FALL SLEW RATE (2.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of VDD_IO, and −30°C
at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20 pF. Table 10. I/O RISE SLEW RATE (1.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of VDD_IO, and −30°C
at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20 pF. Table 11. I/O FALL SLEW RATE (1.8 V VDD_IO) (Note 1)
- Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of VDD_IO, and −30°C
at 110% of VDD_IO. All values are taken at the 50% transition point. The loading used is 20 pF.
Table 13, Table 14, and Table 15. Table 12. DC ELECTRICAL CHARACTERISTICS specification is not implied. Table 13. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.
- Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 14. OPERATING CURRENT CONSUMPTION FOR PARALLEL OUTPUT
- I DD_IO operating current is specified with image at 1/2 saturation level.
Table 15. STANDBY CURRENT CONSUMPTION electrical specifications are listed at 700 MHz. Table 16. INPUT VOLTAGE AND CURRENT (HiSPi POWER SUPPLY 0.4 V)
Figure 8. Differential Output Voltage for Clock and Data Pairs
0 V (Diff)
Table 17. RISE AND FALL TIMES
- One UI is defined as the normalized mean time between one edge and the following edge of the clock.
- Taken from 0 V crossing point.
- Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates
so the rise and fall times do not exceed the maximum 0.3 UI.
- The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
- The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
- Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two
VAA, VAA_PIX) must have the separation specified below.
- Turn on VDD_PLL power supply.
- After 0−10 /C0109s, turn on VAA and VAA_PIX power
- After 0−10 /C0109s, turn on VDD_IO power supply.
- After the last power supply is stable, enable
- Assert RESET_BAR for at least 1 ms.
- Wait 150000 EXTCLKs (for internal initialization
- Configure PLL, output, and image settings to
- Wait 1 ms for the PLL to lock.
- Set streaming mode (R0x301a[2] = 1).
Figure 11. Power Up Table 18. POWER-UP SEQUENCE
- Xtal settling time is component-dependent, usually taking about 10–100 ms.
- Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
- It is critical that V DD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
high current draw on this supply.
VAA, VAA_PIX) must have the separation specified below.
- Disable streaming if output is active by setting
- The soft standby state is reached after the current
Figure 12. Power Down Table 19. POWER-DOWN SEQUENCE
- t 4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
Figure 15. 63-Ball iBGA Package Outline Drawing (Case 503AQ) Note: All dimensions in millimeters.
Figure 16. 48-Pin iLCC Package Outline Drawing (Case 847AJ)
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