1/2-Inch megapixel CMOS digital image sensor
Document overview
- Manufacturer or author: ON Semiconductor
- PDF pages: 29
Technical content
Features
MT9M001_DS Rev. M Pub. 5/15 EN 1 ©Semiconductor Components Industries, LLC , 1/2-Inch Megapixel CMOS Digital Image Sensor MT9M001C12STM (Monochrome) Datasheet, Rev. M For the latest datasheet, please visit www.onsemi.com
- Array Format (5:4): 1,280H x 1,024V (1,310,720 active pixels). Total (incl. dark pixels): 1,312H x 1,048V (1,374,976 pixels) Frame Rate: 30 fps progressive scan; programmable Shutter: Electronic Rolling Shutter (ERS) Window Size: SXGA; programmable to any smaller format (VGA, QVGA, CIF , QCIF , etc.) Programmable Controls: Gain, frame rate, frame size
Applications
Digital still cameras Digital video cameras P C c a m e r a s General Description The ON Semiconductor MT9M001 is an SXGA-format with a 1/2-inch CMOS active-pixel digital image sen- sor. The active imaging pixel array of 1,280H x 1,024V . It incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. It is programmable through a simple two-wire serial interface. This megapixel CMOS image sensor features ON Semi- conductor’ s breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. Table 1: Key Performance Parameters The sensor can be operated in its default mode or pro- grammed by the user for frame size, exposure, gain set- ting, and other parameters. The default mode outputs an SXGA-size image at 30 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data. Parameter Value Optical format 1/2-inch (5:4) Active imager size 6.66 mm (H) x 5.32 mm (V) Active pixels 1,280 H x 1,024 V Pixel size 5.2 m x 5.2 m Shutter type Electronic rolling shutter (ERS) Maximum data rate/ master clock 48 MPS/48 MHz Frame rate SXGA (1280 x 1024) 30 fps progressive scan; programmable ADC resolution 10-bit, on-chip Responsivity 2.1 V/lux-sec Dynamic range 68.2 dB SNR MAX 45 dB Supply voltage 3.0 V 3.6 V, 3.3 V nominal Power consumption 363 mW at 3.3 V (operating); 294 W (standby) Operating temperature 0°C to +70°C Packaging 48-pin CLCC
MT9M001_DS Rev. M Pub. 5/15 EN 2 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Ordering Information
Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description MT9M001C12STM-DP 1 MP 1/2" CIS Dry Pack with Protective Film MT9M001C12STM-DR 1 MP 1/2" CIS Dry Pack without Protective Film MT9M001C12STM-DR1 1 MP 1/2" CIS Dry Pack Single Tray without Protective Film MT9M001C12STM-TP 1 MP 1/2" CIS Tape & Reel with Protective Film MT9M001C12STM-TR 1 MP 1/2" CIS Tape & Reel without Protective Film MT9M001D00STMC84AC1-200 1 MP 1/2" CIS Die Sales, 200 m Thickness
MT9M001_DS Rev. M Pub. 5/15 EN 3 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Table of Contents Table of Contents
MT9M001_DS Rev. M Pub. 5/15 EN 5 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor List of Tables List of Tables
MT9M001_DS Rev. M Pub. 5/15 EN 6 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor General Description General Description Figure 1: 48-Pin CLCC Package Pinout Diagram 123456 4 84 7 4 64 5 44 43 19 20 21 22 23 24 25 26 27 28 29 30 STANDBY TRIGGER NC RESET# NC NC OE# NC A GND VAA AGND AGND NC FRAME_VALID LINE_VALID STROBE D GND VDD DOUT<9> DOUT<8> DOUT<7> DOUT<6> DOUT<5> PIXCLK NC VAA AGND VDD DGND DOUT<0> DOUT<1> DOUT<2> DOUT<3> DOUT<4> CLKIN NC NC DGND VDD NC NC VAAPIX A GND AGND SCLK S DATA NC D GND
MT9M001_DS Rev. M Pub. 5/15 EN 7 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor General Description Figure 2: Block Diagram Clock Two-wire serial Input/Output 10-bit Data Sync Signals Control Register Analog Processing Active-Pixel Sensor (APS) Array SXGA 1,280H x 1,024V Timing and Control ADC
MT9M001_DS Rev. M Pub. 5/15 EN 8 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor General Description Table 3: Pin Descriptions Pin Numbers Symbol Type Description 29 CLKIN Input Clock in. Master clock into sensor (48 MHz maximum). 13 OE# Input Output enable. OE# when HIGH places outputs D OUT<0:9>, FRAME_VALID, LINE_VALID, PIXCLK, and STROBE into a tri-state configuration. 10 RESET# Input Reset. Activates (LOW) asynchronous reset of sensor. All registers assume factory defaults. 46 SCLK Input Serial clock. Clock for serial interface. 7 STANDBY Input Standby. Activates (HIGH) standby mode, disables analog bias circuitry for power saving mode. 8 TRIGGER Input Trigger. Activates (HIGH) snapshot sequence. 45 S DATA Input/Output Serial data. Serial data bus, requires 1.5 K resistor to 3.3V for pull-up. 24–28, 32–36 D OUT<0–9> Output Data out. Pixel data output bits 0:9, D OUT<9> (MSB), DOUT<0> (LSB). 41 FRAME_VALID Output Frame valid. Output is puls ed HIGH during frame of valid pixel data. 40 LINE_VALID Output Line valid. Output is pulsed H IGH during line of selectable valid pixel data (see Reg0x20 for options). 31 PIXCLK Output Pixel clock. Pixel data outputs are valid during falling edge of this clock. Frequency = (master clock). 39 STROBE Output Strobe. Output is pulsed HIGH to indicate sensor reset operation of pixel array has completed. 15,17,18,21, 47, AGND Supply Analog ground. Provide isolated ground for analog block and pixel array. 5, 23, 38, 43 D GND Supply Digital ground. Provide isol ated ground for digital block. 16, 20 V AA Supply Analog power. Provide power supply for analog block, 3.3V ±0.3V. 4, 22, 37 V DD Supply Digital power. Provide power supply for digital block, 3.3V ±0.3V. 2, 3 ,6, 9, 11, 12,14, 19, 30, 42, NC — No connect. These pins must be left unconnected.
MT9M001_DS Rev. M Pub. 5/15 EN 11 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Pixel Data Format Figure 7: Row Timing and FRAME_VALID/LINE_VALID Signals P1 A Q A Q AP 2 . . . . . . . . . Number of master clocks FRAME_VALID LINE_VALID
MT9M001_DS Rev. M Pub. 5/15 EN 12 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Pixel Data Format Frame Timing Formulas Notes: 1. Row skip mode should have no effect on the integration time. Column skip mode changes the effec- tive value of Column Size (Reg0x04) as follows: Column Skip 2 => R4eff = (int(R4 / 4) x 2) + 1 Column Skip 4 => R4eff = (int(R4 / 8) x 2) + 1 Column Skip 8 => R4eff = (int(R4 / 16) x 2) + 1 where the int() function truncates to the next lowest integer. Now use R4eff in the equation for row time instead of R4 2. Default for Reg0x05 = 9. However, sensor ignores any value for Reg0x05 less than 19. Sensor timing is shown above in terms of pixel clock and master clock cycles (please refer to Figure 6). The recommended master clock frequency is 48 MHz. The vertical blank and total frame time equations assume that the number of integration rows (bits 13 through 0 of Reg0x09) is less than the number of active plus blanking rows (Reg0x03 + 1 + Reg0x06 + 1). If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 5. Table 4: Frame Timing Parameter Name Equation (MASTER CLOCK) Default Timing Notes A Active Data Time (Reg0x04 + 1) 1,280 pixel clocks = 26.7s P1 Frame Start Blanking (242) 242 pixel clocks = 5.04s P2 Frame End Blanking (2 + Reg0x05 - 19) (MIN Reg0x05 value = 19) 2 pixel clocks = 0.042s Q = P1 + P2 Horizontal Blanking (244 + Reg0x05 - 19) (MIN Reg0x05 value = 19) 244 pixel clocks = 5.08s A + Q Row Time ((Reg0x04 + 1) + (244 + Reg0x05 - 19)) 1,524 pixel clocks = 31.75s V Vertical Blanking (Reg0x06 + 1) x (A + Q) (MIN Reg0x06 value = 15) 39,624 pixel clocks = 825.5s NROWS x (A + Q) Frame Valid Time (Reg0x03 + 1) x (A + Q) 1,560,576 pixel clocks = 32.51ms F Total Frame Time (Reg0x03 + 1 + Reg0x06 + 1) x (A + Q) 1,600,200 pixel clocks = 33.34ms Table 5: Frame Time — Long Integration Time Parameter Name Equation (master clock) Default Timing V’ Vertical Blanking (long integration time) (Reg0x09 – Reg0x03) x (A + Q) 39,624 pixel clocks = 82.5s F’ Total Frame Time (long integration time) (Reg0x09 + 1) x (A + Q) 1,600,200 pixel clocks = 33.34ms
MT9M001_DS Rev. M Pub. 5/15 EN 13 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Serial Bus Description Serial Bus Description Registers are written to and read from the MT9M001 through the two-wire serial inter- face bus. The sensor is a two-wire serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out of the MT9M001 through the serial data (S DATA) line. The SDATA line is pulled up to 3.3V off-chip by a 1.5K resistor. Either the slave or master device can pull the SDATA line down—the serial interface protocol determines which device is allowed to pull the S DATA line down at any given time. Protocol The two-wire serial interface defines several different transmission codes, as follows: a s t a r t b i t the slave device eight-bit address a(an) (no) acknowledge bit an 8-bit message a s t o p b i t Sequence A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's eight-bit address. The last bit of the address determines if the request will be a read or a write, where a “0” indicates a write and a “1” indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. The MT9M001 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data eight bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH.
MT9M001_DS Rev. M Pub. 5/15 EN 14 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Serial Bus Description Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of seven bits of address and 1 bit of direction. A “0” (0xBA) in the LSB (least significant bit) of the address indi- cates the write mode, and a “1” (0xBB) indicates read mode. Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock—it can only change wh en the serial clock is LOW . Data is trans- ferred eight bits at a time, followed by an acknowledge bit. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.
MT9M001_DS Rev. M Pub. 5/15 EN 16 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Feature Description Feature Description Signal Path The MT9M001 signal path consists of two stages, a programmable gain stage and a programmable analog offset stage. Programmable Gain Stage A total programmable gain of 15 is available and can be calculated using the following formula: Gain 1 to 8: Gain = (bit[6] + 1) x (bit[5:0] x 0.125) For gain higher than eight, the user would need to set bit[6:5] = 11 and use the lower 3 LSB's bit[2:0] to set the higher gain values. The formula for obtaining gain greater than eight is as follows: Total gain = 8 + bit[2:0] For example, for total gain = 12, the value to program is bit[6–0] = 1100100. The maximum total gain = 15, i.e. bit[6:0] = 1100111. The gain circuitry in the MT9M001 is designed to offer signal gains from one to 15. The minimum gain of one corresponds to the lowest setting where the pixel signal is guaran- teed to saturate the ADC under all specified operating conditions. Any reduction of the gain below this value may cause the sensor to saturate at ADC output values less than the maximum, under certain conditions. It is recommended that this guideline be followed at all times. Since bit[6] of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. Some settings offer superior noise perfor- mance to others, despite the same overall gain. Recommended gain settings are listed in Table 6. Figure 10: Signal Path Table 6: Recommended Gain Settings at 48 MHz Nominal Gain Increments Recommended Settings 1 to 4.000 0.125 0x08 to 0x20 4.25 to 8.00 0.25 0x51 to 0x60 9 to 15 1.0 0x61 to 0x67 X + Pixel Output (signal minus reset) Offset Correction Voltage (Reg0x60, Reg0x61, Reg0x63, Reg0x64) (signed lower 9 bits) x 2mV 10-bit ADC ADC Data (9:0) Gain Selection (Reg0x2B - 0x2E)
MT9M001_DS Rev. M Pub. 5/15 EN 18 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Feature Description Figure 13: Readout of Eight Pixels in Normal and Column Skip Output Mode Black Level Calibration The MT9M001 has automatic black level calibration on-chip which can be overridden by the user, as described below and shown in Figure 14. The automatic black level calibration measures the average value of 256 pixels from two dark rows of the chip for each of the four colors. The pixels are averaged as if they were light-sensitive and passed through the appropriate color gain. This average is then digi- tally filtered over many frames. For each color, the new filtered average is compared to a minimum acceptable level (to screen for too low a black level) and a maximum acceptable level. If the average is lower than the minimum acceptable level, the offset correction voltage for that color is increased by one offset LSB (offset LSBs do not match ADC LSBs; typically, one offset LSB is approximately 2mV). If it is above the maximum level, the level is decreased by 1 LSB (2mV). The upper threshold is automa tically adjusted upwards whenever an upward shift in the black level from below the minimum results in a new black level above the maximum. This prevents black level oscillation from below the minimum to above the maximum. The lower threshold is increased with the maximum gain setting according to the formula described under Reg0x5F . This prevents clipping of the black level. Whenever the gain or any of the readout timing registers is changed (shutter width, vertical blanking, number of rows or columns, or the shutter delay) or if the black level recalculation bit, reset bit or restart bit is set, the running digitally filtered average is reset to the first average of the dark pixels. The digital filtering over many frames is then restarted. Whenever the gain or the readout timing registers are changed, the upper threshold is restored to its default value. After changes to the sensor configuration, large shifts in the black level calibration can result. To quickly adapt to this shift, a rapid sweep of the black level during the dark-row readout is performed on the first frame after certain changes to the sensor registers. Any changes to the registers listed above will cause this recalculation. The data from this sweep allows the sensor to choose an accurate new starting point for the running average. This procedure can be disabled as described under Reg0x5F . DOUT9–DOUT0 LINE_VALID Normal readout (9:0) (9:0) (9:0) (9:0) (9:0) (9:0) (9:0) (9:0) DOUT9–DOUT0 LINE_VALID Column skip readout (9:0) (9:0) (9:0) (9:0)
MT9M001_DS Rev. M Pub. 5/15 EN 19 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Feature Description Figure 14: Black Level Calibration Flow Chart X + Pixel Output (signal minus reset) Offset Correction Voltage (color-wise) 10-bit ADC ADC Data (9:0) Gain Selection (color-wise)
MT9M001_DS Rev. M Pub. 5/15 EN 21 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Electrical Specifications Electrical Specifications Data Output and Propagation Delays By default, the MT9M001 launches pixel data, FRAME_VALID and LINE_VALID with the rising edge of PIXCLK. The expectation is that the user captures DOUT[7:0], FRAME_VALID and LINE_VALID using the falling edge of PIXCLK. Figure 17: Data Output Timing Diagram Table 7: DC Electrical Characteristics (DC Setup Conditions: fCLKIN = 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, TA = 25°C) Symbol Definition Condition Min Typ Max Units VDD Core digital voltage 3 3.3 3.6 V VAA Analog voltage 3 3.3 3.6 V VAAPIX Pixel supply voltage 3 3.3 3.6 V VIH Input high voltage V PWR - 0.3 V PWR + 0.3 V VIL Input low voltage -0.3 0.8 V IIN Input leakage current No Pull-up Resistor; VIN = VDD or DGND -15 15 A VOH Output high voltage V PWR - 0.2 — V VOL Output low voltage 0.2 V IOZ Tri-state output leakage current — 15 A IDD Digital operating current — 20 24 mA IAA Analog operating current — 85 110 mA IAAPIX Pixel supply current — 5 10 mA CLKIN PIXCLK tR tFtCLKIN Data[0-7] Frame Valid/ Line Valid XXXXXX XXX XXX XXXXXX Note: Frame_Valid leads Line_Valid by 242 PIXCLKs. Note: Frame_Valid trails Line_Valid (1+ Reg0x05-19) PIXCLKS. tCP tPFL tPLL tFVS tPD tOH P0 P1 P2 PN tLVS tOS tPFH tPLH T
MT9M001_DS Rev. M Pub. 5/15 EN 22 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Electrical Specifications Note: 1Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ISTDBYD Digital standby current STDBY = V DD, CLKIN = 0 MHz — 9 20 A ISTDBYD W/CLK Digital standby current STDBY = V DD, CLKIN = 48 MHz — 55 125 A ISTDBYDA Analog standby current STDBY = V DD — 80 100 A Table 8: AC Electrical Characteristics (AC Setup Conditions: fCLKIN= 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, Output Load = 30pF, TA = 25°C)) Symbol Definition Condition Min Typ Max Unit fCLKIIN Input clock frequency 1 — 48 MHz tCLKIN Input clock period 1000 — 20.83 ns T PIXCLK period 1000 — 20.83 ns tR Input clock rise time 4 V/ns tF Input clock fall time — 4 V/ns Clock duty cycle 45 50 55 % tCP CLKIN to PIXCLK propagation delay — 10 — ns tPD PIXCLK to data valid — — 1 ns tPFH PIXCLK to FV high — — 7 ns tPLH PIXCLK to LV high — — 7 ns tPFL PIXCLK to FV low — — 13 ns tPLL PIXCLK to LV low — — 13 ns tOS Setup time for data before falling edge of PIXCLK T/2 -1 T/2 T/2 +1 ns tOH Hold time for data after falling edge of PIXCLK T/2 -1 T/2 T/2 +1 ns tFVS Setup time for FV before falling edge of PIXCLK 2 3 — ns tLVS Setup time for LV before falling edge of PIXCLK 2 3 — ns CLOAD Load capacitance 30 pF Table 9: Absolute Maximum Ratings Symbol Parameter Rating UnitMIN MAX TOP Operating temperature 0 70 °C TSTG1 Storage temperature –40 125 °C Table 7: DC Electrical Ch aracteristics (continued) (DC Setup Conditions: fCLKIN = 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, TA = 25°C) Symbol Definition Condition Min Typ Max Units
MT9M001_DS Rev. M Pub. 5/15 EN 26 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Electrical Specifications Notes: 1. X and Y coordinates referenced to center of die. 2. Die center = package center. 3. Image center offset from package center (x = 0.015mm, y = 0.712mm). Figure 26: Optical Orientation Table 10: Optical Area Dimensions Optical Area Pixel X-Dimension Y-dimension SXGA Center of pixel (20, 12) 3,340.70 m 3,372.45 m Center of Pixel (1299, 1035) -3,315.2 m -1,952.35 m Chip Size, mm (including Seal Ring) 7.75mm 7.75mm UP Pin 1 Pixel Array Top of board Bottom of board
MT9M001_DS Rev. M Pub. 5/15 EN 27 ©Semiconductor Components Industries, LLC,2015 MT9M001: 1/2-Inch Megapixel Digital Image Sensor Electrical Specifications Figure 27: 48-pin CLCC Package Outline Drawing Notes: 1. All exposed metallized area shall be gold plated 60 micro inches min thk. over nickel plated unless otherwise specified in purchase order. 2. Seal area and die attach area shall be without metallization. 3. Die center to package center accuracy +/- 100 m. 4. Die thickness = 0.675mm(26.5mils). 5. Epoxy thickness for die attachment is 0.025~0.050 mm. 6. Glass transmittance >=90%. 7. Glass tilt =0.10mm max. 8. All dimensions in millimeters. Top View Side View Bottom View
MT9M001_DS Rev. M Pub. 5/15 EN 28 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Revision History
Updated “Ordering Information” on page 2 Converted to ON Semiconductor template Removed Digital Clarity Applied updated template Updated to non-confidential Removed registers and transfered to separate document Updated Figure 27: “48-pin CLCC Package Outline Drawing” on page 30 Updated to Aptina template Updated description in Table 2, “ Available Part Numbers,” on page 1 Update Figure 4: “Pixel Pattern Detail (Top Right Corner),” on page 9 Updated "Data Output and Propagation Delays" on page 21 U p d a t e d tPFL and tPLL in Table 8, “ AC Electrical Characteristics,” on page 22 Updated Table 1, “Key Performance Parameters,” on page 1 Update Table 2, “ Available Part Numbers,” on page 1 Updated Figure 4: “Pixel Pattern De tail (Top Right Corner),” on page 9 Remove color information Updated Table 1, “Key Performance Parameters,” on page 1 Updated Table 6, “Register List and Default Values,” on page 11 Updated Table 7, “Registe r Description,” on page 12 Updated Figure 12, Readout of Six Rows in Normal and Row Mirror Output Mode, on page 17 Deleted Figure 13, Readout of Eight Pixels in Normal and Column Skip Output Mode, on page 18 Updated Table 8, “ AC Electrical Characteristics,” on page 22 Updated Figure 25, Image Center Offset, on page 25 Updated Figure 27, 48-pin CLCC Package Outline Drawing, on page 27 Page 1, remove PRELIMINARY disclaimer Page 1, add Key Performance Parameters table, add APPLICATIONS Page 2, add Table of Contents Page 6, update Pin Description table
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