MT9F002I12STCVH-GEVB

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Technical content

Features

• 1.4 /C0109m Pixel with ON Semiconductor A−Pix/C0116 Technology
• Simple Two−wire Serial Interface
• Auto Black Level Calibration
• Full HD Support at 60 fps for Maximum Video Performance
• 20 percent Extra Image Array Area in Full HD to Enable Electronic Image Stabilization (EIS)
• Support for External Mechanical Shutter
• Support for External LED or Xenon Flash
• High Frame Rate Preview Mode with Arbitrary Down−size Scaling from Maximum Resolution
• Programmable Controls: Gain, Horizontal and Vertical Blanking, Frame Size/Rate, Exposure, Left–right and Top–bottom Image Reversal, Window Size, and Panning
• Data Interfaces: Parallel or Four−lane Serial Highspeed Pixel Interface (HiSPi/C0116) Differential Signaling (SLVS)
• On−chip Phase−locked Loop (PLL) Oscillator
• Bayer Pattern Downsize Scaler *Parallel interface does not work for MT9F002 package parts

Applications

• Digital Video Cameras
• Digital Still Cameras General Description The ON Semiconductor MT9F002 is a 1/2.3−inch CMOS active−pixel digital imagin g sensor with an active pixel array of 4608 H ×

3288 V (4640 H × 3320 V including border pix-

els). It can support 14−megapixel (4384 H ×

3288 V) digital still images and a 1080p plus ad-

ditional 20 percent pixels for electronic image See detailed ordering and shipping information on page 2 of this data sheet.

ORDERING INFORMATION

www.onsemi.com stabilization (4608 H × 2592 V) in digital video mode. The MT9F002 sensor is programmable through a simple two−wire serial interface, and has low power consumption. Table 2. AVAILABLE PART NUMBERS to a pixel clock rate of 220 MHz and 96 MHz, respectively. A block diagram of the sensor is shown in Figure 1. Figure 1. MT9F002 Block Diagram

Figure 4. High−Resolution Still Image Capture + HD Video

such a way that coupling between the two are minimized.

1. All power supplies should be adequately decoupled. ON Semiconductor recommends having 1.0 /C0109F and 0.1 /C0109F decoupling capacitors
2. ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two−wire speed.
3. This pull−up resistor is not required if the controller drives a valid logic level on S CLK at all times.
4. The GPI pins can be statically pulled HIGH or LOW and can be programmed to perform special functions (TRIGGER/VD, OE_BAR, SADDR,

STANDBY) to be dynamically controlled. GPI pads can be left floating, when not used.

1. V PP, which is not shown in Figure 5, is left unconnected during normal operation.
2. The parallel interface output pads can be left unconnected when the serial output interface is used.
3. ON Semiconductor recommends that 0.1 /C0109F and 10 /C0109F decoupling capacitors for each power supply are mounted as close as possible

schematics for circuit recommendations.

1. TEST signals must be tied to D GND for normal sensor operation.
2. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is

10.For serial HiSPi HiVCM mode, set register bit R0x306E[9] = 1 and VDD_TX = VDD_IO = 1.8 V. Figure 5. Typical Configuration: Serial Four−Lane HiSPi Interface

1. All power supplies should be adequately decoupled. ON Semiconductor recommends having 1.0 /C0109F and 0.1 /C0109F decoupling capacitors
2. ON Semiconductor recommends a resistor value of 1.5 k /C0087, but a greater value may be used for slower two−wire speed.
3. This pull−up resistor is not required if the controller drives a valid logic level on S CLK at all times.
4. The GPI pins can be statically pulled HIGH or LOW and can be programmed to perform special functions (TRIGGER/VD, OE_BAR, SADDR,

STANDBY) to be dynamically controlled. GPI pads can be left floating, when not used.

1. V PP, which is not shown in Figure 6, is left unconnected during normal operation.
2. The serial interface output pads can be left unconnected when the parallel output interface is used.
3. ON Semiconductor recommends that 0.1 /C0109F and 10 /C0109F decoupling capacitors for each power supply are mounted as close as possible

schematics for circuit recommendations.

1. TEST signals must be tied to D GND for normal sensor operation.
2. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is

Figure 6. Typical Configuration: Parallel Pixel Data Interface (Die Only)

Table 3 provides signal descriptions for MT9F002 die. Table 3. SIGNAL DESCRIPTIONS EXTCLK Input Master clock input, 2−64 MHz. are restored to their factory default settings. SCLK Input Serial clock for access to control and status registers. select, shutter trigger or slave mode trigger (VD) function. Can be left floating if not used. TEST Input Enable manufacturing test modes. Tie to DGND for normal sensor operation. SDATA I/O Serial data from READs and WRITEs to control and status registers. VPP Supply Disconnect pad for normal operation. VDD_TX Supply Digital power supply for the HiSPi I/O. For HiSPi SLVS mode, set register bit R0x306E[9] = 0 (default), and VDD_TX to 0.4 V. For HiSPi HiVCM mode, set register bit R0x306E[9] = 1, and VDD_TX = VDD_IO. VAA Supply Analog power supply. VAA_PIX Supply Analog power supply for the pixel array. VDD Supply Digital power supply. VDD_IO Supply I/O power supply. DGND Supply Common ground for digital and I/O. VDD_PLL Supply PLL power supply. SLVS_0P Output Lane 1 differential HiSPi (SLVS) serial data (positive). Qualified by the SLVS serial clock. SLVS_0N Output Lane 1 differential HiSPi (SLVS) serial data (negative). Qualified by the SLVS serial clock. SLVS_1P Output Lane 2 differential HiSPi (SLVS) serial data (positive). Qualified by the SLVS serial clock. SLVS_1N Output Lane 2 differential HiSPi (SLVS) serial data (negative). Qualified by the SLVS serial clock. SLVS_2P Output Lane 3 differential HiSPi (SLVS) serial data (positive). Qualified by the SLVS serial clock. SLVS_2N Output Lane 3 differential HiSPi (SLVS) serial data (negative). Qualified by the SLVS serial clock. SLVS_3P Output Lane 4 differential HiSPi (SLVS) serial data (positive). Qualified by the SLVS serial clock. SLVS_3N Output Lane 4 differential HiSPi (SLVS) serial data (negative). Qualified by the SLVS serial clock. SLVS_CP Output Differential HiSPi (SLVS) serial clock (positive). Qualified by the SLVS serial clock. SLVS_CN Output Differential HiSPi (SLVS) serial clock (negative). Qualified by the SLVS serial clock. LINE_VALID Output LINE_VALID (LV) output. Qualified by PIXCLK. FRAME_VALID Output FRAME_VALID (FV) output. Qualified by PIXCLK. DOUT[11:0] Output Parallel pixel data output. Qualified by PIXCLK. PIXCLK Output Pixel clock. Used to qualify the LV, FV, and DOUT[11:0] outputs. FLASH Output Flash output. Synchronization pulse for external light source. Can be left floating if not used. SHUTTER Output Control for external mechanical shutter. Can be left floating if not used.

distributing pixel data over defined data lanes. to transmit across 1, 2, or all 4 data lanes. transmit each active data line and vertical blanking lines. Line” (EOL) sync code at the end of a row within the frame. Figure 9. Streaming vs. Packetized Transmission Note: See the High−Speed Serial Pixel (HiSPi) Protocol Specification V1.00.00 for HiSPi details.

• Scalable Low V oltage Serial (SLVS) which has low amplitude and common−mode voltage (VCM) but scalable using an external supply.
• High VCM scalable serial interface (HiVCM), which has larger scalable amplitude and a high common−mode voltage. Comparison of SLVS and HiVCM Here is a comparison of the differences between SLVS and HiVCM.

Table 4. SLVS AND HiVCM COMPARISON

1. These are nominal values.
2. Power from load driving stage, digital/serializer logic

Figure 12. Block Diagram of DLL Timing Adjustment Figure 13. Delaying the clock_lane with Respect to data_lane Figure 14. Delaying data_lane with Respect to the clock_lane

1 UItDLLSTEP

Note: See the High−Speed Serial Pixel (HiSPi) Physical Layer Specification V2.00.00 for details.

rate are given in “Frame Rate Control” on page 48. Table 5. COMMON SENSOR READOUT MODES

2304 H x 1296 V (16:9) 96 x: Bin2

1536 H x 864 V (16:9) 64 x: Bin2

1096 H x 822 V (4:3) 100 x: Skip2Bin2

1152 H x 648 V (16:9) 96 x: Skip2Bin2

access to control and status registers within the MT9F002. is an input to the sensor and is used to synchronize transfers.

1. a (repeated) start condition
2. a slave address/data direction byte
3. an (a no−) acknowledge bit

generate the start and stop conditions. “repeated start” or “restart” condition. One data bit is transferred during each SCLK clock period. SADDR signal through the GPI pin.

• SCLK
• SDATA
• SADDR (through the GPI pin) SCLK is an input−only signal and must always be driven to a valid logic level for correct operation; if the driving device can place this signal in High−Z, an external pull−up resistor should be connected on this signal. S DATA is a bidirectional signal. An external pull−up resistor should be connected on this signal. SADDR is a signal that can be optionally enabled and controlled by a GPI pin to select an alternate slave address. These slave addresses can also be programmed through R0x31FC. This interface is described in detail in “Two−Wire Serial Register Interface”. Parallel Pixel Data Interface The parallel pixel data interface uses these output−only signals:
• FV
• LV
• PIXCLK
• DOUT[11:0] The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. Table 8 shows the recommended settings. When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. Set reset_register[12] to disable the serializer while in parallel output mode. Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High−Z under pin or register control, as shown in

Table 7. Selection of a pin to use for the OE_N function is described in “General Purpose Inputs”. Table 7. OUTPUT ENABLE CONTROL

0 X Interface driven

Table 8. CONFIGURATION OF THE PIXEL DATA INTERFACE synchronized to the end of frames in the parallel pixel data interface. states: hardware standby, software standby, and streaming. amount of clock cycles as outlined in Table 9.

Figure 26. MT9F002 System States

2700 EXTCLK

Table 9. RESET_BAR AND PLL IN SYSTEM STATES NOTE: VCO = voltage−controlled oscillator.

1. The negation of the RESET_BAR input.
2. A timeout of the internal power−on reset circuit.

the sensor, truncating any frame that is in progress. completed is to poll a sensor register; for example, R0x0000. VCO lock time is 1 ms (minimum). sequence, while the PLL and analog blocks are turned off. changed from their default power−up values. Table 10. SIGNAL STATE DURING RESET EXTCLK Input Enabled. Must be driven to a valid logic level. GPI[3:0] Powered down. Can be left disconnected/floating. TEST Enabled. Must be driven to a logic 0. SCLK Enabled. Must be pulled up or driven to a valid logic level. SDATA I/O Enabled as an input. Must be pulled up or driven to a valid logic level. LINE_VALID Output High−Z. Can be left disconnected or floating.

The MT9F002 provides four general purpose inputs.

• Output enable (see “Output Enable Control”)
• Trigger/VD (slave mode) − see the sections below
• Standby functions
• SADDR selection (see “Serial Register Interface”) The gpi_status register is used to associate a function with a general purpose input. Streaming/Standby Control The MT9F002 can be switched between its soft standby and streaming states under pin or register control, as shown in Table 11. Selection of a pin to use for the STANDBY function is described in “General Purpose Inputs”. The state diagram for transitions between soft standby and streaming states is shown in Figure 26.

Table 11. STREAMING/STANDBY

1 X Soft standby

Table 12. TRIGGER CONTROL

1 X Trigger

www.onsemi.com The parameter limit register space contains registers that declare the minimum and maximum allowable values for:

• The frequency allowable on each clock
• The divisors that are used to control each clock. The following factors determine what are valid values, or combinations of valid values, for the divider/multiplier control registers:
• The minimum/maximum frequency limits for the associated clock must be met: ♦ pll_ip_clk_freq must be in the range 2−24 MHz. Lower frequencies are preferred. ♦ PLL internal VCO frequency must be in the range 384−768 MHz.
• The minimum/maximum value for the divider/multiplier must be met: Range for pre_pll_clk_div: 1−64.
• clk_op must never run faster than clk_pixel to ensure that the output data stream is contiguous.
• When the serial interface is used the clk_op divider cannot be used; row_speed[10:8] must equal 1.
• The value of op_sys_clk_div must match the bit−depth of the image when using serial interface. R0x0112−3 controls whether the pixel data interface will generate 12, 10, or 8 bits per pixel. When the pixel data interface is generating 8 bits per−pixel, op_pix_clk_div must be programmed with the value 8. When the pixel data interface is generating 10 bits per pixel, op_pix_clk_div must be programmed with the value 10. And when the pixel data interface is generating 12 bits per pixel, op_pix_clk_div must be programmed with the value 12. This is not required when using the parallel interface.
• Although the PLL VCO input frequency range is advertised as 2−24 MHz, superior performance (better PLL stability) is obtained by keeping the VCO input frequency as high as possible. The usage of the output clocks is shown below:
• clk_pixel is used by the sensor core to control the timing of the pixel array. The sensor core produces two 10−bit pixels each clk_pixel period. The line length (line_length_pck) and fine integration time (fine_integration_time) are controlled in increments of half of the clk_pixel period.
• clk_op is used to load parallel pixel data from the output FIFO. The output FIFO generates one pixel each clk_op period. This clock also equals the output PIXCLK.
• Master clock frequency corresponds to vt_pix_clk/2.
• Serial clock (op_sys_clk) used for the serial output interface. Programming the PLL Divisors The PLL divisors must be programmed while the MT9F002 is in the software standby state. After programming the divisors, wait for the VCO lock time before enabling the PLL. The PLL is enabled by entering the streaming state. An external timer will need to delay the entrance of the streaming mode by 1 millisecond so that the PLL can lock. The effect of programming the PLL divisors while the MT9F002 is in the streaming state is undefined. Clock Control The MT9F002 uses an aggressive clock−gating methodology to reduce power consumption. The clocked logic is divided into a number of separate domains, each of which is only clocked when required. When the MT9F002 enters a low−power state, almost all of the internal clocks are stopped. The only exception is that a small amount of logic is clocked so that the two−wire serial interface continues to respond to READ and WRITE requests.

www.onsemi.com The MT9F002 supports scaling capability. Scaling is a “zoom out” operation to reduce the size of the output image while covering the same extent as the original image. That is, low resolution images can be generated with full field−of−view. Each scaled output pixel is calculated by taking a weighted average of a group input pixels which is composed of neighboring pixels. The input and output of the scaler is in Bayer format. When compared to skipping, scaling is advantageous because it uses all pixel values to calculate the output image which helps avoid aliasing. Also, it is also more convenient than binning because the scale factor varies smoothly and the user is not limited to certain ratios of size reduction. The MT9F002 sensor is capable of horizontal scaling and full (horizontal and vertical) scaling. The scaling factor is programmable in 1/16 steps and is determined by. ScaleFactor /C0043scale_n scale_m /C004316 scale_m (eq. 7) scale_n is fixed at 16. scale_m is adjustable with R0x0404 Legal values for m are 16 through 128. The user has the ability to scale from 1:1 (m = 16) to 1:8 (m = 128). Scaler Example When horizontal and vertical scaling is enabled for a 1:2 scale factor, an image is reduced by half in both the horizontal and vertical directions. This results in an output image that is one−fourth of the original image size. This can be achieved with the following register settings: R0x0400 = 0x0002 // horizontal and vertical scaling mode R0x0402 = 0x0020 // scale factor m = 32 Shading Correction Lenses tend to produce images whose brightness is significantly attenuated near the edges. There are also other factors causing color plane nonuniformity in images captured by image sensors. The cumulative result of all these factors is known as image shading. The MT9F002 has an embedded shading correction module that can be programmed to counter the shading effects on each individual Red, GreenB, GreenR, and Blue color signal. The Correction Function Color−dependent solutions are calibrated using the sensor, lens system and an image of an evenly illuminated, featureless gray calibration field. From the resulting image, register values for the color correction function (coefficients) can be derived. The correction functions can then be applied to each pixel value to equalize the response across the image as follows: Pcorrected(row, col) /C0043Psensor(row, col) * f(row, col) (eq. 8) where P are the pixel values and f is the color dependent correction functions for each color channel. Each function includes a set of color−dependent coefficients defined by registers R0x3600–3726. The function’s origin is the center point of the function used in the calculation of the coefficients. Using an origin near the central point of symmetry of the sensor response provides the best results. The center point of the function is determined by ORIGIN_C (R0x3782) and ORIGIN_R (R0x3784) and can be used to counter an offset in the system lens from the center of the sensor array.

1. Electronic rolling shutter (ERS) mode

described in detail in “Global Reset”. x_output_size, and y_output_size registers accordingly. Figure 28. Effect of Horizontal Mirror on Readout Order

• 0 = Normal readout
• 1 = Readout is mirrored horizontally so that the column specified by x_addr_end_ is read out of the sensor first. Vertical Flip When the vertical_flip bit is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. Figure 29 shows a sequence of 6 rows being read out with vertical_flip = 0 and vertical_flip = 1. Changing vertical_flip causes the Bayer order of the output image to change; the new Bayer order is reflected in the value of the pixel_order register.

Figure 38. Pixel Readout (x_odd_inc = 7, y_odd_inc = 31) same integration times to be used in each mode.

• x_addr_start should be a multiple of x_skip_factor*8
• (x_addr_end − x_addr_start + x_odd_inc) should be a multiple of x_skip_factor*8 The number of columns/rows read out with subsampling can be found from the equation below:
• columns/rows = (addr_end − addr_start + odd_inc) / skip_factor

Figure 40. Bayer Resampling

Figure 41. Results of Resampling

1. Set 0x0400 to 0x02 // Enable the on−chip scalar.
2. Set 0x306E to 0x90B0 // Configure the on−chip

scalar to resample Bayer data.

1. Set 0x0400 to 0x00 // Disable the on−chip scalar.
2. Set 0x306E to 0x9080 // Configure the on−chip

scalar to resample Bayer data. row, or by the time it takes to sample and read out a row. Values for min_line_blanking_pck are provided in Table 14. coarse_integration_time + 1. register settings are shown in Table 14. Table 14. MINIMUM ROW TIME AND BLANKING NUMBERS

1. line_length_pck> min_line_length_pck
2. line_length_pck > 0.5*(x_addr_end − x_addr_start

1. The row time must allow the FIFO to output all

• For parallel interface: line_length_pck > (x_output_size) * “vt_pix_clk period” / “op_pix_clk period” + 0x005E
• For HiSPi (4−lane): line_length_pck ≥ (1/4)*(x_output_size) * “vt_pix_clk period” / “op_pix_clk period” + 0x005E Minimum Frame Time The minimum number of rows in the image is 2, so min_frame_length_lines will always equal (min_frame_blanking_lines + 2).

Table 15. MINIMUM FRAME TIME AND BLANKING coarse_integration_time registers. the larger integration time. corresponding fine_correction values are shown in Table 16. Table 16. FINE_INTEGRATION_TIME LIMITS Table 17. FINE_CORRECTION VALUES

Table 18. POWER MODE CONTEXTS

1 R0x30E8 0x8001 Reserved

2 R0x30E8 0x8002 Reserved

3 R0x30E8 0x8003 Reserved

4 Rr0x30E8 0x8004 Reserved

5 R0x30E8 0x8005 Reserved

6 R0x30E8 0x8006 Reserved

7 R0x30E8 0x8007 Reserved

registers to control both analog and digital gain to the sensor.

• global_gain
• greenR_gain
• red_gain
• blue_gain
• greenB_gain The registers provide three analog gain stages. The analog_gain_2 analog gain stage has a granularity of 64 steps over 2x gain. A digital gain (GAIN<15:12>) from 1−15x can also be applied. Analog Gain Stages The analog gain stages of the MT9F002 sensor are shown in Figure 42. The recommended gain settings enable gain increases very early in the signal chain (such as in the colamp), so the signal can be effectively boosted while amplifying as few noise sources as possible.

Figure 42. Analog Gain Stages settings are shown in Table 19. Table 19. RECOMMENDED REGISTER SETTINGS

next VD rising edge to begin the readout. Figure 54. Slave Mode GRR Timing

Figure 55. Slave Mode HiSPi Output (ERS to GRR Transition)

Table 20. TEST PATTERNS

0 Normal operation: no test pattern

1 Solid color

3 Fade−to−gray color bars

4 PN9 link integrity pattern (only on sensors with serial interface)

256 Walking 1s (12−bit value)

257 Walking 1s (10−bit value)

258 Walking 1s (8−bit value)

and controlled by test_mode (R0x31C6[6:4]). Table 21. HiSPi TEST PATTERNS 0 Transmit a constant 0 on all enabled data lanes. 1 Transmit a constant 1 on all enabled data lanes. 2 Transmit a square wave at half the serial data rate on all enabled data lanes. 3 Transmit a square wave at the pixel rate on all enabled data lanes. 4 Transmit a continuous sequence of pseudo random data, with no SAV code, copied on all enabled data lanes. 5 Replace data from the sensor with a known sequence copied on all enabled data lanes. set appropriately to control the frame rate and output timing.

• All clock divisors
• x_addr_start
• x_addr_end
• y_addr_start
• y_addr_end
• frame_length_lines
• line_length_pck
• x_output_size
• y_output_size Effect of Data Path Processing on Test Patterns Test patterns are introduced early in the pixel data path. As a result, they can be affected by pixel processing that occurs within the data path. This includes:
• Noise cancellation
• Black pedestal adjustment
• Lens and color shading correction These effects can be eliminated by the following register settings:
• R0x30CA−B[0] = 1
• R0x31E0−1[0] = 0
• R0x301A−B[3] = 0 (enable writes to data pedestal)
• R0x301E−F = 0x0000 (set data pedestal to 0)
• R0x3780[15] = 0 (turn off lens/color shading correction) Solid Color Test Pattern In this mode, all pixel data is replaced by fixed Bayer pattern test data. The intensity of each pixel is set by its associated test data register (test_data_red, test_data_greenR, test_data_blue, test_data_greenB).

the full height of the output image. Figure 56. 100% Color Bars Test Pattern that, if the window is higher.

Figure 61. Test Cursor Behavior with Image Orientation

have the separation specified below.

1. Turn on VDD_IO power supply.
2. After 1–500 ms, turn on VDD and VDD_HiSPi
3. After 1–500 ms, turn on VDD_PLL and
4. After 1–500 ms, turn on VDD_TX power supply
5. After the last power supply is stable, enable
6. Assert RESET_BAR for at least 1ms.
7. Wait 2700 EXTCLKs for internal initialization
8. Configure PLL, output, and image settings to
9. Set mode_select = 1 (R0x0100).
10. Wait 1 ms for the PLL to lock before streaming

Figure 62. Power−Up Sequence Table 22. POWER−UP SEQUENCE NOTE: Digital supplies must be turned on before analog supplies. time or have the separation specified below.

1. Disable streaming if output is active by setting
2. The soft standby state is reached after the current
3. Assert hard reset by setting RESET_BAR to a
4. After 1–500 ms, turn off VDD and VDD_HiSPi
5. After 1–500 ms, turn off VDD_IO power supply.

needed. Register values are retained in the soft standby state. optionally to return all register values back to the default.

1. Disable streaming if output is active by setting
2. The soft standby state is reached after the current
3. Follow the soft standby sequence listed above.
4. Set software_reset = 1 (R0x0103) to start the

internal initialization sequence.

1. After 2700 EXTCLKs, the internal initialization

Figure 65. Soft Standby and Soft Reset

2700 EXTCLKs

Figure 66. Quantum Efficiency

Table 24. 11.4/C0053 CHIEF RAY ANGLE

Table 25. 25/C0053 CHIEF RAY ANGLE

1. Set the register bit field R0x301A[5] = 1.
2. Read the register bit fields R0x31FA[11:9].
3. Determine the CRA value according to Table 26.

Table 26. CRA VALUE

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ELECTRICAL CHARACTERISTICS

Table 27. DC ELECTRICAL DEFINITIONS AND CHARACTERISTICS performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 28. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.

Figure 67. Two−Wire Serial Bus Timing Parameters Note: Read sequence: For an 8−bit READ, read waveforms start after WRITE command and register address are issued. Table 29. TWO−WIRE SERIAL REGISTER INTERFACE ELECTRICAL CHARACTERISTICS Table 30. TWO−WIRE SERIAL REGISTER INTERFACE TIMING SPECIFICATION

Figure 68. I/O Timing Diagram Table 31. I/O PARAMETERS

Table 32. I/O TIMING Table 33. POWER SUPPLY AND OPERATING TEMPERATURE

1. Where ‘n’ is the number of PHYs
2. Specification values may be exceeded when outside this temperature range.

Table 34. SLVS ELECTRICAL DC SPECIFICATION

Table 35. SLVS ELECTRICAL TIMING SPECIFICATION

1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.
2. Taken from the 0V crossing point with the DLL off.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates

so the rise and fall times do not exceed the maximum 0.3 UI.

1. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
2. The absolute skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
3. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two

CM point. Note that differential skew also is related to the /C0068VCM_AC spec which also must not be exceeded. to 1.8 V the common−mode is elevated to around 0.9 V . Table 36. HiVCM POWER SUPPLY AND OPERATING TEMPERATURES

1. Where ‘n’ is the number of PHYs
2. Specification values may be exceeded when outside this temperature range.

Table 37. HiVCM ELECTRICAL VOLTAGE AND IMPEDANCE SPECIFICATION Table 38. HiVCM ELECTRICAL AC SPECIFICATION

1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.
2. Taken from the 0 V crossing point with the DLL off.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates

so the rise and fall times do not exceed the maximum 0.3 UI.

1. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
2. The absolute skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
3. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two

CM point. Note that differential skew also is related to the /C0068VCM_AC spec which also must not be exceeded. Vob and VCM with voltmeters for both Logic 1 and Logic 0.

Figure 69. Single−Ended and Differential Signals Figure 70. DC Test Circuit Both VOD and VCM are measured for all output channels.

1. Timing measurements are to be taken using the
2. Rise and fall times are measured between 20% to
3. Mean Clock−to−Data skew should be measured

0.5 UI with the difference being the

Clock−to−Data Skew (see Equation 25).

Figure 76. 48−Pin ILCC Package Outline Drawing ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries i n the United States and/or other countries. laws and is not for resale in any manner. A−Pix is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.