MT9F002

MT9F002 ONSEMI | Alldatasheet

Document overview

• Manufacturer or author: ON Semiconductor
• PDF pages: 93

Technical content

Features

MT9F002 DS Rev. H Pub. 6/15 EN 1 ©Semiconductor Components Industries, LLC 2015, 1/2.3-Inch 14 Mp CMOS Digital Image Sensor MT9F002 Data Sheet, Rev. H For the latest data sheet, please visit: www.onsemi.com

• 1.4 m pixel with ON Semiconductor A-Pix™ technology  Simple two-wire serial interface  Auto black level calibration  Full HD support at 60 fps for maximum video performance  20 percent extra image array area in full HD to enable electronic image stabilization (EIS).  Support for external mechanical shutter  Support for external LED or xenon flash  High frame rate preview mode with arbitrary down- size scaling from maximum resolution  Programmable controls: gain, horizontal and vertical blanking, frame size/rate, exposure, left–right and top–bottom image reversal, window size, and panning  Data interfaces: parallel or four-lane serial high- speed pixel interface (HiSPi™) differential signaling (SLVS)  On-chip phase-locked loop (PLL) oscillator  Bayer pattern downsize scaler

Applications

 Digital video cameras  Digital still cameras General Description The ON Semiconductor MT9F002 is a 1/2.3-inch CMOS active-pixel digital imaging sensor with an active pixel array of 4608H x 3288V (4640H x 3320V including border pixels). It can support 14-megapixel (4384H x 3288V) digital still images and a 1080p plus additional 20 percent pixels for electronic image stabi- lization (4608H x 2592V) in digital video mode. The MT9F002 sensor is programmable through a simple two-wire serial interface, and has low power consump- tion. Table 1: Key Performance Parameters Parameter Value Optical format 1/2.3-inch (4:3) Active pixels and imager size

• 4608H x 3288V: (entire array): 6.451mm (H) x 4.603mm (V), 7.925mm diagonal
• 4384H x 3288V (4:3, still mode): 6.138mm (H) x 4.603mm (V), 7.672mm diagonal
• 4608H x 2592V (16:9, video mode): 6.451mm (H) x 3.629mm (V), 7.402mm diagonal Pixel size 1.4 m x 1.4m Chief ray angle 0°, 11.4°, and 25° Color filter array RGB Bayer pattern Shutter type Electronic rolling shutter (ERS) with global reset release (GRR) Input clock frequency 2–64 MHz Maxi- mum data rate Parallel 96 Mp/s at 96 MHz PIXCLK HiSPi (4-lane) 700 Mbps/lane Frame rate 14M resolution (4384H x 3288V) Programmable up to 13.7 fps for HiSPi I/F, 6.3 fps for parallel I/F Preview VGA mode • 30 fps with binning
• 60 fps with skip2bin2 1080p mode:
• 60 fps using HiSPi interface 2304H x 1296V (1080p +20%EIS)
• 30 fps using parallel interface 2256H x 1268V (1080p +17%EIS) ADC resolution 12-bit, on-chip Responsivity 0.724 V/lux-sec (550nm) Dynamic range 65.3 dB SNR MAX 35.5 dB Supply voltage I/O Digital 1.7–1.9 V (1.8 V nominal) or 2.4–3.1 V (2.8 V nominal) Digital 1.7–1.9 V (1.8 V nominal) Analog 2.7–3.1 V (2.8 V nominal) HiSPi PHY HiSPi I/O (SLVS) HiSPi I/O (HiVCM) 1.7–1.9 V (1.8 V nominal) 0.3 - 0.9 V (0.4 or 0.8 V nominal) 1.7–1.9 V (1.8 V nominal) Power Con- sump- tion Full resolution 13.65 fps (HiSPi serial I/F , 12-bit) 724 mW 1080p60 (HiSPi serial I/F, 10-bit) XYbin2: 596 mW 1080p30 (HiSPi serial I/F, 10-bit) XYbin2: 443 mW Package 48-pin iLCC (10 mm x 10 mm) and bare die Operating temperature –30°C to +70°C (at junction)

MT9F002 DS Rev. H Pub. 6/15 EN 2 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor

Ordering Information

Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description MT9F002I12STCV-DP RGB, 0deg CRA, HiSPi, iLCC Package Drypack, Protective Film MT9F002I12-N4000-DP RGB, 12deg CRA, HiSPi, iLCC Package Drypack, Protective Film MT9F002I12STCVD3-GEVK 0deg CRA, HiSPi, Demo Kit MT9F002I12STCVH-GEVB 0deg CRA, HiSPi, Head Board MT9F002I12-N4000D-GEVK 12deg CRA, HiSPi, Demo Kit MT9F002I12-N4000H-GEVB 12deg CRA, HiSPi, Head Board

MT9F002 DS Rev. H Pub. 6/15 EN 3 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Table of Contents Table of Contents

MT9F002 DS Rev. H Pub. 6/15 EN 6 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor List of Tables List of Tables

MT9F002 DS Rev. H Pub. 6/15 EN 7 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor General Description General Description The MT9F002 digital image sensor features ON Semiconductor’ s breakthrough low-noise CMOS imaging technology that achieves near-CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. When operated in its default 4:3 still-mode, the sensor generates a full resolution (4384x3288)image at 13 frames per second (fps) using the HiSPi serial interface. An on-chip analog-to-digital converter (ADC) generates a 12-bit value for each pixel. Functional Overview The MT9F002 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal clocks from a single master input clock running between 2 and 64 MHz. The maximum output pixel rate is 220 Mp/s for serial HiSPi I/F and 96 Mp/s for parallel I/F , corre- sponding to a pixel clock rate of 220 MHz and 96 MHz, respectively. A block diagram of the sensor is shown in Figure 1. Figure 1: Block Diagram The core of the sensor is a 14Mp active-pixel array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row inte- grate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an ADC. The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The pixel array contains optically active and light-shielded (“dark”) pixels. The dark pixels are used to provide data for on-chip offset-correction algorithms (“black level” control). PLL Timing and Control Registers Pixel Array Column Amplifiers Column Amplifiers Row Drivers Voltage Reference Black Level Correction Scaler Limiter Output Buffer/FIFO Lens Shading Correction Digital Gain Data Pedestal I2C EXTCLK Analog Core Core Data Path Test Pattern Generator Parallel I/O: PIXCLK FV, LV, DOUT[11:0] Serial HiSPi: SLVSC P/N, SLVS[3:0] P/N Output Data Path PGA PGA ADC ADC 12 bits 12 bits 12 bits 12 bits

MT9F002 DS Rev. H Pub. 6/15 EN 10 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Operating Modes Operating Modes By default, the MT9F002 powers up with the serial pixel data interface enabled. The sensor can operate in serial HiSPi or parallel mode. For low-noise operation, the MT9F002 requires separate power supplies for analog and digital power. Incoming digital and analog ground conductors should be placed in such a way that coupling between the two are minimized. Both power supply rails should also be routed in such a way that noise coupling between the two supplies and ground is minimized. Caution ON Semiconductor does not recommend the use of inductance filters on the power supplies or output signals. Figure 5: Typical Configuration: Serial Four-Lane HiSPi Interface Notes: 1. All power supplies should be adequately de coupled. ON Semiconductor recommends having 1.0F and 0.1F decoupling capacitors for every power supply. 2. ON Semiconductor recommends a resistor value of 1.5k , but a greater value may be used for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The GPI pins can be statically pulled HIGH or LO W and can be programmed to perform special func- tions (TRIGGER/VD, OE_BAR, SADDR, STANDBY) to be dynamically controlled. GPI pads can be left floating, when not used. 5. V PP, which is not shown in Figure 5, is left unconnected during normal operation. VDD_IO V DD_TX V DD_PLLVDD VAA VDD VDD_TX VAA VAA_PIX Master clock (2–64 MHz) SDATA SCLK RESET_BAR TEST EXTCLK DGND AGND Digital ground Analog ground Digital Core power1 HiSPi PHY I/O power1, 10 Analog power1 To controller From controller VDD_IO VDD_PLL PLL power1 Digital I/O power1 1.5kΩ2 1.5kΩ2, 3 Analog power1 VAA_PIX SLVSC_N SLVSC_P SLVS_0P SLVS_0N SLVS_1P SLVS_1N SLVS_2P SLVS_2N SLVS_3P SLVS_3N FLASH SHUTTER GPI[3:0]4 VDD_HISPI

MT9F002 DS Rev. H Pub. 6/15 EN 11 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Operating Modes 6. The parallel interface output pads can be left unconnected when the serial output interface is used. 7. ON Semiconductor recommends that 0.1 F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- out and design considerations. Check the MT9F002 demo headboard schematics for circuit recom- mendations. 8. TEST signals must be tied to D GND for normal sensor operation. 9. ON Semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 10. For serial HiSPi HiVCM mode, set register bit R0x306E[9] = 1 and V DD_TX = VDD_IO = 1.8V. Figure 6: Typical Configuration: Parallel Pixel Data Interface Notes: 1. All power supplies should be adequately de coupled. ON Semiconductor recommends having 1.0F and 0.1F decoupling capacitors for every power supply. 2. ON Semiconductor recommends a resistor value of 1.5k , but a greater value may be used for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The GPI pins can be statically pulled HIGH or LO W and can be programmed to perform special func- tions (TRIGGER/VD, OE_BAR, SADDR, STANDBY) to be dynamically controlled. GPI pads can be left floating, when not used. 5. V PP, which is not shown in Figure 6, is left unconnected during normal operation. 6. The serial interface output pads can be left unco nnected when the parallel output interface is used. 7. ON Semiconductor recommends that 0.1 F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- out and design considerations. Check the MT9F002 demo headboard schematics for circuit recom- mendations. 8. TEST signals must be tied to D GND for normal sensor operation. VAA_PIX VDD Master clock (2–64 MHz) SDATA SCLK RESET_BAR TEST FLASH FRAME_VALID SHUTTER DOUT [11:0]EXTCLK DGND AGND Digital ground Analog ground Digital core power1 To controller parallel port From Controller LINE_VALID PIXCLK VDD_IO GPI[3:0]4 Digital I/O power1 1.5kΩ2 1.5kΩ2, 3 VDD_IO V DD_PLLVDD VAA VAA VAA_PIX Analog power1 VDD_PLL PLL power1 Analog power1

MT9F002 DS Rev. H Pub. 6/15 EN 12 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Operating Modes 9. ON Semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized.

MT9F002 DS Rev. H Pub. 6/15 EN 13 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Signal Descriptions Signal Descriptions Table 3 provides signal descriptions for MT9F002 die. For pad location and aperture information, refer to the MT9F002 die data sheet. Table 3: Signal Descriptions Signal Type Description EXTCLK Input Master clock input, 2-64 MHz. RESET_BAR Input Asynchronous active LOW reset. When asserted, data output stops and all internal registers are restored to their factory default settings. SCLK Input Serial clock for access to control and status registers. GPI[3:0] Input General purpose inputs. After reset, these pads are powered-down by default; this means that it is not necessary to bond to these pads. Any of these pads can be programmed (through register R0x3026) to provide hardware control of the standby, output enable, SADDR select, shutter trigger or slave mode trigger (VD) function. Can be left floating if not used. TEST Input Enable manufacturing test modes. Tie to DGND for normal sensor operation. SDATA I/O Serial data from READs and WRITEs to control and status registers. VPP Supply Disconnect pad for normal operation. Power supply used to program one-time programmable (OTP) memory. Manufacturing use only. VDD_HiSPi Supply HiSPi PHY power supply. Digital power supply for the HiSPi serial data interface. This should be tied to VDD. VDD_TX Supply Digital power supply for the HiSPi I/O. For HiSPi SLVS mode, set register bit R0x306E[9] = 0 (default), and VDD_TX to 0.4V. For HiSPi HiVCM mode, set register bit R0x306E[9] = 1, and VDD_TX = VDD_IO. V AA Supply Analog power supply. VAA_PIX Supply Analog power supply for the pixel array. AGND Supply Analog ground. VDD Supply Digital power supply. VDD_IO Supply I/O power supply. DGND Supply Common ground for digital and I/O. VDD_PLL Supply PLL power supply. SLVS_0P Output Lane 1 differential HiSPi (SLVS) serial data (positive). Qualified by the SLVS serial clock. SLVS_0N Output Lane 1 differential HiSPi (SLVS) serial data (negative). Qualified by the SLVS serial clock. SLVS_1P Output Lane 2 differential HiSPi (SLVS) serial data (positive). Qualified by the SLVS serial clock. SLVS_1N Output Lane 2 differential HiSPi (SLVS) serial data (negative). Qualified by the SLVS serial clock. SLVS_2P Output Lane 3 differential HiSPi (SLVS) serial data (positive). Qualified by the SLVS serial clock. SLVS_2N Output Lane 3 differential HiSPi (SLVS) serial data (negative). Qualified by the SLVS serial clock. SLVS_3P Output Lane 4 differential HiSPi (SLVS) serial data (positive). Qualified by the SLVS serial clock.

MT9F002 DS Rev. H Pub. 6/15 EN 14 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Signal Descriptions Figure 7: 48-Pin iLCC HiSPi Package Pinout Diagram SLVS_3N Output Lane 4 differential HiSPi (SLVS) serial data (negative). Qualified by the SLVS serial clock. SLVS_CP Output Differential HiSPi (SLVS) serial clock (positive). Qualified by the SLVS serial clock. SLVS_CN Output Differential HiSPi (SLVS) serial clock (negative). Qualified by the SLVS serial clock. LINE_VALID Output LINE_VALID (LV) output. Qualified by PIXCLK. FRAME_VALID Output FRAME_VALID (FV) output. Qualified by PIXCLK. DOUT[11:0] Output Parallel pixel data output. Qualified by PIXCLK. PIXCLK Output Pixel clock. Used to qualify the LV, FV, and DOUT[11:0] outputs. FLASH Output Flash output. Synchronization pulse for external light source. Can be left floating if not used. SHUTTER Output Control for external mechanical shutter. Can be left floating if not used. Table 3: Signal Descriptions (continued) Signal Type Description 123456 4 84 7 4 64 5 44 43 19 20 21 22 23 24 25 26 27 28 29 30 AGND VAA NC VAA AGND VAA_PIX VAA_PIX NC NC V AA AGND VDD_HiSPi VDD_IO DGND VDD EXTCLK VDD DGND VDD_IO SDATA SCLK TEST RESET_BAR VDD DGND VDD_IO GPI0 GPI1 GPI2 GPI3 SHUTTER FLASH V DD_PLL VPP VDD_TX SLVS_0N SLVS_0P SLVS_1N SLVS_1P SLVS_CN SLVS_CP SLVS_2N SLVS_2P SLVS_3N SLVS_3P D GND NC DGND

MT9F002 DS Rev. H Pub. 6/15 EN 15 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Output Data Format Output Data Format Pixel Data Interface The MT9F002 reads data out of the pixel array in a progressive scan over a High Speed serial data interface, or parallel data interface. RAW8, RAW10, and RAW12 image data formats are supported. Figure 8: Data Formats High Speed Serial Pixel Data Interface The High Speed Serial Pixel (HiSPi)TM interface uses four data and one clock low voltage differential signaling (SLVS) outputs. S L V S _ C P S L V S _ C N S L V S _ 0 P S L V S _ 0 N S L V S _ 1 P S L V S _ 1 N S L V S _ 2 P S L V S _ 2 N S L V S _ 3 P S L V S _ 3 N The HiSPi interface supports the following protocols: Streaming-S and Packetized-SP . The streaming protocol conforms to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. The packetized protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. HiSPi Streaming Mode Protocol Layer The protocol layer is positioned between the output data path of the sensor and the physical layer. The main functions of the protocol layer are generating sync codes, formatting pixel data, inserting horizontal/vertical blanking codes, and distributing pixel data over defined data lanes. The HiSPi interface can only be configured when the sensor is in standby. This includes configuring the interface to transmit across 1, 2, or all 4 data lanes. D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RAW12 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X RAW10 D7 D6 D5 D4 D3 D2 D1 D0 X X X X RAW8 Cd

MT9F002 DS Rev. H Pub. 6/15 EN 16 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor HiSPi Physical Layer Protocol Fundamentals Referring to Figure 9, it can be seen that a SYNC code is inserted in the serial data stream prior to each line of image data. The streaming protocol will insert a SYNC code to transmit each active data line and vertical blanking lines. The packetized protocol will transmit a SYNC code to note the start and end of each row. The packetized protocol uses sync a “Start of Frame” (SOF) sync code at the start of a frame and a “Start of Line” (SOL) sync code at the start of a line within the frame. The protocol will also transmit an “End of Frame” (EOF) at the end of a frame and an “End of Line” (EOL) sync code at the end of a row within the frame Figure 9: Steaming vs . Packetized Transmission Note: See the High-Speed Serial Pixel (HiSPi)™ Protocol Specification V1.00.00 for HiSPi details. HiSPi Physical Layer The HiSPi physical layer is partitioned into blocks of four data lanes and an associated clock lane. Any reference to the PHY in the remainder of this document is referring to this minimum building block. The HiSPi PHY uses a low voltage serial differential output. The HiSPi PHY drivers use a simple current steering driver scheme with two outputs that are complementary to each other (V OA and VOB). It is intended that these drivers be attached to short-length 100 differential interconnect to a receiver with a 100 termination. CL represents the total parasitic excess capacitance loading of the receiver and the interconnect. There are two standards:  Scalable Low Voltage Serial (SLVS) which has low amplitude and common-mode voltage (VCM) but scalable using an external supply.  High VCM scalable serial interface (HiVCM), which has larger scalable amplitude and a high common-mode voltage.

MT9F002 DS Rev. H Pub. 6/15 EN 17 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Comparison of SLVS and HiVCM Comparison of SLVS and HiVCM Here is a comparison of the differences between SLVS and HiVCM. Notes: 1. These are nominal values 2. Power from load driving stage, digital/se rializer logic (VDD_HiSPi) not included. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. The four Data lanes are 90 degrees out of phase with the Clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. Figure 10 shows the configuration between the HiSPi transmitter and the receiver. Figure 10: HiSPi Transmitter and Receiver Interface Block Diagram The PHY will serialize a 10-, 12-, 14- or 16-bit data word and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of clock. Figure 11 shows bit transmission. In this example, the word is transmitted in order of MSB to LSB. The receiver latches data at the rising and falling edge of the clock. Table 4: SLVS and HiVCM Comparison Parameter HiVCM SLVS Typical Differential Amplitude1 280mV 200mV Typical Common Mode1 0.9V 200mV Typical Power Consumption2 45mW 4mW Transmission Distance Longer distance Short distance LVDS FPGA Receiver Compatible Yes No A camera containing the HiSPi transmitter A host (DSP) containing the HiSPi receiver DATA_P DATA_N DATA2_P DATA2_N DATA3_P DATA3_N DATA4_P DATA4_N CLK_P CLK_N Tx PHY0 Rx PHY0 DATA_P DATA_N DATA2_P DATA2_N DATA3_P DATA3_N DATA4_P DATA4_N CLK_P CLK_N

MT9F002 DS Rev. H Pub. 6/15 EN 19 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Comparison of SLVS and HiVCM Figure 13: Delaying the clock_lane with Respect to data_lane Figure 14: Delaying data_lane with Respect to the clock_lane Note: See the High-Speed Serial Pixel (HiSPi)™ Ph ysical Layer Specification V2.00.00 for details. Parallel Pixel Data Interface MT9F002 image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking, as shown in Figure 15. The amount of hori- zontal blanking and vertical blanking is programmable; LV is HIGH during the shaded region of the figure. FV timing is described in the “Output Data Timing (Parallel Pixel Data Interface)”. dataN (de lN = 000) cp ( delclock = 000) cp (d elclock = 00 1) cp (delclock = 010) cp (de lclock = 011) cp ( delclock = 100) cp (d elcloc k = 1 01) c p (delclock = 110) cp ( delclock =111) increasing delclock_[2:0] increases clock delay 1 UI

1 UItDLLSTEP

cp ( delclock = 000) dataN (delN = 000) dataN(delN = 001) dataNdelN = 010) dataN(delN = 011) dataN(delN = 100) dataN(delN = 101) dataN( delN = 1 10 ) dataN( delN = 1 11 ) increasing delN_[2:0] increases data delay

MT9F002 DS Rev. H Pub. 6/15 EN 20 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Comparison of SLVS and HiVCM Figure 15: Spatial Illustration of Image Readout VALID IMAGE HORIZONTAL BLANKING VERTICAL BLANKING VERTICAL/HORIZONTAL BLANKING

MT9F002 DS Rev. H Pub. 6/15 EN 22 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Comparison of SLVS and HiVCM Table 5: Common Sensor Readout Modes Key Readout Modes Output Resolution Aspect Ratio DFOV: 7.67 mm (%) Subsampling Mode Frame Rate ADC Effective Bit-Depth Data Rate (Mbps/Lane) 14M Capture 4384H x 3288V (4:3) 100 n/a 13.7 12 660 1080p +20% EIS (3Mp) Video 2304H x 1296V (16:9) 96 x: Bin2 y: Bin2 60 10 550 2304H x 1296V (16:9) 96 x: Bin2 y: Bin2 30 10 275 720p +20%EIS (1.3Mp) Video 1536H x 864V (16:9) 64 x: Bin2 y: Bin2 60 10 550 1536H x 864V (16:9) 64 x: Bin2 y: Bin2 30 10 275 VGA Video (High Quality) 1096H x 822V (4:3) 100 x: Skip2Bin2 y: Bin4 60 10 550 EVF1 - Preview (Low Power) 1096H x 822V (4:3) 100 x: Skip2Bin2 y: Bin4 30 10 275 EVF2 - Preview (Low Power) 1152H x 648V (16:9) 96 x: Skip2Bin2 y: Bin4 30 10 275

MT9F002 DS Rev. H Pub. 6/15 EN 23 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Two-Wire Serial Register Interface The two-wire serial interface bus enables read/write access to control and status regis- ters within the MT9F002. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (S CLK) that is an input to the sensor and is used to synchronize trans- fers. Data is transferred between the master and the slave on a bidirectional signal DATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or master device can drive SDATA LOW—the interface protocol determines which device is allowed to drive SDATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the MT9F002 uses SCLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low- level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no-) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both S CLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for both the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The default slave addresses used by the MT9F002 sensor are 0x20 (write address) and 0x21 (read address). Alternative slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the SADDR signal through the GPI pin.

MT9F002 DS Rev. H Pub. 6/15 EN 24 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Alternate slave addresses can also be programmed through the i2c_ids register (R0x31FC-31FD). Note that this register needs to be unlocked through reset_regis- ter_lock_reg (R0x301A[3]) before is can be written to.. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the S CLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl- edge bit by driving SDATA LOW . As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indi- cates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave’ s internal register address is automatically incre- mented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit.

MT9F002 DS Rev. H Pub. 6/15 EN 27 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Sequential WRITE, Start at Random Location This sequence (Figure 23) starts in the same way as the single WRITE to random location (Figure 22 on page 26). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until “L” bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 23: Sequential WRITE, Start at Random Location Slave Address 0S A Reg Address[15:8] A A Reg Address[7:0] A Previous Reg Address, N Reg Address, M M+1 M+2 M+1 M+3 A A A M+L-2 M+L-1 M+L A A P Write Data Write Data Write Data Write DataWrite Data

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Programming Restrictions MT9F002 DS Rev. H Pub. 6/15 EN 28 ©Semiconductor Components Industries, LLC,2015. Programming Restrictions The following sections list programming rules that must be adhered to for correct opera- tion of the MT9F002. Refer to the MT9F002 Register Reference document for register programming details. X Address Restrictions The minimum column address available for the sensor is 24. The maximum value is 4647. Effect of Scaler on Legal Range of Output Sizes When the scaler is enabled, it is necessary to adjust the values of x_output_size and y_output_size to match the image size generated by the scaler. The MT9F002 will operate incorrectly if the x_output_size and y_output_size are significantly larger than the output image. To understand the reason for this, consider the situation where the sensor is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the number of pixels in each direction). This situation is shown in Figure 24. Figure 24: Effect of Limiter on the Data Path In Figure 24, three different stages in the data path (see “Timing Specifications” on page 71) are shown. The first stage is the output of the sensor core. The core is running at full resolution and x_output_size is set to match the active array size. The LV signal is asserted once per row and remains asserted for N pixel times. The PIXEL_VALID signal toggles with the same timing as LV , indicating that all pixels in the row are valid. The second stage is the output of the scaler, when the scaler is set to reduce the image size by one-half in each dimension. The effect of the scaler is to combine groups of pixels. Therefore, the row time remains the same, but only half the pixels out of the scaler are valid. This is signaled by transitions in PIXEL_VALID. Overall, PIXEL_VALID is asserted for (N/2) pixel times per row. Table 6: Definitions for Programming Rules Name Definition xskip xskip = 1 if x_odd_inc = 1; xskip = 2 if x_odd_inc = 3; xskip = 4 if x_odd_inc = 7 yskip yskip = 1 if y_odd_inc = 1; yskip = 2 if y_odd_inc = 3; yskip = 4 if y_odd_inc = 7; yskip = 8 if y_odd_inc = 15; yskip = 16 if y_odd_inc = 31; yskip = 32 if y_odd_inc = 63 Core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 LINE_VALID Scaler output: scaled to half size LINE_VALID PIXEL_VALID Limiter output: scaled to half size, x_output_size = x_addr_end - x_addr_start + 1 LINE_VALID PIXEL_VALID PIXEL_VALID

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Programming Restrictions MT9F002 DS Rev. H Pub. 6/15 EN 30 ©Semiconductor Components Industries, LLC,2015. Output Data Timing The output FIFO acts as a boundary between two clock domains. Data is written to the FIFO in the VT (video timing) clock domain. Data is read out of the FIFO in the OP (output) clock domain. When the scaler is disabled, the data rate in the VT clock domain is constant and uniform during the active period of each pixel array row readout. When the scaler is enabled, the data rate in the VT clock domain becomes intermittent, corresponding to the data reduction performed by the scaler. A key constraint when configuring the clock for the output FIFO is that the frame rate out of the FIFO must exactly match the frame rate into the FIFO. When the scaler is disabled, this constraint can be met by imposing the rule that the row time on the serial data stream must be greater than or equal to the row time at the pixel array. The row time on the serial data stream is calculated from the x_output_size and the data_format (8, 10, or 12 bits per pixel), and must include the time taken in the serial data stream for start of frame/row, end of row/frame and checksum symbols. Caution If this constraint is not met, the FIFO will either underrun or overrun. FIFO underrun or over- run is a fatal error condition that is signaled through the data path_status register (R0x306A). Changing Registers While Streaming The following registers should only be reprogrammed while the sensor is in software standby: v t _ p i x _ c l k _ d i v  vt_sys_clk_div  pre_pll_clk_div  pll_multiplier  op_pix_clk_div o p _ s y s _ c l k _ d i v Programming Restrictions When Using Global Reset Interactions between the registers that control the global reset imposes some program- ming restrictions on the way in which they are used; these are discussed in "Global Reset" on page 58.

MT9F002 DS Rev. H Pub. 6/15 EN 31 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Control of the Signal Interface Control of the Signal Interface This section describes the operation of the signal interface in all functional modes. Serial Register Interface The serial register interface uses these signals: S CLK S DATA S ADDR (through the GPI pin) SCLK is an input-only signal and must always be driven to a valid logic level for correct operation; if the driving device can place this signal in High-Z, an external pull-up resistor should be connected on this signal. SDATA is a bidirectional signal. An external pull-up resistor should be connected on this signal. SADDR is a signal that can be optionally enabled and controlled by a GPI pin to select an alternate slave address. These slave addresses can also be programmed through R0x31FC. This interface is described in detail in “Two-Wire Serial Register Interface” on page 23. Parallel Pixel Data Interface The parallel pixel data interface uses these output-only signals: F V L V P I X C L K OUT[11:0] The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. Table 8 on page 32 shows the recommended settings. When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. Set reset_register[12] to disable the serializer while in parallel output mode. Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchro- nously between the driven and High-Z under pin or register control, as shown in Table 7. Selection of a pin to use for the OE_N function is described in "General Purpose Inputs" on page 35. Table 7: Output Enable Control OE_N Pin Drive Signals R0x301A–B[6] Description Disabled 0 Interface High-Z Disabled 1 Interface driven 1 0 Interface High-Z X1 I n t e r f a c e d r i v e n 0X I n t e r f a c e d r i v e n

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Control of the Signal Interface MT9F002 DS Rev. H Pub. 6/15 EN 32 ©Semiconductor Components Industries, LLC,2015. Configuration of the Pixel Data Interface Fields in R0x301A are used to configure the operation of the pixel data interface. The supported combinations are shown in Table 8. Table 8: Configuration of the Pixel Data Interface Serializer Disable R0x301 A–B[12] Parallel Enable R0x301A–B[7] Standby End-of-Frame R0x301A–B[4] Description 0 0 1 Power up default. Serial pixel data interface and its clocks are enabled. Transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 0 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of the current row readout on the parallel pixel data interface. 1 1 1 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface.

MT9F002 DS Rev. H Pub. 6/15 EN 33 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Control of the Signal Interface System States The system states of the MT9F002 are represented as a state diagram in Figure 26 and described in subsequent sections. The effect of RESET_BAR on the system state and the configuration of the PLL in the different states are shown in Table 9 on page 34. The sensor’ s operation is broken down into three separate states: hardware standby, software standby, and streaming. The transition between these states might take a certain amount of clock cycles as outlined in Table 9. Figure 26: MT9F002 System States Powered Off Streaming Powered On POR =1 RESET _BAR transitions 1 -> 0 (asynchronous from any state ) Initialization Timeout Two-wire Serial Interface Write mode_select = 0 PLL Lock PLL locked Software reset initiated (synchronous from any state) Wait for Frame End Software Standby Two-wire Serial Interface Write mode_select = 1 Two-wire Serial Interface Write software_reset = 1 Internal Initialization Hardware Standby

2700 EXTCLK

RESET_BAR = 0 POR = 0 RESET_BAR = 1 PLL not locked POR active (only if POR is on sensor) Power supplies turned off (asychronous from any state) Frame in progress

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Control of the Signal Interface MT9F002 DS Rev. H Pub. 6/15 EN 34 ©Semiconductor Components Industries, LLC,2015. Note: VCO = voltage-controlled oscillator. Power-On Reset Sequence When power is applied to the MT9F002, it enters a low-power hardware standby state. Exit from this state is controlled by the later of two events: 1. The negation of the RESET_BAR input. 2. A timeout of the internal power-on reset circuit. It is possible to hold RESET_BAR permanently de-asserted and rely upon the internal power-on reset circuit. When RESET_BAR is asserted it asynchronously resets the sensor, truncating any frame that is in progress. When the sensor leaves the hardware standby state it performs an internal initialization sequence that takes 2700 EXTCLK cycles. After this, it enters a low-power software standby state. While the initialization sequence is in progress, the MT9F002 will not respond to READ transactions on its two-wire serial interface. Therefore, a method to determine when the initialization sequence has completed is to poll a sensor register; for example, R0x0000. While the initialization sequence is in progress, the sensor will not respond to its device address and READs from the sensor will result in a NACK on the two-wire serial interface bus. When the sequence has completed, READs will return the operational value for the register (0x2800 if R0x0000 is read). When the sensor leaves software standby mode and enables the VCO, an internal delay will keep the PLL disconnected for up to 1ms so that the PLL can lock. The VCO lock time is 1ms (minimum). Soft Reset Sequence The MT9F002 can be reset under software control by writing “1” to software_reset (R0x0103). A software reset asynchronously resets the sensor, truncating any frame that is in progress. The sensor starts the internal initialization sequence, while the PLL and analog blocks are turned off. At this point, the behavior is exactly the same as for the power-on reset sequence. Table 9: RESET_BAR and PLL in System States State EXTCLKs PLL Powered off x VCO powered down POR active x Hardware standby 0 Internal initialization Software standby PLL Lock VCO powering up and locking, PLL output bypassed Streaming VCO running, PLL output active Wait for frame end

MT9F002 DS Rev. H Pub. 6/15 EN 35 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Control of the Signal Interface Signal State During Reset Table 10 on page 35 shows the state of the signal interface during hardware standby (RESET_BAR asserted) and the default state during software standby. After exit from hardware standby and before any registers within the sensor have been changed from their default power-up values. General Purpose Inputs The MT9F002 provides four general purpose inputs. After reset, the input pads associ- ated with these signals are powered down by default, allowing the pads to be left discon- nected/floating. The general purpose inputs are enabled by setting reset_register[8] (R0x301A). Once enabled, all four inputs must be driven to valid logic levels by external signals. The state of the general purpose inputs can be read through gpi_status[3:0] (R0x3026). In addition, each of the following functions can be associated with none, one, or more of the general purpose inputs so that the function can be directly controlled by a hardware input:  Output enable (see “Output Enable Control” on page 31)  Trigger/VD (slave mode) - see the sections below  Standby functions ADDR selection (see “Serial Register Interface” on page 31) Table 10: Signal State During Reset Pad Name Pad Type Hardware Standby Software Standby EXTCLK Input Enabled. Must be driven to a valid logic level.RESET_BAR (XSHUTDOWN) GPI[3:0] Powered down. Can be left disconnected/floating. TEST Enabled. Must be driven to a logic 0. SCLK Enabled. Must be pulled up or driven to a valid logic level. SDATA I/O Enabled as an input. Must be pulled up or driven to a valid logic level. LINE_VALID Output High-Z. Can be left disconnected or floating. FRAME_VALID DOUT[11:0] PIXCLK SLVS_0P SLVS_0N SLVS_1P SLVS_1N SLVS_2P SLVS_2N SLVS_3P SLVS_3N SLVS_CP SLVS_CN FLASH High-Z. Logic 0. SHUTTER

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Control of the Signal Interface MT9F002 DS Rev. H Pub. 6/15 EN 36 ©Semiconductor Components Industries, LLC,2015. The gpi_status register is used to associate a function with a general purpose input. Streaming/Standby Control The MT9F002 can be switched between its soft standby and streaming states under pin or register control, as shown in Table 11. Selection of a pin to use for the STANDBY func- tion is described in “General Purpose Inputs” on page 35. The state diagram for transi- tions between soft standby and streaming states is shown in Figure 26 on page 33. Trigger Control When the global reset feature is in use, the trigger for the sequence can be initiated either under pin or register control, as shown in Table 12. Selection of a pin to use for the TRIGGER function is described in “General Purpose Inputs” on page 35. In slave mode, the GPI pin also serves as VD signal input. Table 11: Streaming/STANDBY STANDBY Streaming R0x301A–B[2] Description Disabled 0 Soft standby Disabled 1 Streaming X0 S o f t s t a n d b y 0 1 Streaming 1X S o f t s t a n d b yTable 12: Trigger Control Trigger Global Trigger R0x3160–1[0] Description Disabled 0 Idle Disabled 1 Trigger

00 I d l e

1 X Trigger

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Control of the Signal Interface MT9F002 DS Rev. H Pub. 6/15 EN 38 ©Semiconductor Components Industries, LLC,2015. From the diagram, the clock frequencies can be calculated as follows: Note: Virtual pixel clock is used as the basis for frame timing equations. (EQ 3) Internal pixel clock used to readout the pixel array: (EQ 4) External pixel clock used to output the data: (EQ 5) Serial output clock: (EQ 6) The parameter limit register space contains registers that declare the minimum and maximum allowable values for:  The frequency allowable on each clock  The divisors that are used to control each clock. The following factors determine what are valid values, or combinations of valid values, for the divider/multiplier control registers:  The minimum/maximum frequency limits for the associated clock must be met: – pll_ip_clk_freq must be in the range 2- 24 MHz. Lower frequencies are preferred. –P L L i n t e r n a l V C O f r e q u e n c y m u s t be in the range 384-768 MHz.  The minimum/maximum value for the divider/multiplier must be met: Range for pre_pll_clk_div: 1-64.  clk_op must never run faster than clk_pixel to ensure that the output data stream is contiguous.  When the serial interface is used the clk_ op divider cannot be used; row_speed[10:8] must equal 1.  The value of op_sys_clk_div must match the bit-depth of the image when using serial interface. R0x0112-3 controls whether the pixel data interface will generate 12, 10, or 8 bits per pixel. When the pixel data interface is generating 8 bits per-pixel, op_pix_- clk_div must be programmed with the value 8. When the pixel data interface is gener- ating 10 bits per pixel, op_pix_clk_div must be programmed with the value 10. And when the pixel data interface is generating 12 bits per pixel, op_pix_clk_div must be programmed with the value 12. This is not required when using the parallel interface.  Although the PLL VCO input frequency range is advertised as 2-24 MHz, superior performance (better PLL stability) is obtained by keeping the VCO input frequency as high as possible. The usage of the output clocks is shown below: vt_pix_clk ext_clk_freq_mhz pll_multip lier 1 shift_vt_pix_clk_div+ clk_pixel ext_clk_freq_mhz pll_multip lier 1 shift_vt_pix_clk_div+ clk_op ext_clk_freq_mhz pll_multiplier op_sys_clk_freq_mhz ext_clk_freq_mhz pll_multiplier

MT9F002 DS Rev. H Pub. 6/15 EN 39 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Control of the Signal Interface  clk_pixel is used by the sensor core to control the timing of the pixel array. The sensor core produces two 10-bit pixels each clk_pixel period. The line length (line_length_pck) and fine integration time (fine_integration_time) are controlled in increments of half of the clk_pixel period.  clk_op is used to load parallel pixel data from the output FIFO. The output FIFO generates one pixel each clk_op period. This clock also equals the output PIXCLK.  Master clock frequency corr esponds to vt_pix_clk/2.  Serial clock (op_sys_clk) used for the serial output interface. Programming the PLL Divisors The PLL divisors must be programmed while the MT9F002 is in the software standby state. After programming the divisors, wait for the VCO lock time before enabling the PLL. The PLL is enabled by entering the streaming state. An external timer will need to delay the entrance of the streaming mode by 1 millisecond so that the PLL can lock. The effect of programming the PLL divisors while the MT9F002 is in the streaming state is undefined. Clock Control The MT9F002 uses an aggressive clock-gating methodology to reduce power consump- tion. The clocked logic is divided into a number of separate domains, each of which is only clocked when required. When the MT9F002 enters a low-power state, almost all of the internal clocks are stopped. The only exception is that a small amount of logic is clocked so that the two- wire serial interface continues to respond to READ and WRITE requests.

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor MT9F002 DS Rev. H Pub. 6/15 EN 40 ©Semiconductor Components Industries, LLC,2015. The MT9F002 supports scaling capability. Scaling is a “zoom out” operation to reduce the size of the output image while covering the same extent as the original image. That is, low resolution images can be generated with full field-of-view. Each scaled output pixel is calculated by taking a weighted average of a group input pixels which is composed of neighboring pixels. The input and output of the scaler is in Bayer format. When compared to skipping, scaling is advantageous because it uses all pixel values to calculate the output image which helps avoid aliasing. Also, it is also more convenient than binning because the scale factor varies smoothly and the user is not limited to certain ratios of size reduction. The MT9F002 sensor is capable of horizontal scaling and full (horizontal and vertical) scaling. The scaling factor is programmable in 1/16 steps and is determined by. (EQ 7) scale_n is fixed at 16. scale_m is adjustable with R0x0404 Legal values for m are 16 through 128. The user has the ability to scale from Scaler Example When horizontal and vertical scaling is enabled for a 1:2 scale factor, an image is reduced by half in both the horizontal and vertical directions. This results in an output image that is one-fourth of the original image size. This can be achieved with the following register settings: R0x0400 = 0x0002 // horizontal and vertical scaling mode R0x0402 = 0x0020 // scale factor m = 32 Shading Correction Lenses tend to produce images whose brightness is significantly attenuated near the edges. There are also other factors causing color plane nonuniformity in images captured by image sensors. The cumulative result of all these factors is known as image shading. The MT9F002 has an embedded shading correction module that can be programmed to counter the shading effects on each individual Red, GreenB, GreenR, and Blue color signal. ScaleFactor = scale_n

MT9F002 DS Rev. H Pub. 6/15 EN 41 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Color-dependent solutions are calibrated using the sensor, lens system and an image of an evenly illuminated, featureless gray calibration field. From the resulting image, register values for the color correction function (coefficients) can be derived. The correction functions can then be applied to each pixel value to equalize the response across the image as follows: (EQ 8) where P are the pixel values and f is the color dependent correction functions for each color channel. Each function includes a set of color-dependent coefficients defined by registers R0x3600–3726. The function's origin is the center point of the function used in the calcu- lation of the coefficients. Using an origin near the central point of symmetry of the sensor response provides the best results. The center point of the function is determined by ORIGIN_C (R0x3782) and ORIGIN_R (R0x3784) and can be used to counter an offset in the system lens from the center of the sensor array. Pcorrected row, col = Psensor(row,col) * f(row,col)

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Sensor Readout Configuration MT9F002 DS Rev. H Pub. 6/15 EN 42 ©Semiconductor Components Industries, LLC,2015. Sensor Readout Configuration Image Acquisition Modes The MT9F002 supports two image acquisition modes: 1. Electronic rolling shutter (ERS) mode This is the normal mode of operation. When the MT9F002 is streaming; it generates frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When the ERS is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate inci- dent light. The integration (exposure) time is controlled by varying the time between row reset and row readout. For each row in a frame, the time between row reset and row readout is fixed, leading to a uniform integration time across the frame. When the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integra- tion time in such a way that the stream of output frames from the MT9F002 switches cleanly from the old integration time to the new while only generating frames with uniform integration. See “Changes to Integration Time” in the MT9F002 Register Ref- erence. 2. Global reset mode This mode can be used to acquire a single image at the current resolution. In this mode, the end point of the pixel integration time is controlled by an external electro- mechanical shutter, and the MT9F002 provides control signals to interface to that shutter. The operation of this mode is described in detail in "Global Reset" on page 58. The benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particu- larly at low frame rates, because an ERS image effectively integrates each row of the pixel array at a different point in time. Window Control The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_ad- dr_end, and y_addr_end registers. For both parallel and serial HiSPi interfaces, the output image size is controlled by the x_output_size and y_output_size registers. Pixel Border The default settings of the sensor provide a 4608H x3288V image. A border of up to 8 pixels (4 in binning) on each edge can be enabled by reprogramming the x_addr_start, y_addr_start, x_addr_end, y_addr_end, x_output_size, and y_output_size registers accordingly. This provides a total active pixel array of 4640H x 3320V including border pixels.

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Sensor Readout Configuration MT9F002 DS Rev. H Pub. 6/15 EN 48 ©Semiconductor Components Industries, LLC,2015. Figure 38: Pixel Readout (x_odd_inc=7, y_odd_inc=31) Programming Restrictions When Subsampling When subsampling is enabled as a viewfinder mode and the sensor is switched back and forth between full resolution and subsampling, it is recommended that line_length_pck be kept constant between the two modes. This allows the same integration times to be used in each mode. X incrementing Y incrementing

MT9F002 DS Rev. H Pub. 6/15 EN 49 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Sensor Readout Configuration When subsampling is enabled, it may be necessary to adjust the x_addr_end, x_ad- dr_start and y_addr_end settings: the values for these registers are required to corre- spond with rows/columns that form part of the subsampling sequence. The adjustment should be made in accordance with the following rules: x_skip_factor = (x_odd_inc + 1) / 2 y_skip_factor = (y_odd_inc + 1) / 2  x_addr_start should be a multiple of x_skip_factor*8  (x_addr_end - x_addr_start + x_odd_inc) should be a multiple of x_skip_factor*8 The number of columns/rows read out with subsampling can be found from the equa- tion below:  columns/rows = (addr_end - addr_start + odd_inc) / skip_factor Summing Mode Summing can be enabled with binning. Unlike binning mode where the values of adja- cent same color pixels are averaged together, summing adds the pixel values together, resulting in better sensor sensitivity. Summing normally provides two times the sensi- tivity compared to the binning only mode. The 2x2 summing mode can be enabled by programming the following register bit fields: R0x3178[5:4] = 3 R0x3178[7:6] = 1 To disable summing, program register bit fields above to 0. Figure 39: Pixel Binning and Summing 2x2 Binning or Summing Σ v Σv avg Summi ng avg avg avgavg Binni ng avg

MT9F002 DS Rev. H Pub. 6/15 EN 51 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Sensor Readout Configuration Frame Rate Control The formulas for calculating the frame rate of the sensor are shown below. The line length is programmed directly in pixel clock periods through register line_length_pck. For a specific window size, the minimum line length can be found from the following equation: (EQ 9) Note that line_length_pck also needs to meet the minimum line length requirement set in register min_line_length_pck. The row time can either be limited by the time it takes to sample and reset the pixel array for each row, or by the time it takes to sample and read out a row. Values for min_line_blanking_pck are provided in Table 14 on page 52. The frame length is programmed directly in number of lines in the register frame_line_length. For a specific window size, the minimum frame length is shown in Equation 10: (EQ 10) The frame rate can be calculated from these variables and the pixel clock speed as shown in Equation 11: (EQ 11) If coarse_integration_time is set larger than frame_length_lines the frame size will be expanded to coarse_integration_time + 1. minimum_line_length x_addr_end x_addr_start– 1+ minimum frame_length_lines y_addr_end - y_addr_start 1+ = frame rate vt pixel clock mhz 1 106

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Sensor Readout Configuration MT9F002 DS Rev. H Pub. 6/15 EN 52 ©Semiconductor Components Industries, LLC,2015. Minimum Row Time The minimum row time and blanking values with default register settings are shown in Table 14. In addition, enough time must be given to the output FIFO so it can output all data at the set frequency within one row time. There are therefore three checks that must all be met when programming line_length_pck: 1. line_length_pck> min_line_length_pck 2. line_length_pck > 0.5*(x_addr_end - x_addr_start + x_odd_inc)/((1+x_odd_inc)/2) + min_line_blanking_pck 3. The row time must allow the FIFO to output all data during each row. That is,  For parallel interface: line_length_pck > (x_output_size) * “vt_pix_clk period” / “op_pix_clk period” + 0x005E F o r H i S P i ( 4 - l a n e ) : line_length_pck > (1/4)*(x_output_size) * “vt_pix_clk period” / “op_pix_clk period” + 0x005E Minimum Frame Time The minimum number of rows in the image is 2, so min_frame_length_lines will always equal (min_frame_blanking_lines + 2). Table 14: Minimum Row Time and Blanking Numbers Register No Row Binning Row Binning row_speed[2:0] 1 2 4 1 2 4 min_line_blanking_pck 0x0138 0x0138 0x0138 0x00E8 0x00E8 0x00E8 min_line_length_pck 0x04C8 0x0278 0x0278 0x0968 0x04B8 0x0260 Table 15: Minimum Frame Time and Blanking Numbers Register min_frame_blanking_lines 0x0092 min_frame_length_lines 0x0094

MT9F002 DS Rev. H Pub. 6/15 EN 53 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Sensor Readout Configuration Integration Time The integration (exposure) time of the MT9F002 is controlled by the fine_integration_- time and coarse_integration_time registers. The limits for the fine integration time are defined by: fine_integration_time_min < fine_integration_time < (line_length_pck – (EQ 12) fine_integration_time_max_margin The limits for the coarse integration time are defined by: coarse_integration_time_min < coarse_integration_time (EQ 13) The actual integration time is given by: (EQ 14) It is required that: coarse_integration_time < = (frame_length_lines - coarse_integration_time_max_margin) (EQ 15) If this limit is exceeded, the frame time will automatically be extended to (coarse_inte- gration_time + coarse_integartion_time_max_margin) to accommodate the larger inte- gration time. Fine Integration Time Limits The limits for the fine_integration_time can be found from fine_integration_time_min and fine_integration_time_max_margin. It is necessary to change fine_correction (R0x3010) when binning is enabled or the pixel clock divider (row_speed[2:0]) is used. The corresponding fine_correction values are shown in Table 16. Fine Correction For the fine_integration_time limits, the fine_correction constant will change with the pixel clock speed and binning mode. Table 16: Fine_Integration_Time Limits Register No Row Binning Row Binning row_speed[2:0] 1 2 4 1 2 4 fine_integration_time_min 0x02B0 0x0158 0x0AC 0x05F2 0x02FA 0x017E fine_integration_time_max_margin 0x0212 0x0109 0x0086 0x0376 0x01BA 0x00DC Table 17: Fine_Correction Values Register No Row Binning Row Binning row_speed[2:0] 1 2 4 1 2 4 fine_correction 0x094 0x044 0x01C 0x0183 0x0BB 0x057 integration_time coarse_integration_time* line_length_pck fine_integration_time+

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Power Mode Contexts MT9F002 DS Rev. H Pub. 6/15 EN 54 ©Semiconductor Components Industries, LLC,2015. Power Mode Contexts The MT9F002 sensor supports power consumption optimization through the power mode contexts. Depending on the sensor operating mode, the appropriate power context can be programmed through register R0x30E8 as shown in Table 18 below. Programming register R0x30E8 will internally set the analog bias current reserved regis- ters to predetermined values which result in optimized bias currents in the analog domain. Register R0x30E8 is not “Frame Sync'd,” and should be programmed when FRAME_VALID is not active, in order to avoid a “Bad Frame.” Table 18: Power Mode Contexts Power Mode Context Register Address Recommended Value Description

1 R0x30E8 0x8001 Reserved

2 R0x30E8 0x8002 Reserved

3 R0x30E8 0x8003 Reserved

4 Rr0x30E8 0x8004 Reserved

5 R0x30E8 0x8005 Reserved

6 R0x30E8 0x8006 Reserved

7 R0x30E8 0x8007 Reserved

MT9F002 DS Rev. H Pub. 6/15 EN 55 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Power Mode Contexts ON Semiconductor Gain Model The ON Semiconductor gain model uses color-specific registers to control both analog and digital gain to the sensor. These registers are:  global_gain g r e e n R _ g a i n r e d _ g a i n  blue_gain g r e e n B _ g a i n The registers provide three analog gain stages. The analog_gain_2 analog gain stage has a granularity of 64 steps over 2x gain. A digital gain (GAIN<15:12>) from 1-15x can also be applied. analog gain = 2^GAIN<11:10> x 2^GAIN<9:7> x GAIN<6:0>/64 (EQ 16) digital_gain = GAIN<15:12> (EQ 17) Total gain = digital_gain x analog_gain (EQ 18) Analog Gain Stages The analog gain stages of the MT9F002 sensor are shown in Figure 1. The recommended gain settings enable gain increases very early in the signal chain (such as in the colamp), so the signal can be effectively boosted while amplifying as few noise sources as possible. Figure 42: Analog Gain Stages As a result of the different gain stages, analog gain levels can be achieved in different ways. The recommended gain settings are shown in Table 19 on page 56. colamp_gain ASC1 analog_gain_2 (ASC2_fine_gain) analog_gain_3 1x, 2x, 4x and 8x 1x 1x to 1.984375x 1x, 2x Gain = 2^gain[11:10] Gain= gain [6:0]/64 Gain = 2^gain[9:7] Pixel Offset Cancellation digital_gain Gain = gain[15:12]

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Power Mode Contexts MT9F002 DS Rev. H Pub. 6/15 EN 58 ©Semiconductor Components Industries, LLC,2015. Global Reset Global reset mode allows the integration time of the MT9F002 to be controlled by an external electromechanical shutter. Global reset mode is generally used in conjunction with ERS mode. The ERS mode is used to provide viewfinder information, the sensor is switched into global reset mode to capture a single frame, and the sensor is then returned to ERS mode to restore viewfinder operation. Overview of Global Reset Sequence The basic elements of the global reset sequence are: 1. By default, the sensor operates in ERS mo de and the SHUTTER output signal is LOW . The electromechanical shutter must be open to allow light to fall on the pixel array. Integration time is controlled by the coarse_integration_time and fine_integration_- time registers. 2. A global reset sequence is triggered. 3. All of the rows of the pixel array are placed in reset. 4. All of the rows of the pixel array are taken out of reset simultaneously. All rows start to integrate incident light. The electromechanical shutter may be open or closed at this time. 5. If the electromechanical shutter has been closed, it is opened. 6. After the desired integration time (controlled internally or externally to the MT9F002), the electromechanical shutter is closed. 7. A single output frame is generated by th e sensor with the usual LV , FV , PIXCLK, and D OUT timing. As soon as the output frame has completed (FV de-asserts), the electro- mechanical shutter may be opened again. 8. The sensor automatically resumes operation in ERS mode. This sequence is shown in Figure 46. The following sections expand to show how the timing of this sequence is controlled. Figure 46: Overview of Global Reset Sequence Entering and Leaving the Global Reset Sequence A global reset sequence can be triggered by a register write to global_seq_trigger[0] (global trigger, to transition this bit from a 0 to a 1) or by a rising edge on a suit- ably-configured GPI input (see “Trigger Control” on page 36). When a global reset sequence is triggered, the sensor waits for the end of the current row. When LV de-asserts for that row, FV is de-asserted 6 PIXCLK periods later, potentially truncating the frame that was in progress. The global reset sequence completes with a frame readout. At the end of this readout phase, the sensor automatically resumes operation in ERS mode. The first frame inte- grated with ERS will be generated after a delay of approximately: ((13 + coarse_integration_time) * line_length_pck). This sequence is shown in Figure 47. ERS ERSRow Reset Integration Readout

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Power Mode Contexts MT9F002 DS Rev. H Pub. 6/15 EN 62 ©Semiconductor Components Industries, LLC,2015. The integration time of the GRR sequence is defined as: (EQ 19) Where: (EQ 20) (EQ 21) The integration equation allows for 24-bit precision when calculating both the shutter and readout of the image. The global_rst_end has only 16-bit as the array reset function and requires a short amount of time. The integration time can also be scaled using global_scale. The variable can be set to These programming restrictions must be met for correct operation of bulb exposures:  global_read_start > global_shutter_start  global_shutter_start > global_rst_end  global_shutter_start must be smaller than the exposure time (that is, this counter must expire before the trigger is de-asserted) Figure 52: Global Reset Bulb Retriggering the Global Reset Sequence The trigger for the global reset sequence is edge-sensitive; the global reset sequence cannot be retriggered until the global trigger bit (in the global_seq_trigger register) has been returned to “0,” and the GPI (if any) associated with the trigger function has been de-asserted. The earliest time that the global reset sequence can be retriggered is the point at which the SHUTTER output de-asserts; this occurs approximately 2 * line_length_pck after the negation of FV for the global reset readout phase. The frame that is read out of the sensor during the global reset readout phase has exactly the same format as any other frame out of the serial pixel data interface, including the addition of two lines of embedded data. The values of the coarse_integration_time and fine_integration_time registers within the embedded data match the programmed values of those registers and do not reflect the integration time used during the global reset sequence. Integration Time global _scale [global _read _start global _shutter _start– global _rst _end ]– global _read _start 2 16 global _read _start 27 : 0 global _read _start 11 5 : 0+= global _shutter _start 2 16 global _shutter _start 27 : 0 global _shutter _start 11 5 : 0+= ERS ERSRow Reset Integration Readout Trigger Wait for end of current row Automatic at end of frame readout global_rst_end GPI2 global_read_start - global_shutter_start

MT9F002 DS Rev. H Pub. 6/15 EN 63 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Power Mode Contexts Global Reset and Soft Standby If the mode_select[stream] bit is cleared while a global reset sequence is in progress, the MT9F002 will remain in streaming state until the global reset sequence (including frame readout) has completed, as shown in Figure 53. Figure 53: Entering Soft Standb y During a Global Reset Sequence Slave Mode The MT9F002 sensor supports Slave mode to sync the frame rate more precisely, and simply by the VD signal from external ASIC. The VD signal also allows for precise control of frame rate and register change updates. The VD signal for slave GRR mode is synchronized to ERS frame time, so that sensor can complete the current frame readout in ERS mode before moving to GRR mode, and avoid ERS broken frame before moving into GRR mode. Control bit vd_trigger_new_- frame bit allows VD triggering every new frame. A GPI pin on the sensor can be programmed to act as VD input pin signal whose rising edge can be used to start every new frame (see Figure 55 for details). An optional functionality to limit the duration counters are halted is given by setting vd_timer bit to 1. When this bit is set the counters will not wait indefinitely for VD rising edge & resume normal counting after halting for a limited time. Otherwise when vd_timer is set to 0, internal row and column counters are halted until the arrival of VD's positive edge. Slave Mode GRR Global reset sequence is triggered by programming the global_seq_trigger bit. After this register bit is written the sensor will wait for rising edge of VD signal at the end of the current frame to go into GRR mode. The control bit needed to be set to enable this func- tionality is vd_trigger_grst. Once in the GRR integration phase, the sensor will wait for the next VD rising edge to begin the readout. At the end of the readout phase, the sensor automatically resumes operation in ERS mode with readout of successive frames starting with rising edge of VD. Figure 54: “Slave Mode GRR Timing,” on page 64 and Figure 55: “Slave Mode HiSPi Output (ERS to GRR Transition),” on page 64 are related timing diagrams: ERS ERS Row Reset Integration Readout mode_select[streaming] system state Software StandbyStreaming

MT9F002 DS Rev. H Pub. 6/15 EN 65 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Sensor Core Digital Data Path Sensor Core Digital Data Path Test Patterns The MT9F002 supports a number of test patterns to facilitate system debug. Test patterns are enabled using test_pattern_mode (R0x0600–1). The test patterns are listed in Table 20. Test patterns 0–3 replace pixel data in the output image (the embedded data rows are still present). Test pattern 4 replaces all data in the output image (the embedded data rows are omitted and test pattern data replaces the pixel data). HiSPi Test Patterns Test patterns specific to the HiSPi are also generated. The test patterns are enabled by using test_enable (R0x31C6 - 7) and controlled by test_mode (R0x31C6[6:4]). For all of the test patterns, the MT9F002 registers must be set appropriately to control the frame rate and output timing. This includes: A l l c l o c k d i v i s o r s  x_addr_start  x_addr_end  y_addr_start  y_addr_end  frame_length_lines l i n e _ l e n g t h _ p c k x _ o u t p u t _ s i z e  y_output_size Table 20: Test Patterns test_pattern_mode Description

0 Normal operation: no test pattern

1 Solid color

2 100% color bars 3F a d e - t o - g r a y c o l o r b a r s

4 PN9 link integrity pattern (only on sensors with serial

interface)

256 Walking 1s (12-bit value)

257 Walking 1s (10-bit value)

258 Walking 1s (8-bit value)Table 21: HiSPi Test Patterns

test_mode Description 0 Transmit a constant 0 on all enabled data lanes. 1 Transmit a constant 1 on all enabled data lanes. 2 Transmit a square wave at half the serial data rate on all enabled data lanes. 3 Transmit a square wave at the pixel rate on all enabled data lanes.

4 Transmit a continuous sequence of pseudo random da ta, with no SAV code, copied on all enabled data

lanes. 5 Replace data from the sensor with a known sequence copied on all enabled data lanes.

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Sensor Core Digital Data Path MT9F002 DS Rev. H Pub. 6/15 EN 66 ©Semiconductor Components Industries, LLC,2015. Effect of Data Path Processing on Test Patterns Test patterns are introduced early in the pixel data path. As a result, they can be affected by pixel processing that occurs within the data path. This includes:  Noise cancellation  Black pedestal adjustment  Lens and color shading correction These effects can be eliminated by the following register settings:  R0x30CA-B[0] = 1  R0x31E0-1[0] = 0  R0x301A-B[3] = 0 (enable writes to data pedestal)  R0x301E-F = 0x0000 (set data pedestal to 0)  R0x3780[15] = 0 (turn off lens/color shading correction) Solid Color Test Pattern In this mode, all pixel data is replaced by fixed Bayer pattern test data. The intensity of each pixel is set by its associated test data register (test_data_red, test_data_greenR, test_data_blue, test_data_greenB). 100% Color Bars Test Pattern In this test pattern, shown in Figure 41 on page 127, all pixel data is replaced by a Bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, black). Each bar is 1/8 of the width of the pixel array. The pattern repeats after eight bars. Each color component of each bar is set to either 0 (fully off) or 0x3FF (fully on for 10-bit data). The pattern occupies the full height of the output image. The image size is set by x_addr_start, x_addr_end, y_addr_start, y_addr_end and may be affected by the setting of x_output_size, y_output_size. The color-bar pattern is discon- nected from the addressing of the pixel array, and will therefore always start on the first visible pixel, regardless of the value of x_addr_start. The number of colors that are visible in the output is dependent upon x_addr_end - x_addr_start and the setting of x_out- put_size: the width of each color bar is fixed. The effect of setting horizontal_mirror in conjunction with this test pattern is that the order in which the colors are generated is reversed: the black bar appears at the left side of the output image. Any pattern repeat occurs at the right side of the output image regardless of the setting of horizontal_mirror. The state of vertical_flip has no effect on this test pattern. The effect of subsampling, binning, and scaling of this test pattern is undefined.

MT9F002 DS Rev. H Pub. 6/15 EN 67 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Sensor Core Digital Data Path Figure 56: 100% Color Bars Test Pattern Fade-to-gray Color Bars Test Pattern In this test pattern, shown in Figure 42 on page 128, all pixel data is replaced by a Bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, black). Each bar is 1/8 of the width of the pixel array (2592/8 = 324 pixels). The test pattern repeats after 2592 pixels. Each color bar fades vertically from zero or full inten- sity at the top of the image to 50 percent intensity (mid-gray) on the last (968th) row of the pattern. Each color bar is divided into a left and a right half, in which the left half fades smoothly and the right half fades in quantized steps. The speed at which each color fades is dependent on the sensor's data width and the height of the pixel array. We want half of the data range (from 100 or 0 to 50 percent) difference between the top and bottom of the pattern. Because of the Bayer pattern, each state must be held for two rows. The rate-of-fade of the Bayer pattern is set so that there is at least one full pattern within a full-sized image for the sensor. Factors that affect this are the resolution of the ADC (10-bit or 12-bit) and the image height. For example, the MT9P013 fades the pixels by 2 LSB for each two rows. With 12-bit data, the pattern is 2048 pixels high and repeats after that, if the window is higher. The image size is set by x_addr_start, x_addr_end, y_addr_start, y_addr_end and may be affected by the setting of x_output_size, y_output_size. The color-bar pattern starts at the first column in the image, regardless of the value of x_addr_start. The number of colors that are visible in the output is dependent upon x_addr_end - x_addr_start and the setting of x_output_size: the width of each color bar is fixed at 324 pixels. The effect of setting horizontal_mirror or vertical_flip in conjunction with this test pattern is that the order in which the colors are generated is reversed: the black bar appears at the left side of the output image. Any pattern repeat occurs at the right side of the output image regardless of the setting of horizontal_mirror. The effect of subsampling, binning, and scaling of this test pattern is undefined. Horizontal mirror = 0 Horizontal mirror = 1

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Sensor Core Digital Data Path MT9F002 DS Rev. H Pub. 6/15 EN 68 ©Semiconductor Components Industries, LLC,2015. Figure 57: Fade-to-Gray Color Bar Test Pattern PN9 Link Integrity Pattern The PN9 link integrity pattern is intended to allow testing of a serial pixel data interface. Unlike the other test patterns, the position of this test pattern at the end of the data path means that it is not affected by other data path corrections (row noise, pixel defect correction and so on). This test pattern provides a 512-bit pseudo-random test sequence to test the integrity of the serial pixel data output stream. The polynomial x9 + x5 + 1 is used. The polynomial is initialized to 0x1FF at the start of each frame. When this test pattern is enabled:  The embedded data rows are disabled an d the value of frame_format_decriptor_1 changes from 0x1002 to 0x1000 to indicate that no rows of embedded data are present.  The whole output frame, bounded by th e limits programmed in x_output_size and y_output_size, is filled with data from the PN9 sequence.  The output data format is (effectively) fo rced into RAW10 mode regardless of the state of the ccp_data_format register. Before enabling this test pattern the clock divisors must be configured for RAW10 opera- tion (op_pix_clk_div = 10). This polynomial generates this sequence of 10-bit values: 0x1FF , 0x378, 0x1A1, 0x336, 0x385... On the parallel pixel data output, these values are presented 10-bits per PIXCLK. On the serial pixel data output, these values are streamed out sequentially without performing the RAW10 packing to bytes that normally occurs on this interface. Horizontal mirror = 0, Vertical flip = 0 Horizontal mirror = 1, Vertical flip = 0 Horizontal mirror = 0, Vertical flip = 1 Horizontal mirror = 1, Vertical flip = 1

MT9F002 DS Rev. H Pub. 6/15 EN 71 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Timing Specifications Timing Specifications Power-Up Sequence The recommended power-up sequence for the MT9F002 is shown in Figure 62. The available power supplies—V DD_IO, VDD, VDD_PLL, VAA, VAA_PIX, VDD_HISPI, VDD_TX can be turned on at the same time or have the separation specified below. 1. Turn on V DD_IO power supply. 2. After 1–500ms, turn on V DD and VDD_ HiSPi power supplies. 3. After 1–500ms, turn on V DD_PLL and VAA/VAA_PIX power supplies. 4. After 1–500ms, turn on V DD_TX power supply 5. After the last power supply is stable, enable EXTCLK. 6. Assert RESET_BAR for at least 1ms. 7. Wait 2700 EXTCLKs for internal initialization into software standby. 8. Configure PLL, output, and image settings to desired values 9. Set mode_select = 1 (R0x0100). 10. Wait 1ms for the PLL to lock before streaming state is reached. Figure 62: Power-Up Sequence Note: Digital supplies must be turned on before analog supplies. Table 22: Power-Up Sequence Definition Symbol Min Typ Max Unit VDD_IO to VDD, VDD_HiSPi time t10 – 5 0 0 m s VDD, VDD_HiSPi to VDD_PLL time t20 – 5 0 0 m s VDD_PLL to VAA/VAA_PIX time t30 – 5 0 0 m s VAA, VAA_PIX to VDD_TX t4– – 5 0 0 m s Active hard reset t5 1–– m s Internal initialization t6 2700 – – EXTCLKs PLL lock time t7 1–– m s Internal INIT Hard Reset Software Standby PLL Lock Streaming t6 t7 VDD_TX VAA, VAA_PIX EXTCLK VDD_PLL VDD, VDD_HiSPi VDD_IO RESET_BAR

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Timing Specifications MT9F002 DS Rev. H Pub. 6/15 EN 72 ©Semiconductor Components Industries, LLC,2015. Power-Down Sequence The recommended power-down sequence for the MT9F002 is shown in Figure 63. The available power supplies—V DD_IO, VDD, VDD_PLL, VAA, VAA_PIX, VDD_HiSPi, and VDD_TX—can be turned off at the same time or have the separation specified below. 1. Disable streaming if output is active by setting mode_select = 0 (R0x0100). 2. The soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. Assert hard reset by setti ng RESET_BAR to a logic “0.” 4. Turn off the V DD_TX, VAA/VAA_PIX, and VDD_PLL power supplies. 5. After 1 –500ms, turn off VDD and VDD_HiSPi power supply. 6. After 1 –500ms, turn off VDD_IO power supply. Figure 63: Power-Down Sequence Table 23: Power-Down Sequence Definition Symbol Min Typ Max Unit Hard reset t1 1–– m s VDD_TX to VDD time t20 – 5 0 0 m s VDD/VAA/VAA_PIX to VDD time t30 – 5 0 0 m s VDD_PLL to VDD time t40 – 5 0 0 m s VDD to VDD_IO time t50 – 5 0 0 m s VDD_IO VDD, VDD_HISPI VDD_PLL VAA, VAA_PIX VDD_TX EXTCLK RESET_BAR Turning Off Power Supplies Hard Reset Software StandbyStreaming

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Timing Specifications MT9F002 DS Rev. H Pub. 6/15 EN 74 ©Semiconductor Components Industries, LLC,2015. Soft Standby and Soft Reset The MT9F002 can reduce power consumption by switching to the soft standby state when the output is not needed. Register values are retained in the soft standby state. Once this state is reached, soft reset can be enabled optionally to return all register values back to the default. The details of the sequence are described below and shown in Figure 65. Soft Standby 1. Disable streaming if output is active by setting mode_select = 0 (R0x0100). 2. The soft standby state is reached after the current row or frame, depending on config- uration, has ended. Soft Reset 1. Follow the soft standby sequence listed above. 2. Set software_reset = 1 (R0x0103) to start the internal initialization sequence. 3. After 2700 EXTCLKs, the internal initializa tion sequence is completed and the current state returns to soft standby automatically. All registers, including software_reset, return to their default values. Figure 65: Soft Standby and Soft Reset EXTCLK mode_select R0x0100 software_reset R0x0103 Logic “1” Logic “0” Streaming Soft Standby Soft Reset Soft Standby next row/frame

2700 EXTCLKs

Logic “0” Logic “0” Logic “0”

MT9F002 DS Rev. H Pub. 6/15 EN 75 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Spectral Characteristics Spectral Characteristics Figure 66: Quantum Efficiency 350 400 450 500 550 600 650 700 750 Quantum Efficiency (%) Wavelength (nm) R G B

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Spectral Characteristics MT9F002 DS Rev. H Pub. 6/15 EN 76 ©Semiconductor Components Industries, LLC,2015. Table 24: 11.4 ° Chief Ray Angle Image Height CRA (%) (mm) (deg) 00 0 5 0.192 0.57 10 0.384 1.14 15 0.575 1.71 20 0.767 2.28 25 0.959 2.85 30 1.151 3.42 35 1.343 3.99 40 1.534 4.56 45 1.726 5.13 50 1.918 5.70 55 2.110 6.27 60 2.302 6.84 65 2.493 7.41 70 2.685 7.98 75 2.877 8.55 80 3.069 9.14 85 3.261 9.69 90 3.452 10.26 95 3.644 10.83 100 3.836 11.40 0 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 CRA (deg) Image Height (%)

MT9F002 DS Rev. H Pub. 6/15 EN 77 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Spectral Characteristics Reading the Sensor CRA Follow the steps below to obtain the CRA value of the image sensor: 1. Set the register bit field R0x301A[5] = 1. 2. Read the register bit fields R0x31FA[11:9]. 3. Determine the CRA value according to Table 26. Table 25: 25 ° Chief Ray Angle Image Height CRA (%) (mm) (deg) 00 0 5 0.192 2.16 10 0.384 4.27 15 0.575 6.35 20 0.767 8.41 25 0.959 10.45 30 1.151 12.44 35 1.343 14.37 40 1.534 16.21 45 1.726 17.93 50 1.918 19.49 55 2.110 20.89 60 2.302 22.10 65 2.493 23.10 70 2.685 23.88 75 2.877 24.46 80 3.069 24.83 85 3.261 25.00 90 3.452 25.00 95 3.644 24.84 100 3.836 24.56 Table 26: CRA Value Binary Value of R0x31FA[11:9] CRA Value 000 0 001 25 010 11.4 0 1 02 03 04 05 06 07 08 09 0 1 0 0 CRA (deg) Image Height (%)

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor

Electrical Characteristics

MT9F002 DS Rev. H Pub. 6/15 EN 78 ©Semiconductor Components Industries, LLC,2015. Caution Stresses greater than those listed in Table 28 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. Notes: 1. Exposure to absolute maximum rating cond itions for extended periods may affect reliability. Table 27: DC Electrical Defi nitions and Characteristics 0.4V; Output load = 68.5pF; TJ = 60°C; Data Rate = 660 Mbps; DLL set to 0, 14Mp frame-rate at 13.65 fps Definition Condition Symbol Min Typ Max Unit Core digital voltage VDD 1.7 1.8 1.9 V I/O digital voltage V DD_IO 1.7 1.8 1.9 V Analog voltage V AA 2.7 2.8 3.1 V Pixel supply voltage V AA_PIX 2.7 2.8 3.1 V PLL supply voltage V DD_PLL 2.4 2.8 3.1 V HiSPi digital voltage V DD_HiSPi 1.7 1.8 1.9 V HiSPi I/O digital voltage SLVS HiVCM VDD_TX 0.3 1.7 0.4 1.8 0.9 1.9 V V Digital operating current Serial HiSPi SLVS @ 13.65fps 75.0 mA I/O digital operating current Serial HiSPi SLVS @ 13.65fps 1.2 mA Analog operating current Serial HiSPi SLVS @ 13.65fps 172 mA Pixel supply current Serial HiSPi SLVS @ 13.65fps 5.6 mA PLL supply current Serial HiSPi SLVS @ 13.65fps 12.3 mA HiSPi digital operating current S erial HiSPi SLVS @ 13.65fps 28.6 mA HiSPi I/O digital operating current Serial HiSPi SLVS @ 13.65fps 10.5 mA Digital operating current Parallel interface @ 6.3fps 65.0 mA I/O digital operating current Parallel interface @ 6.3fps 41.5 mA Analog operating current Parallel interface @ 6.3fps 101.0 mA Pixel supply current Parallel interface @ 6.3fps 2.5 mA PLL supply current Parallel interface @ 6.3fps 13.7 mA Soft standby (clock on) mW Table 28: Absolute Maximum Ratings Symbol Definition Condition Min Max Unit VDD_MAX Core digital voltage –0.3 1.9 V VDD_IO_MAX I/O digital voltage –0.3 3.1 V VAA_MAX Analog voltage –0.3 3.5 V VAA_PIX Pixel supply voltage –0.3 3.5 V VDD_PLL PLL supply voltage –0.3 3.5 V VDD_HiSPi_MAX HiSPi digital voltage –0.3 1.9 V VDD_TX_MAX HiSPi I/O digital voltage –0.3 1.9 V tST Storage temperature –40 125 °C

MT9F002 DS Rev. H Pub. 6/15 EN 79 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Figure 67: Two-Wire Serial Bus Timing Parameters Note: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 29: Two-Wire Serial Register Interface Electrical Characteristics VDD_TX = 0.4V; Output load = 68.5pF; TJ = 60°C; Data Rate =660 Mbps; DLL set to 0 Symbol Parameter Condition Min Typ Max Unit VIL Input LOW voltage –0.5 0.73 0.3 x V DD_IO V IIN Input leakage current No pull up resistor; VIN = VDD_IO or DGND –2 2 A VOL Output LOW voltage At specified 2mA 0.031 0.032 0.035 V IOL Output LOW current At specified V OL 0.1V 3 mA CIN Input pad capacitance 6 pF CLOAD Load capacitance pF SDATA SCLK Write Start ACK Stop SDATA SCLK Read Start ACK tr_clk tf_clk 90% 10% tr_sdat tf_sdat 90% 10% tSDH tSDS tSHAW tAHSW tSTPS tSTPH Register Address Bit 7 Write Address Bit 0 Register Value Bit 0 Register Value Bit 7 Read Address Bit 0 Register Value Bit 0 Write Address Bit 7 Read Address Bit 7 tSHAR tSDSRtSDHRtAHSR tSRTH tSCLK

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor MT9F002 DS Rev. H Pub. 6/15 EN 80 ©Semiconductor Components Industries, LLC,2015. Table 30: Two-Wire Serial Register Interface Timing Specification VDD_TX = 0.4V; Output load = 68.5pF; TJ = 60°C; Data Rate = 660 Mbps,; DLL set to 0 Figure 68: I/O Timing Diagram Symbol Parameter Condition Min Typ Max Unit fSCLK Serial interface input clock – 0 100 400 kHz SCLK duty cycle V OD 45 50 60 % tRS C L K / S DATA rise time 300 s tSRTS Start setup time Master WRITE to slave 0.6 s tSRTH Start hold time Master WRITE to slave 0.4 s tSDH S DATA hold Master WRITE to slave 0.3 0.65 s tSDS S DATA setup Master WRITE to slave 0.3 s tSHAW S DATA hold to ACK Master READ to slave 0.15 0.65 s tAHSW ACK hold to S DATA Master WRITE to slave 0.15 0.70 s tSTPS Stop setup time Master WRITE to slave 0.3 s tSTPH Stop hold time Master WRITE to slave 0.6 s tSHAR S DATA hold to ACK Master WRITE to slave 0.3 1.65 s tAHSR ACK hold to S DATA Master WRITE to slave 0.3 0.65 s tSDHR S DATA hold Master READ from slave .012 0.70 s tSDSR S DATA setup Master READ from slave 0.3 s Data[11:0] FRAME_VALID/ LINE_VALID FRAME_VALID leads LINE_VALID by 6 PIXCLKs. FRAME_VALID trails LINE_VALID by 6 PIXCLKs. PIXCLK EXTCLK tCP tR tEXTCLK tF tRP tFP tPDtPD tPFH tPLH tPFL tPLL Pxl _0 Pxl _1 Pxl _2 Pxl _n 90% 10% 90% 10%

MT9F002 DS Rev. H Pub. 6/15 EN 81 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Notes: 1. Where 'n' is the number of PHYs 2. Temperature of 25°C Table 31: I/O Parameters load = 68.5pF; TJ = 60°C; Data Rate = 660 Mbps,; DLL set to 0 Symbol Definition Conditions Min Max Units VIH Input HIGH voltage VDD_IO = 1.8V 1.4 V DD_IO + 0.3 V VDD_IO = 2.8V 2.4 VIL Input LOW voltage VDD_IO = 1.8V GND – 0.3 0.4 VDD_IO = 2.8V GND – 0.3 0.8 IIN Input leakage current No pull-up resistor; VIN = VDD OR DGND – 20 20 A VOH Output HIGH voltage At specified I OH VDD_IO - 0.4V – V VOL Output LOW voltage At specified I OL –0 . 4 V IOH Output HIGH current At specified V OH –– 1 2 m A IOL Output LOW current At specified V OL –9 m A IOZ Tri-state output leakage current –1 0 A Table 32: I/O Timing 0.4V; Output load = 68.5pF; TJ = 60°C; Data Rate = 660 Mbps,; DLL set to 0 Symbol Definition Conditions Min Typ Max Units fEXTCLK Input clock frequency PLL enabled 2 24 64 MHz tEXTCLK Input clock period PLL enabled 200 41.7 15.6 ns tR Input clock rise time 0.1 – 1 V/ns tF Input clock fall time 0.1 – 1 V/ns Clock duty cycle 45 50 55 % tJITTER Input clock jitter – – 0.3 ns Output pin slew Fastest C LOAD = 15pF – 0.7 – V/ns fPIXCLK PIXCLK frequency Default – – 96 MHz tPD PIXCLK to data valid Default – – 3 ns tPFH PIXCLK to FRAME_VALID HIGH Default – – 3 ns tPLH PIXCLK to LINE_VALID HIGH Default – – 3 ns tPFL PIXCLK to FRAME_VALID LOW Default – – 3 ns tPLL PIXCLK to LINE_VALID LOW Default – – 3 ns Table 33: Power Supply and Operating Temperature Parameter Symbol Min Typ Max Unit Notes SLVS Current Consumption I DD_TX n*18 mA 1, 2 HiSPi PHY Current Consumption I DD_HiSPi n*45 mA 1, 2, 3 Operating temperature T J -30 70 °C 4

MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor MT9F002 DS Rev. H Pub. 6/15 EN 82 ©Semiconductor Components Industries, LLC,2015. 3. Up to 700 Mbps 4. Specification values may be exceeded when outside this temperature range. Table 34: SLVS Electrical DC Specification Tj = 25°C Parameter Symbol Min Typ Max Unit SLVS DC mean common mode voltage VCM 0.45*VDD_T X 0.5*VDD_TX 0.55*V DD_TX V SLVS DC mean differential output voltage |VOD| 0.36*V DD_T X 0.5*VDD_TX 0.64*V DD_TX V Change in VCM between logic 1 and 0  VCM 25 mV Change in |VOD| between logic 1 and 0 | V OD|2 5 m V VOD noise margin NM ±30 % Difference in VCM between any two channels | VCM|5 0 m V Difference in VOD between any two channels | VOD|1 0 0 m V Common-mode AC Voltage (pk) without VCM cap termination VCM_AC 50 mV Common-mode AC Voltage (pk) with VCM cap termination VCM_AC 30 mV Maximum overshoot peak |VOD|V OD_AC 1.3*|VOD|V Maximum overshoot Vdiff pk-pk Vdiff_pkpk 2.6*VOD V Single-ended Output impedance R O 35 50 70  Output Impedance Mismatch RO 20 %

MT9F002 DS Rev. H Pub. 6/15 EN 83 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Notes: 1. One UI is defined as the normalized mean ti me between one edge and the following edge of the clock. 2. Taken from the 0V crossing point with the DLL off. 3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3 UI. 4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges. 5. The absolute skew between any Clock in one PHY and any Data lane in any other PHY between any edges. Differential skew is defined as the skew between complementary outputs. It is measured as the abso- lute time between the two complementary edges at mean VCM point. Note that differential skew also is related to the VCM_AC spec which also must not be exceeded. HiVCM Electrical Specifications The HiSPi 2.0 specification also defines an alternative signaling level mode called HiVCM. Both VOD and VCM are still scalable with VDD_TX, but with VDD_TX nominal set to 1.8V the common-mode is elevated to around 0.9V . Notes: 1. Where 'n' is the number of PHYs 2. Temperature of 25°C 3. Up to 700 Mbps 4. Specification values may be exceeded when outside this temperature range. Table 35: SLVS Electrical Timing Specification Parameter Symbol Min Max Unit Notes Data Rate 1/UI 280 700 Mbps 1 Bitrate Period t PW 1.43 3.57 ns 1 Max setup time from transmitter t PRE 0.3 UI 1, 2 Max hold time from transmitter t POST 0.3 UI 1, 2 Eye Width t EYE 0.6 UI 1, 2 Data Total Jitter (pk-pk) @1e-9 t TOTALJIT 0.2 UI 1, 2 Clock Period Jitter (RMS) t CKJIT 50 ps 2 Clock Cycle-to-Cycle Jitter (RMS) t CYCJIT 100 ps 2 Rise time (20% - 80%) tR 150ps 0.25 UI 3 Fall time (20% - 80%) tF 150ps 0.25 UI 3 Clock duty cycle DCYC 45 55 % 2 Mean Clock to Data Skew t CHSKEW -0.1 0.1 UI 1, 4 PHY-to-PHY Skew t PHYSKEW 2.1 UI 1, 5 Mean differential skew t DIFFSKEW -100 100 ps 6 Table 36: HiVCM Power Supply and Operating Temperatures Parameter Symbol Min Typ Max Unit Notes HiVCM Current Consumption I DD_TX n*34 mA 1, 2 HiSPi PHY Current Consumption I DD_HiSPi n*45 mA 1, 2, 3 Operating temperature T J -30 70 °C 4

MT9F002 DS Rev. H Pub. 6/15 EN 84 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Table 37: HiVCM Electrical Voltage and Impedance Specification Tj = 25° C Parameter Symbol Min Typ Max Unit HiVCM DC mean common mode voltage V CM 0.76 0.90 1.07 V HiVCM DC mean differential output voltage |V OD| 200 280 350 mV Change in VCM between logic 1 and 0 VCM 25 mV Change in |VOD| between logic 1 and 0 | V OD|2 5 m V VOD noise margin NM ±30 % Difference in VCM between any two channels | VCM|5 0 m V Difference in VOD between any two channels | VOD|1 0 0 m V Common-mode AC Voltage (pk) without VCM cap termination VCM_AC 50 mV Common-mode AC Voltage (pk) with VCM cap termination VCM_AC 30 mV Maximum overshoot peak |VOD|V OD_AC 1.3*|VOD|V Maximum overshoot Vdiff pk-pk V diff_pkpk 2.6*VOD V Single-ended Output impedance R O 40 70 100  Output Impedance Mismatch RO 20 %

MT9F002 DS Rev. H Pub. 6/15 EN 85 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Notes: 1. One UI is defined as the normalized mean ti me between one edge and the following edge of the clock. 2. Taken from the 0 V crossing point with the DLL off. 3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3 UI. 4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges. 5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges. 6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two complementary edges at mean VCM point. Note that differential skew also is related to the VCM_AC spec which also must not be exceeded. Electrical Definitions Figure 69 is the diagram defining differential amplitude VOD, VCM, and rise and fall times. To measure VOD and VCM use the DC test circuit shown in Figure 70 on page 86 and set the HiSPi PHY to constant Logic 1 and Logic 0. Measure Voa, Vob and VCM with voltmeters for both Logic 1 and Logic 0. Table 38: HiVCM Electrical AC Specification Parameter Symbol Min Max Unit Notes Data Rate 1/UI 280 700 Mbps 1 Bitrate Period t PW 1.43 3.57 ns 1 Max setup time from transmitter t PRE 0.3 UI 1, 2 Max hold time from transmitter t POST 0.3 UI 1, 2 Eye Width t EYE 0.6 UI 1, 2 Data Total Jitter (pk-pk) @1e-9 t TOTALJIT 0.2 UI 1, 2 Clock Period Jitter (RMS) t CKJIT 50 ps 2 Clock Cycle-to-Cycle Jitter (RMS) t CYCJIT 100 ps 2 Rise time (20% - 80%) t R 150ps 0.3 UI 3 Fall time (20% - 80%) t F 150ps 0.3 UI 3 Clock duty cycle D CYC 45 55 % 2 Clock to Data Skew t CHSKEW -0.1 0.1 UI 1, 4 PHY-to-PHY Skew tP HYSKEW 2.1 UI 1, 5 Mean differential skew t DIFFSKEW -100 100 ps 6

MT9F002 DS Rev. H Pub. 6/15 EN 87 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor VCM = |VCM (1)-VCM (0) | (EQ 27) Both VOD and VCM are measured for all output channels. The worst case VOD is defined as the largest difference in VOD between all channels regardless of logic level. And the worst case VCM is similarly defined as the largest difference in VCM between all chan- nels regardless of logic level. Timing Definitions 1. Timing measurements are to be taken using the Square Wave test mode. 2. Rise and fall times are measured between 20% to 80% positions on the differential waveform, as shown in Figure 69: “Single-Ended and Differential Signals,” on page 86. 3. Mean Clock-to-Data skew should be measured from the 0V crossing point on Clock to the 0V crossing point on any Data channel regardless of edge, as shown in Figure 71 on page 87. This time is compared with the ideal Data transition point of 0.5UI with the difference being the Clock-to-Data Skew (see Equation 28 on page 87). Figure 71: Clock-to-Data Skew Timing Diagram (EQ 28) (EQ 29) 4. The differential skew is measured on the two single-ended signals for any channel. The time is taken from a transition on V oa signal to corresponding transition on Vob signal at VCM crossing point. tCHSKEW ps t tpw tCHSKEW UI t tpw

MT9F002 DS Rev. H Pub. 6/15 EN 90 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Cycle-to-cycle jitter (tCYCJIT) is defined as the difference in time between consecutive clock high and clock low periods tHCLK and tLCLK, quoting the RMS value of the variation (tHCLK - tLCLK). If pk-pk jitter is also measured, this should be limited to ±3-sigma.

MT9F002 DS Rev. H Pub. 6/15 EN 91 ©Semiconductor Components Industries, LLC,2015 MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor Package Dimensions Package Dimensions Figure 76: 48-Pin iLCC Package Outline Drawing

MT9F002 DS Rev. H Pub. 6/15 EN 92 ©Semiconductor Components Industries, LLC,2015. MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor

Revision History

 Updated “Ordering Information” on page 2  Updated “Ordering Information” on page 2  Converted to ON Semiconductor template  Removed Confidential marking  Updated Table 2, “ Available Part Numbers,” on page 2  Deleted Figure 8: “48-pin iLCC Parallel Package Pinout Diagram  Updated “High Speed Serial Pixel Data Interface” on page 15  Updated “Power-On Reset Sequence” on page 34  Updated Figure 27: “Clocking Configuration,” on page 37  Updated “Summing Mode” on page 49  Updated corporate address on last page  Updated trademarks  Updated to Production  Updated Table 2, “ Available Part Numbers,” on page 2  Updated power consumption in Table 1, “Key Performance Parameters,” on page 1  Updated Figure 5: “Typical Configuratio n: Serial Four-Lane HiSPi Interface,” on page 10  Updated Figure 6: “Typical Configuration: Parallel Pixel Data Interface,” on page 11  Updated Table 3, “Signal Descriptions,” on page 13  Updated Figure 7: “48-Pin iLCC HiSPi Package Pinout Diagram,” on page 14  Updated Figure 27: “Clocking Configuration,” on page 37  Updated “Power Mode Contexts” on page 54  Updated paragraph under note to Table 19, “Recommended Register Settings,” on page 56 and deleted old Table 22, “ISO Speed Equivalent Gain Settings: Rev. 3 Sensor”  Updated Figure 55: “Slave Mode HiSPi Ou tput (ERS to GRR Transition),” on page 64  Replaced Figure 68: “11.4 Chief Ray Angle” with Table 24, “11.4° Chief Ray Angle,” on page 76  Updated Table 27, “DC Electrical Defi nitions and Characteristics,” on page 78 C h a n g e d V DD_SLVS to VDD_HiSPi C h a n g e d VDD_SLVS_TX to VDD_TX  Updated to Preliminary  Updated “Features” on page 1  Updated Table 2, “ Available Part Numbers,” on page 2  Updated Table 1, “Key Performance Parameters,” on page 1  Updated “General Description” on page 1  Updated Table 25, “25° Chief Ray Angle,” on page 77

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