MT93L16

ZL38002_07 ZARLINK | Alldatasheet

Document overview

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Technical content

Features

• 112 ms acoustic echo canceller
• Up to 12 dB of noise reduction
• Works with low cost voice codec. ITU-T G.711 or signed mag µ/A-Law, or linear 2’s compliment
• Each port may operate independently in companded format or linear format
• Advanced NLP design - full duplex speech with no switched loss on audio paths
• Fast re-convergence time: tracks changing echo environment quickly
• Adaptation algorithm converges even during Double-Talk
• Designed for exceptional performance in high background noise environments
• Provides protection against narrow-band signal divergence
• Howling prevention stops uncontrolled oscillation in high loop gain conditions
• Programmable offset nulling of all PCM channels
• Serial micro-controller interface
• Idle channel noise suppression
• ST-BUS, GCI, or variable-rate SSI PCM interfaces
• User gain control provided for speaker path ( - 2 4d B t o + 2 1d B i n 3d B s t e p s )
• Adjustable gain pads from -24 dB to +21 dB at Xin, Sin and Sout to compensate for different system requirements
• AGC on speaker path
• Handles up to -6 dB acoustic echo return loss (with the appropriate gain pad settings)
• Transparent data transfer and mute options
• 20 MHz master clock operation
• Low power mode during PCM Bypass
• Bootloadable for future factory software upgrades
• 2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs January 2007

Ordering Information

ZL38002QDG 48 Pin TQFP Trays ZL38002QDG1 48 Pin TQFP* Trays ZL38002DGE1 36 Pin QSOP* Tubes, Bake & Drypack ZL38002DGF1 36 Pin QSOP* Tape & Reel, Bake & Drypack *Pb Free Matte Tin -40°C to 85 °C ZL38002 Digital Echo Canceller for Hands Free Communication Data Sheet Figure 1 - Functional Block Diagram Rout MD1 MD2 Sin Micro Interface Program RAM Program ROM Howling ControllerNBSD Linear/ µ/A-Law R1R1 S1 S2 FORMAT Linear/ µ/A-Law HP FilterLinear µ/A-Law/ Adaptive Filter HP Filter VDD VSS RESET F0i BCLK/C4i MCLK Sout Rin DATA1 DATA2 CS SCLK ENA2 LAW AGC User Gain -24 -> +21dB ADV NLP Linear µ/A-Law/ UNIT CONTROL Detector Talk Double NBSD ENA1 Limiter Limiter ACOUSTIC ECHO PATH Gain Pad Gain Pad Gain Pad Noise Reduction

Zarlink Semiconductor Inc.

Applications

• Hands free car kits
• Full duplex speaker-phone for digital telephone
• Echo cancellation for video conferencing
• Security systems
• Intercom systems (door entry, elevator, and restaurant drive-through) MT93L16 ZL38001 ZL38002 ZL38003 Description AEC for analog hands- free communication AEC for analog hands- free communication AEC with noise reduction for digital hands-free communication AEC with noise reduction & codecs for digital hands-free communication Application Analog Desktop phone Analog Intercom Analog Desktop phone Analog Intercom Hands-free Car Kits Digital Desktop Phone Home Security Intercom & Pedestals Hands-free Car Kits Digital Desktop Phone Home Security Intercom & Pedestals

AEC 1 channel 1 channel 1 channel 1 channel LEC 1 channel 1 channel Custom Load Custom Load Gains User Gain Us er Gain/18 dB Gain on Sout User Gain + System tuning gains User Gain + System tuning gains Noise Reduction NN Y Y Integrated Codecs N N N dual channel Table 1 - Acoustic Echo Cancellation Family

Zarlink Semiconductor Inc. Figure 2 - Pin Connections Pin Description QSOP Pin # TQFP Pin # Name Description 14 3 E N A 1 SSI Enable Strobe/ST-BUS & GCI Mode for Rin/Sout (Input). This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present for frame synchronization. This is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for on Rin/Sout pins. Strobe period is 125 ms. For ST- BUS or GCI, this pin, in conjunction with the MD1 pin, selects the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). 24 5 M D 1 ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI operation, this pin, in conjunction with the ENA1 pin, will select the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode. 34 6 E N A 2 SSI Enable Strobe /ST-BUS & GCI Mode for Sin/Rout (Input). This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer on Sin/Rout pins. Strobe period is 125 ms. For ST-BUS/GCI, this pin, in conjunction with the MD2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). 44 7 M D 2 ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI operation, this pin in conjunction with the ENA2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode. DATA2 VDD NC IC NC DATA1SCLK Sout Rout BCLK/C4i IC IC Sin Rin IC MD2 MD1 F0i FORMAT IC LAW ENA1 RESET NC ENA2 MCLK CS QSOP

31 VSS

29 VSS2

Zarlink Semiconductor Inc. 54 8 R i n Receive PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input stream. Data may be in either companded or 2’s complement linear format. This is the Receive Input channel from the line (or network) side. Data bits are clocked in following SSI, GCI or ST-BUS timing requirements. 62 S i n Send PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input stream. Data may be in either companded or 2’s complement linear format. This is the Send Input channel (from the microphone). Data bits are clocked in following SSI, GCI or ST-BUS timing requirements. 73 I C Internal Connection (Input). Must be tied to Vss. 85 M C L K Master Clock (Input). Nominal 20 MHz Master Clock input (can be asynchronous relative to 8 KHz frame signal.) Tie together with MCLK2. 9,10,11 6, 7, 8 IC Internal Connection (Input). Must be tied to Vss. 12 9 LAW A/µ Law Select (Input). When low, selects µ−Law companded PCM. When high, selects A-Law companded PCM. This control is for both serial pcm ports. 13 11 FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM code. This control is for both serial pcm ports. 14 13 RESET Reset / Power-down (Input). An active low resets the device and puts the ZL38002 into a low-power stand-by mode. 17 16 SCLK Serial Port Synchronous Clock (Input). Data clock for the serial microport interface. 18 17 CS Serial Port Chip Select (Input). Enables serial microport interface data transfers. Active low. 19 19 DATA2 Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd. 20 21 DATA1 Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1 pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for transmitting and receiving data. 22 23 VDD Positive Power Supply (Input). Nominally 3.3 volts. 23 24 Sout Send PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM output stream. Data may be in either companded or 2’s complement linear PCM format. This is the Send Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked out following SSI, ST- BUS or GCI timing requirements. 24 26 Rout Receive PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM output stream. Data may be in either companded or 2’s complement linear PCM format. This is the Receive out signal after the AGC and gain control. Data bits are clocked out following SSI, ST-BUS or GCI timing requirements. Pin Description (continued) QSOP Pin # TQFP Pin # Name Description

Zarlink Semiconductor Inc. 25 27 F0i Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low (or active-high) frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss. 26 29 BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit clock. This clock must be synchronous with ENA1 and ENA2 enable strobes. In ST-BUS or GCI operation, C4i pin must be connected to the 4.096 MHz (C4) system clock. 27, 28 30, 31 IC Internal Connection (Input). Tie to Vss. 29 33 VSS2 Digital Ground (Input). Nominally 0 volts. 30 34 VDD2 Positive Power Supply (Input). Nominally 3.3 volts (tie together with VDD). 31 35 VSS Digital Ground (Input). Nominally 0 volts (tie together with VSS2). 33 38 MCLK2 Master Clock (Input). Nominal 20 MHz master clock (tie together with MCLK). 34,35,36 39, 40, 41 IC Internal Connection (Input). Tie to Vss. 15, 16, 21, 1, 4, 10, 12, 14, 15, 18, 20, 22, 25, 28, 32, 36, 37, 42, 44 NC No Connect (Output). This pin should be left unconnected. Pin Description (continued) QSOP Pin # TQFP Pin # Name Description

Zarlink Semiconductor Inc.

Zarlink Semiconductor Inc.

Zarlink Semiconductor Inc.

1.0 Changes Summary

The following table captures the changes from the November 2005 issue.

2.0 Functional Description

The ZL38002 device is comprised of an acoustic echo cancel ler and the necessary control functions for operation. The ZL38002 guarantees clear signal transmission in both tr ansmit and receive audio path directions to ensure reliable voice communication, even when low level si gnals are provided. The ZL38002 does not use variable attenuators during double-talk or sing le-talk periods of speech, as do many other acoustic echo cancellers for speakerphones. Instead, the ZL38002 provides high perfo rmance full-duplex operation similar to network echo cancellers. This results in users experiencing clear speech and uninterrupted background signals during the conversation and prevents subjective sound quality problems associated with “noise gating” or “noise contrasting”. The ZL38002 uses an advanced adaptive filt er algorithm that is double-talk stable, which means that convergence takes place even while both parties are talking. This al gorithm allows continual tracking of changes in the echo path, regardless of double-talk, as long as a reference signal is available for the echo canceller. The echo tail cancellation capability of the acoustic echo canceller has been sized appropriately (112 ms) to cancel echo in an average sized office with a reverberation time of less than 112 ms. In addition to the echo cancellers, the following functions are supported:

• 12 dB of noise reduction
• User gain pads at the Sin and Sout ports pl us one at the input of adaptive filter (XRAM)
• Control of adaptive filter convergence speed during peri ods of double-talk, far end single-talk and near-end echo path changes
• Control of Non-Linear Processor thresholds for suppression of residual non-linear echo
• Howling detector to identify when instability is starti ng to occur and to take action to prevent oscillation
• Narrow-Band Detector for preventing adaptive fi lter divergence caused by narrow-band signals
• Programmable high pass filters at Rin and Sin for removal of DC components in PCM channels
• Limiters that introduce controlled saturation levels
• Serial controller interface compatible with Motorola, National and Intel microcontrollers
• PCM encoder/decoder compatible with m/A-Law ITU-T G.711, m/A-Law Sign-Mag or linear 2’s complement coding
• Automatic gain control on the receive speaker path
• Idle channel noise suppression

2.1 Noise Reduction

The ZL38002 incorporates a noise reduct ion circuit that reduces background noi se up to 12 dB. The level of noise reduction is programmed allowing the user to adjust the level of noise cancellation according to system requirements. This is controlled thr ough the NR register on page 3 address 16 H. A larger value in this register will increase the amount of noise reductio n. As the amount of noise reduction is increased the amount of distortion in the audio path also increases. The noise reduction can be bypassed by setting bit 4 in Control Register 1 (Address 01H) Page Item Change

1 Updated Ordering Information

Zarlink Semiconductor Inc.

2.2 Noise Suppression

The ZL38002 also utilizes noise suppression which can be used to reduce idle channel noise from emanating from the acoustic end. By setting a threshold value in the lower nibble (bits 0-3) of the MCR2 register on page 0 address 01H, idle channel noise below the threshold is zero-forced. The threshold limits ranges from 0 to 16 (based on a 16 bit 2's complement) with a value of 0 disabling suppression.

2.3 Adaptation Speed Control

The adaptation speed of the acoustic echo canceller is designed to optimize the convergence speed versus divergence caused by interfering near-end signals. Adap tation speed algorithm takes into account many different factors such as relative double-talk condition, far end signal power, echo path change and noise levels to achieve fast convergence.

2.4 Advanced Non-Li near Processor (ADV-NLP)

After echo cancellation, there is likely to be residual ec ho which needs to be removed so that it will not be audible. The ZL38002 uses an NLP to remove low level residual echo signals which are not comprised of background noise. The operation of the NLP depends upon a dynamic activation threshold, as well as a double-talk detector which disables the NLP during double-talk periods. The ZL38002 keeps the perceived noise level constant, wi thout the need for any variable attenuators or gain switching that causes audibl e “noise gating”. The noise level is consta nt and identical to the original background noise even when the NLP is activated. The NLP can be disabled by setting the NLP- bit to 1 in the AEC control registers.

2.5 Narrow Band Signal Detect or (NBSD) 1

Single or multi-frequency tones (e.g,. DTMF, or signalling tones) present in the reference input of an echo canceller for a prolonged period of time may cause the adaptive filter to diverge. The Narrow Band Signal Detector (NBSD) is designed to prevent this divergence by detecting single or multi-tones of arbitrary frequency, phase, and amplitude. When narrow band signals are detected, the filter adaptation process is stopped but the echo canceller continues to cancel echo. The NBSD can be disabled by setting the NB- bit to 1 in the MC control registers.

2.6 Howling Detector (HWLD)1

The Howling detector is part of an Anti-Howling control, designed to prevent oscillation as a result of positive feedback in the audio paths. The HWLD can be disabled by setting the AH- bit to 1 in the (MC) control register.

2.7 Programmable High Pass Filter

Programmable high pass filters are place at the Sin and Rin ports. These filters have two functions, one to remove any DC offset that may be present on eith er the Rin or the Sin port and two, to filter low frequency noise such as road noise (below 300 Hz). The offset null filters can be disabled by setting the HPF- bit to 1 in the AEC control registers. 1. Patented

Zarlink Semiconductor Inc.

2.8 Limiters

To prevent clipping in the echo paths, two limiters with variable thresholds are provided at the outputs.

2.9 User Gain

The user gain function provides the ability for users to adju st the audio gain on all path s. This gain is adjustable from -24 dB to +21 dB in 3 dB steps for the Sout and Rout paths. It is important to use ONLY this user gain function to adjust the speaker volume. The user gain function in the ZL38002 is optimally placed outside the echo path such that no reconvergence is necessary after gain changes, avoiding a burst of each overtime the speaker gain is changed.

2.10 AGC

The AGC function is provided to limit the volume in the speaker path. The gain of the speaker path is automatically reduced during the following conditions:

• When clipping of the receive signal occurs
• When initial convergence of the acoustic echo canceller detects unusually large echo return
• When howling is detected The AGC can be disabled by setting the AGC- bit to 1 in MC control register

2.11 Programmable Gain Pad

The ZL38002 has three gain pads located at Sin, Sout and at the adaptive filter (Xin). These gain pads are intended to be set once during initialization and not be used as dynamic gain adjustments. The purpose of theses gainpads are to help fine tune the performance of the acoustic echo canceller for a particular system. For example, the gain pad can be used to improve t he subjective quality in low ERL environments. The ZL38002 can cancel echo with a ERL as low as 0 dB (attenuation from Rout to Sin). In many hand free applications, the ERL can be low (or negative). This is due to both speaker a nd microphone gain setting. The speaker gain has to be set high enough for the speaker to be heard properly and t he microphone gain needs to be set high enough to ensure sufficient signal is sent to the far end. If the ERL (Acoustic Attenuation - speaker gain - microphone gain) is greater than 0 dB, then the echo canceller cannot cancel echo. To overcome this limitation, the gain pad at Sin and Sout can be used to lower the Sin level (and therefore the ERL) by 6 dB, perform the echo cancellation then amplify it at Sout by 6 dB. This will have the effect having 0dB gain between Sin and Sout for double talk signals while injecting a additional 6 dB attenuation for the echo return. It is important to reduce the DTDT threshold (Page 0 address 30) to match the Sin/Sout gain settings. The gain can be accessed through Customer Gain Control Registers 1 - 2 (Page 0, Address 1CH - 1DH).

2.12 Mute Function

A pcm mute function is provided for independent control of the Receive and Send audio paths. Setting the MUTE_R or MUTE_S bit in the MC register, causes quiet code to be transmitted on the Rout or Sout paths respectively. The ZL38002 has an optional DC offset control. The user can add a positive offset to the mute value. This is controlled through the DC offset register (Page 0, Address 03h) Quiet code is defined according to the following table.

Zarlink Semiconductor Inc.

2.13 Master Bypass

A PCM bypass function is provided to allow transparent transmission of pcm data through the ZL38002. When the bypass function is active, PCM data passes transparently from Rin to Rout and from Sin to Sout, with bit-wise integrity preserved. When the Bypass function is selected, most inter nal functions are powered down to provide low power consumption. The BYPASS control bit is located in the main control MC register.

2.14 AEC Bypass

An AEC bypass function is provided to allow the user to bypass only the AEC (i.e the echo estimate from the adaptive filter is not subtracted from the Send path). This bypass does not effect any other function in the ZL38002. The AEC BYPASS control bit is located in the Acoustic Echo Canceller Control Register (AECCR).

2.15 Adaptation Control

Adaptation control bit is located in the Acoustic Echo C anceller Control Register (Page 0, Address 21h). When the ADAPT- bit is set to 1, the adaptive filt er is frozen at the current state. In this state, the device continues to cancel echo with the current echo model. When the ADAPT- bit is set to 0, the adaptive filter is continually updated allowing the echo cancellor to adapt and track changes in the echo path. This is the normal operating state ZL38002

2.16 Throughput Delay

In all modes, except ST-BUS/GCI operation, voice channe ls have 2 frames of constant delay. In ST-BUS/GCI operation, the D and C channels have a delay of one frame.

2.17 Power Down / Reset

Holding the RESET pin at logic low will keep the ZL38002 device in a power-down state. In this state all internal clocks are halted, and the DATA1, Sout and Rout pins are tristated. The user should hold the RESET pin low for at least 200 msec following po wer-up. This will insure that the device powers up in a proper state. Following any return of RESET to logic high, the user must wait for 8 complete 8 KHz frames prior to writing to the device registers. During this time, the initialization routines will execute and set the ZL38002 to default operation based on the installed algorithm. LINEAR 16 bits 2’s complement SIGN/ MAGNITUDE µ-Law A-Law CCITT (G.711) µ-Law A-Law +Zero (quiet code) 0000h 80h FFh D5h Table 2 - Quiet PCM Code Assignment

Zarlink Semiconductor Inc.

3.0 PCM Data I/O

The PCM data transfer for the ZL38002 is provided through two PCM ports. One port consists of Rin and Sout pins while the second port consists of Si n and Rout pins. The data are transfe rred through these ports according to either ST-BUS, GCI or SSI conventi ons detected automatically by the device. The ZL38002 determines the convention by monitoring the signal applied to the F0i pin. When a valid ST-BUS (active low) frame pulse is applied to the F0i pin, the ZL38002 will assume ST-BUS operation. When a valid GCI (active high) frame pulse is applied to the F0i pin, the device will as sume GCI operation. If F0i is tied continuously to Vss, the device is set to SSI operation. Figures 3 to 6 show timing diagrams of these 3 PCM-interface operation conventions.

3.1 ST-BUS and GCI Operation

The ST-BUS PCM interface conforms to Zarlink’s ST-BUS standard with an active-low frame pulse. Input data is clocked in by the rising edge of the bit clock (C4i ) three-quarters of the way into the bit cell and output data bit boundaries (Rout, Sout) occur every second falling edge of the bit clock (see Figure 11.) The GCI PCM interface corresponds to the GCI standard commonly used in Europe with an active-high frame pulse. Input data is clocked in by the falling edge of the bit clock (C4i ) three-quarters of the way into the bit cell and output data bit boundaries (Rout, Sout) occur every second rising edge of the bit clock (see Figure 12.) Either of these interfaces (ST-BU S or GCI) can be used to transport 8 bit companded PCM data (using one timeslot) or 16 bit 2’s complement linear PCM data (using two timeslots). The MD1/ENA1 pins select the timeslot on the Rin/Sout port while the MD2/ENA2 pi n selects the timeslot on the Sin/Rout port, as in Table 2. Figures 3 to 6 illustrate the timeslot allocation for each of these four modes. Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1) C4i F0i (ST-BUS) Sin Rout Rin Sout 76543 210 76543 210 76543 210 76543 210 outputs = High impedance inputs = don’t care In ST-BUS/GCI Mode 1, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 0. Note that the user can configure PORT1 and PORT2 into different modes. PORT1 PORT2 01 2 3 4 B F0i (GCI) start of frame (stbus & GCI) EC EC

Zarlink Semiconductor Inc. Figure 4 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 2 (Mode 2) C4i F0i (ST-BUS) Sin Rout Rin Sout 76543 21 0 76543 21 0 76543 210 76543 21 0 In ST-BUS/GCI Mode 2, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 2. Note that the user can configure PORT1 and PORT2 into different modes. PORT1 PORT2 01 2 3 4 outputs = High impedance inputs = don’t care B F0i (GCI) start of frame (stbus & GCI) EC EC

Zarlink Semiconductor Inc. Figure 5 - ST-BUS and GCI 8-Bit Companded PCM I/O with D and C channels (Mode 3) C4i F0i (ST-BUS) Rin Sout EC Sin Rout EC PORT1 PORT2 indicates that an input channel is bypassed to an output channel ST-BUS/GCI Mode 3 supports connection to 2 B+D devices where timeslots 0 and 1 transport D and C channels and echo canceller (EC) I/O channels are assigned to ST-BUS timeslot 2 (B). Both PORT1 and PORT2 must be configured in Mode 3. 01 2 3 4 outputs = High impedance inputs = don’t care 76543 21 0 7654 321 0 7654 321 0 76543 210 76543 21 0 7654 321 0 7654 321 0 76543 210 76543 21 0 7654 321 0 7654 321 0 76543 210 D C B F0i (GCI) start of frame (stbus & GCI)

Zarlink Semiconductor Inc. Figure 6 - ST-BUS and GCI 16-Bit 2’s Complement Linear PCM I/O (Mode 4)

3.2 SSI Operation

The SSI PCM interface consists of data input pins (Rin, Sin), data output pins (Sout, Rout), a variable rate bit clock (BCLK), and two enable pins (ENA1, ENA2) to provide stro bes for data transfers. The active high enable may be either 8 or 16 BCLK cycles in durat ion. Automatic detection of the data type (8 bit companded or 16-bit 2’s complement linear) is accomplished internally. The data type cannot change dynamically from one frame to the next. PORT1 Rin/Sout ST-BUS/GCI Mode Selection PORT2 Sin/Rout Enable Pins Enable Pins MD1 ENA1 MD2 ENA2 0 0 Mode 1 . 8 bit companded PCM I/O on timeslot 0 0 0 0 1 Mode 2 . 8 bit companded PCM I/O on timeslot 2. 0 1 1 0 Mode 3 . 8 bit companded PCM I/O on timeslot 2. Includes D & C channel bypass in timeslots 0 & 1. 1 1 Mode 4 . 16-bit 2’s complement linear PCM I/O on timeslots 0 & 1. Table 3 - ST-BUS & GCI Mode Select C4i F0i (stbus) Rin Sout 76543210 Sin Rout PORT1 PORT2 S1 4 13 121 1 1 098 ST-BUS/GCI Mode 4 allows 16 bit 2’s complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and PORT2 need not necessarily both be in mode 4. outputs = High impedance inputs = don’t care 76543210S1 4 13 12 11 10 9 8 76543210S1 4 13 12 11 10 98 76543210S1 4 13 12 11 10 9 8 F0i (GCI) start of frame (stbus & GCI) EC EC

Zarlink Semiconductor Inc. In SSI operation, the frame boundary is determined by the rising edge of the ENA1 enable strobe (see Figure 7). The other enable strobe (ENA2) is used for parsing input/output data and it must pulse within 125 microseconds of the rising edge of ENA1. In SSI operation, the enable st robes may be a mixed combination of 8 or 16 BCLK cycles allowing the flexibility to Table 4 - SSI Enable Strobe Pins

3.3 PCM Law and Format Control (LAW, FORMAT)

The PCM companding/coding law used by the ZL38002 is controlled through the LAW and FORMAT pins. ITU-T G.711 companding curves for m-Law and A-Law are selected by the LAW pin. PCM coding ITU-T G.711 and Sign- Magnitude are selected by the FORMAT pin. See Table 4. Figure 7 - SSI Operations Enable Strobe Pin Designated PCM I/O Port ENA1 Line Side Echo Path (PORT 1) ENA2 Acoustic Side Echo Path (PORT 2) BCLK ENA1 Rin Sout 8 or 16 bits 8 or 16 bits PORT1 PORT2 8 or 16 bits 8 or 16 bits ENA2 Sin Rout Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate with 16-bit enable strobes. outputs = High impedance inputs = don’t care start of frame (SSI) EC EC

Zarlink Semiconductor Inc.

3.4 Linear PCM

The 16-bit 2’s complement PCM linear coding permits a dynamic range beyond that which is specified in ITU-T G.711 for companded PCM. The echo-cancellation algorithm will accept 16-bits 2’s complement linear code which gives a maximum signal level of +15 dBm0.

3.5 Bit Clock (BCLK/C4i )

The BCLK/C4i pin is used to clock the PCM data for GCI and ST-BUS (C4i ) interfaces, as well as for the SSI (BCLK) interface. In SSI operation, the bit rate is determined by the BCLK frequency. This i nput must contain either eight or sixteen clock cycles within the valid enable strobe window. BCLK may be any rate between 128 KHz to 4.096 MHz and can be discontinuous outside of the enable strobe windows defined by ENA1, ENA2 pins. Incoming PCM data (Rin, Sin) are sampled on the falling edge of BCLK while outgoing PCM data (Sout, Rout) are clocked out on the rising edge of BCLK. See Figure 13. In ST-BUS and GCI operation, connect the system C4 (4.096 MHz) clock to the C4i pin.

3.6 Master Clock (MCLK)

A nominal 20 MHz, continuously-running master clock (MCL K) is required. MCLK may be asynchronous with the 8K H z f r a m e .

4.0 Microport

The serial microport provides access to all ZL38002 intern al read and write registers, plus write-only access to the bootloadable program RAM (see next section for bootload de scription). This microport is compatible with Intel MCS-51 (mode 0), Motorola SPI (CPOL=0, CPHA=0) and National Semiconductor Micr owire specifications. The microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a synchronous data clock pin (SCLK). The ZL38002 automatically adjusts its internal timing and pi n configuration to conform to Intel or Motorola/National specifications. The microport dynamically senses the state of the SCLK pin each time the CS pin becomes active (i.e., high to low transition). If the SCLK pin is high during a CS activation, then the Intel mode 0 timing is assumed. In this case the DATA1 pin is defined as a bi-directiona l (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during a CS activation, then Motorola/National timing is assumed and DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. The ZL38002 supports Motorola half- PCM Code Sign-Magnitude FORMAT=0 ITU-T (G.711) FORMAT=1 µ/A-LAW LAW = 0 or 1 µ-LAW LAW = 0 A-LAW LAW =1 + Full Scale 1111 1111 1000 0000 1010 1010 + Zero 1000 0000 1111 1111 1101 0101 - Zero 0000 0000 0111 1111 0101 0101 - Full Scale 0111 1111 0000 0000 0010 1010 Table 5 - Companded PCM

Zarlink Semiconductor Inc. duplex processor mode (CPOL=0 and CPHA=0). This means that during a write to the ZL38002, via a Motorola processor, output data from the DATA1 pin is disregarded. This also means that input data on the DATA2 pin is ignored by the ZL38002 during a valid read by the Motorola processor. All data transfers through the microport are two bytes l ong. This requires the transmission of a Command/Address byte followed by the data byte to be writt en to or read from t he addressed register. CS must remain low for the duration of this two-byte transfer. As shown in Figures 8 and 9, the falling edge of CS indicates to the ZL38002 that a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcont roller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the ZL 38002 and the microcontroller. At the end of the two-byte transfer, CS is brought high again to terminat e the session. The rising edge of CS will tri-state the DATA1 pin. The DATA1 pin will remain tri-stated as long as CS is high. Intel processors utilize Least Significant Bit (LSB) first transmission while Motorola/National processors use Most Significant Bit (MSB) first transmi ssion. The ZL38002 microport automatica lly accommodates both schemes for normal data bytes. However, to ensure timely decoding of the R/W and address information, the Command/Address byte is defined differently for Intel and Motorola/National operations. Refer to the relative timing diagrams of Figure 6 and Figure 7. Receive data bits are sampled on the rising edge of SCLK while transmit data is clocked out on the falling edge of SCLK. Detailed microport timing is shown in Figure 13 and Figure 14.

5.0 Bootload Process and Execution from RAM

A bootloadable program RAM (BRAM) is available on the ZL38002 to support factory-issued software upgrades to the built-in algorithm. To make use of this bootload feat ure, users must include 4096 X 8 bits of memory in their microcontroller system (i.e., external to the ZL38002), from which the ZL38002 can be bootloaded. Registers and program data are loaded into the ZL38002 in the same fa shion via the serial micropor t. Both employ the same command / address / data byte specification described in the previous section on serial microport. Either intel or motorola mode may be transparently used for bootloading. There are also two register s relevant to bootloading (BRC=control and SIG=signature, see Register Summary). Th e effect of these register values on device operation is summarized in Table 5. Bootload mode is entered and exited by writing to the boo tload bit in the Bootload RAM Control (BRC) register at address 3fh (see Register Summary). During bootload mode, any serial microport “write” (R/W command bit =0) to an address other than that of the BRC register will contribute to filling the program BRAM. Call these transactions "BRAM-fill" writes. Although a command/address byte must still precede each data byte (as described for the serial microport), the values of the address fields for these “BRAM-fill” writes are ignored (except for the value 3fh, which designates the BRC register.) Instead, addresses are in ternally generated by the ZL38002 for each “BRAM-fill” write. Address generation for “BRAM-fill ” writes resumes where it left off following any read transaction while bootload mode is enabled. The first 4 096 "BRAM-fill" writes while bootload is enabled will load the memory, filling the BRAM and ignoring further writes. Before bootload mode is disabled, it is recommended that users then read back the value from the signat ure register (SIG) and compare with the one supplied by the factory along with the code. Equality verifies that the correct data has been loaded. The signature calculation uses an 8-bit MISR which only incorporates input from “BRAM-fill” writes. Resetting the bootload bit ( C2) in the BRC register to 0 (see Register Summary) exits bootload mode, resetting the signat ure (SIG) register and internal address generator for the next bootload. A hardware reset (RESET =0) similarly returns the ZL38002 to the ready state for the start of a bootload.

Zarlink Semiconductor Inc. Note: bits C 1 C0 are reserved, and must be set to zero. FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM) BRC Register Bits C3C2C1C0 X 1 0 0 R/W Address Data W 3fh (= 1 1 1 1 1 1 b) Writes "data" to BRC reg. - Bootload frozen; BRAM contents are NOT affected. W other than 3fh Writes "data" to next byte in BRAM (bootloading.) R 1 x x x x x b Reads back "data" = BRC reg value. - Bootload frozen; BRAM contents are NOT affected. R 0 x x x x x b Reads back "data" = SIG reg value. - Bootload frozen; BRAM contents are NOT affected. NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs) BRC Register Bits C3C2C1C0 X 0 0 0 R/W Address Data W any (= a5 a4 a3 a2 a1 a0 b) Writes "data" to corresponding DREG. R any (= a5 a4 a3 a2 a1 a0 b) Reads back "data" = corresponding DREG value. PROGRAM EXECUTION MODES C3C2C1C0 0 0 0 0 Execute program in ROM, bootload mode disabled. - BRAM address counter reset to initial (ready) state. - SIG register reseeded to initial (ready) state C3C2C1C0 0 1 0 0 Execute program in ROM, while bootloading the RAM. - BRAM address counter increments on microport writes (except to 3fh) - SIG register recalculates signature on microport writes (except to 3fh) C3C2C1C0 1 0 0 0 Execute program in RAM, bootload mode disabled. - BRAM address counter reset to initial (ready) state. - SIG register reseeded to initial (ready) state C3C2C1C0 1 1 0 0 - INVALID - Table 6 - Bootload RAM Control (BRC) Register States

Zarlink Semiconductor Inc. To begin execution from the RAM once the program has been loaded, the bootload mode must be disabled (BOOT bit, C2=0) and execution from RAM enabled (RAM_ROMb bit, C3=1) by setting the appropriate bits in the BRC register. During the bootload process, however, ROM program execution (RAM_ROMb bit, C3=0) should be selected. See Table 5 for the effect of the BRC register settings on Microport accesses and on program execution. Following program loading and enabling of execution from RAM, it is recommended that the user set the software reset bit in the Main Control (MC) register, to ensure that the device updates the default register values to those of the new program in RAM. Note: it is important to use a software reset rather than a hardware (RESET=0) reset, as the latter will return the device to its default settings (which includes execution from program ROM instead of RAM.) To verify which code revision is currently running, us ers can access the Firmware Revision Code (FRC) register (see Register Summary). This register reflects the identity code (revision number) of the last program to run register initialization (which follows a software or hardware reset.) Figure 8 - Serial Microport Timing for Intel Mode 0 R/W A0 A1 A2 A3 A4 A5 X COMMAND/ADDRESS DATA INPUT/OUTPUT DATA 1 SCLK CS Ð ƒ Ð ƒ This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38002. The ZL38002: outputs transmit data on the falling edge of SCLK The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high. A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 6 bits - Addressing Data 1 bit - Unused D0 D1 D2 D3 D4 D5 D6 D7 latches receive data on the rising edge of SCLK

Zarlink Semiconductor Inc. Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire XA0A1A2A3A4A5R/W COMMAND/ADDRESS DATA INPUT DATA 2 Receive DATA 1 Transmit SCLK CS Ð ƒ Ð ƒ This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38002. The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high. A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 6 bits - Addressing Data 1 bit - Unused D0D1D2D3D4D5D6D7 D0D1D2D3D4D5D6D7High Impedance DATA OUTPUT ¡ The ZL38002: outputs transmit data on the falling edge of SCLK latches receive data on the rising edge of SCLK

Zarlink Semiconductor Inc.

6.0 Register Summary

Any register not described in the following section should be labels reserved for internal use. Address CPU Access Page Reset Value Description 00H R/W 00 0 H Main Control Register 1 (MCR1) 01H R/W 00 0 H Main Control Register 2 (MCR2) 02H Read 0 Status Register (SR) 03H R/W 00 0 H DC Offset Register 04H R/W 0A 1 H High Pass Filter Constant Register (FLTSH) 05H R/W 00 8 H Mu Constant 07H Read 0 A6 H Bootload RAM Signature Register (SIG) 08H R/W 08 0 H Slow Adaptation Threshold Register 1 (SATR1) Slow Adaptation Threshold Register 2 (SATR2)09H R/W 0 0 4 H 12H R/W 0 00 H Automatic Sout Gain Reduction (SoutGR) 1CH R/W 08 8 H Customer Gain Control Register 1 (CGCR1) Customer Gain Control Register 2 (CGCR2)1DH R/W 00 8 H 20H R/W 06 D H Receive Gain Control Register (RGCR) 21H R/W 00 0 H Acoustic Echo Canceller Control Register (AECCR) 22H Read 0 00 H Acoustic Echo Canceller Status Register 1 (ARCSR1) Acoustic Echo Canceller Status Register 2 (AECSR2)23H Read 0 00 H 24H R/W 0 8 0 H Acoustic LMS Filter Length Register 1 (ALMSFR1) Acoustic LMS Filter Length Register 2 (ALMSFR2)25H R/W 03 E H 26H R/W 03 D H Decay Step Size Control Register (DSSCR) 27H R/W 00 6 H Decay Step Number Register (DSNR) 28H R/W 09 6 H Near-End Speech Detection Threshold 1 (NESDT1) Near-End Speech Detection Threshold 2 (NESDT2)29H R/W 00 4 H 30H R/W 08 0 H Double-Talk Hand-Over Time 1 (DTHOT1) Double-Talk Hand-Over Time 2 (DTHOT2)31H R/W 02 1 H 32H R/W 02 A H Automatic Rout Gain Reduction Register (RoutGR) 34H R/W 0A A H NLP Threshold Register 35H R/W 00 1 H 36H Read 0 00 H Send (Sin) Peak Detect Register 1 (SPDR1) Send (Sin) Peak Detect Register 2 (SPDR2)37H Read 0 00 H 38H Read 0 00 H Send Error Peak Detect Register 1 (SEPDR1) Send Error Peak Detect Register 2 (SEPDR2)39H Read 0 00 H Table 7 - Address Map

Zarlink Semiconductor Inc. 3AH Read 0 00 H Receive (Rout) Peak Detect Register 1 (RPDR1) Receive (Rout) Peak Detect Register 2 (RPDR2)3BH Read 0 00 H 3CH Read 0 00 H Adaptation Speed Register 1 (ASR1) Adaptation Speed Register 2 (ASR2)3DH Read 0 10 H 3FH R/W 0/1/2/3 08 H BRC Bootload RAM Control Register (BRCR) 1AH Read 1 00 H Noise Level R Path Register 1 (NLRPR1) Noise Level R Path Register 2 (NLRPR2)1BH Read 1 00 H 3AH Read 1 00 H Noise Level S Path Register 1 (NLSPR1) Noise Level S Path Register 2 (NLSPR2)3BH Read 1 00 H 1CH R/W 20 0 H AGC Gain Register 1 (AGCGR1) AGC Gain Register 2 (AGCGR2)1DH R/W 20 8 H 15H R/W 32 0 H Noise Threshold for Noise Reduction Register (NRTH) 17H R/W 32 0 H Minimum Noise Reduction Level Register(Beta) Address CPU Access Page Reset Value Description Table 7 - Address Map (continued)

Zarlink Semiconductor Inc.

7.0 Register Definitions

7 LIMIT When high, Rin and Sin signals ar e limited to 0.25 in amplitude. When low, no limit is imposed on the inputs.

6 MUTE_R When high, the Rin path is muted to quiet code (after the NLP) and when low

the Rin path is not muted.

5 MUTE_S When high, the Sin path is muted to quiet code (after the NLP) and when low

the Sin path is not muted.

4 BYPASS When high, the Send and Receive pa ths are transparently by-passed from

input to output and when low the Send and Receive paths are not bypassed.

3 NB- When high, Narrowband signal detectors in Rin and Sin paths are disabled

and when low the signal detectors are enabled. 2 AGC- When high, AGC is disabled and when low AGC is enabled.

1 AH- When high, the Howling detector is disabled and when low the Howling

detector is enabled.

0 RESET When high, the power initialization ro utine is executed presetting all registers

to default values. This bit automatically clears itself to’0’ when reset is complete. Register Table 1 - Main Control Register 1 (MC1) Bit Name Description SHFT When high and in 16-bit linear mode, th is bit enables shift right by 2 on inputs Sin, Rin, and shift left by 2 on output s Sout, Rout, for codec. If not in 16-bit linear mode for both I/O ports, this bit is ignored. When low, =default, no shift.

6 Reserved Reserved: Must be set to low

5 Reserved Reserved: Must be set to low

Register Table 2 - Main Control Register 2 (MC2) Read/Write Page 0, Address: 00H Reset Value: 00H 76543210 LIMIT MUTE_R MUTE_S BYPASS NB- AGC- AH- RESET Read/Write Address: 01H Reset Value: 00H 76543210 SHFT Reserved Reserved NRdis NSUP3 NSUP2 NSUP1 NSUP0

Zarlink Semiconductor Inc. Register Table 3 - Acoustic Echo Canceller Status Register Register Table 4 - DC Offset Register 4 NRDIS When high, noise reduction is disabled. When low, noise reduction is enabled. 3-0 NSUP Noise Suppression Threshold - Any value below this threshold in the send path will be suppressed (reset) Bit Name Description 7-6 Reserved Reserved: Must be set to low 5 HFLAG False howling detect bit.’1’ indicates’ false howling’ detected (music or sinusoidal match).’0’ indicates no ’false howling’, i.e. howling is not ruled out (by any matches to music or speech). Th e final howling decision is in bit 5 of ASR (HWLNG). 4-2 Reserved Reserved: Must be set to low

1 NB This bit indicates a LOGICAL-OR of status bits NBR + NBS (from ASR

register).

0 NBR When high, a narrowband signal has been detected in the Receive (Rin/Rout)

path. Bit Name Description 7-5 Reserved Reserved: Must be set to low 4-0 DC4-DC0 DC offset value in mute condition. Bit Name Description Register Table 2 - Main Control Register 2 (MC2) Read/Write Address: 01H Reset Value: 00H 76543210 SHFT Reserved Reserved NRdis NSUP3 NSUP2 NSUP1 NSUP0 Read/Write Page 0, Address:02H Reset Value: 00H 76543210 Reserved Reserved HFLAG Reserved Reserved Reserved NB NBR Read/Write Page 0, Address: 03H Reset Value: 60H 76543210 Reserved Reserved Reserved DC4 DC3 DC2 DC1 DC0

Zarlink Semiconductor Inc. Register Table 5 - High Pass Filter Constant Register (FLTSH) Register Table 6 - Mu Constant Register Bit Name Description 7-5 FR2-FR0 These four bits control the cut-off frequency of HPF at Rin. 4-0 F S4-FS0 These four bits control the cut-off frequency of HPF at Sin. Bit Name Description 7-0 MU5-0 This register allows the user to program control the adaptation speed. This register allows a maximum value of 3Fh. The default value is 08h corresponding to decimal value of 2.0. Decimal value of 1.0 is 04h. Lower values correspond to slower adaptation speed. Reserved. Write’0’. Read/Write Page 0, Address: 04H Reset Value: A1H 76543210 FR2 FR1 FR0 FS4 FS3 FS2 FS1 FS0 3 dB frequency and bit 0-4 for Sin 00: 2 KHz; 08: 2.65 Hz; 10: 3 KHz; 18: 3.6 Hz 01: 820 Hz; 09: 1.1 KHz; 11: 1.2 KHz; 19: 1.6 KH 02: 350 Hz; 0A: 450 Hz; 12: 580 Hz; 1A: 700 Hz 03: 160 Hz; 0B: 200 Hz; 13: 250 Hz; 1B: 300 Hz 04: 80 Hz; 0C: 100 Hz; 14: 125 Hz; 1C: 150 Hz 05: 40 Hz; 0D: 50 Hz; 15: 60 Hz; 1D: 70 Hz 06: 20 Hz; 0E: 25 Hz; 16: 30 Hz; 1E: 38 Hz 07: 10 Hz; 0F: 14 Hz; 17: 15 Hz; 1F: 18 Hz 3dB frequency and bit 5-7 for Rin 0: 2 KHz; 1; 820 Hz; 2: 350 Hz; 3: 160 Hz; 4: 80 Hz; 5: 40 Hz; 6: 20 Hz; 7: 10 Hz Read/Write Page 0, Address:05H Reset Value: 08H 76543210 RESV RESV MU 5 MU4 MU3 MU2 MU1 MU0

Zarlink Semiconductor Inc. Register Table 7 - Bootload RAM Signature Register (SIG) Register Table 8 - Slow Adaptation Threshold Registers (SATR1) & (SATR2) Bit Name Description 7-0 SIG7-0 This register provides the signature of the bootloaded data to verify error-free delivery into the device. Note: this register is only accessible if BOOT bit is high (bootload mode enabled) in the above BRC register. While bootload is disabled, the register value is held constant at its reset seed value of FFh. Bit Name Description 15-0 SAT15-SAT0 Threshold for deciding low adaptation speed. 8000h = 1.0. Read/Write Page 0, Address: 07H Reset Value: FFH 76543210 SIG7 SIG6 SIG5 SIG4 SIG3 SIG2 SIG1 SIG0 Read/Write Page 0, Address: 09H Reset Value: 04H 76543210 SAT15 SAT14 SAT13 SAT12 SAT11 SAT10 SAT9 SAT8 Read/Write Page 0, Address: 08H Reset Value: 80H 76543210 SAT7 SAT6 SAT5 SAT4 SAT3 SAT2 SAT1 SAT0

Zarlink Semiconductor Inc. Register Table 9 - Sout Gain Reduction (SoutGR) Register Table 10 - Customer Gain Control Registers (CGCR1) & (CGCR2) Bit Name Description 7 - 1 Reserved Reserved: Must be set to low

0 SoutGR This bit will provide an automatic si gnal reduction on Sout by 12 dB (far-end

speaker) when double talk is present with this bit set to 1. Bit Name Description 15-12 Reserved Reserved: Must be set to low 11-8 XRAMGain3-0 Gain control for ROUT to Xram, range from -24 dB to 21 dB. (1111=+21dB, 0000=-24 dB) 7-4 SoutGain3-0 Gain control for SOUT, range from -24 dB to 21 dB. ( 1111=+21dB, 0000=- 24 dB) 3-0 SinGain3-0 Gain control for SIN, range from -24 dB to 21 dB. (1111=+21dB, 0000=- 24 dB) Read/Write Page 0, Address: 12H Reset Value: 00H 76543210 Reserved Reserved Reserved Reserved Reserved Reserved Reserved SoutGR Read/Write Page 0, Address: 1DH Reset Value: 08H 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved XRAMGain3 XRAMGain2 XRAMGain1 XRAMGain0 Read/Write Page 0, Address: 1CH Reset Value: 88H 76543210 SoutGain3 SoutGain2 SoutGain1 SoutGain 0 SinGain3 SinGain3 S inGain3 SinGain3

Zarlink Semiconductor Inc. Register Table 11 - Receive Gain Control (RCGR) Bit Name Description 7-4 Reserved Reserved: Must be set to low 3 G3 User Gain Control on Rin/Rout path. (Tolerance of gain values: +/- 0.15 dB 2 G2 1 G1 0 G0 Read/Write Page 0, Address: 20H Reset Value: 00H 76543210 Reserved Reserved Reserved Reserved G3 G2 G1 G0 Gain Code: G4-G0 Gain(dB) data sheet Gain(dB) actual 00h -24 -24.08 01h -21 -21.31 02h -18 -18.06 03h -15 -14.91 04h -12 -12.04 05h -9 -9.08 06h -6 -6.02 07h -3 -3.06 08h +0 +0 09h +3 +3.01 0Ah +6 +5.99 0Bh +9 +9.01 0Ch +12 +12.01 0Dh +15 +15.03 0Eh +18 +18.03 0Fh +21 +21.05

Zarlink Semiconductor Inc. Register Table 12 - Acoustic Echo Canceller Control Register (AECCR) Bit Name Description

7 Reserved Reserved: Must be set to low

6 ASC- When high, internal adaptat ion speed control is disabled. When low, internal adaptation speed control is enabled. 5 NLP- When high, the non-linear processor in the Sin/Sout path is disabled. When low, the non-linear processor in the Sin/Sout path is enabled. 4 NJ- When high, the noise filtering process is disabled in the NLP. When low, the noise filtering process is enabled in the NLP. 3 HPF- When high, the offset nulling filt er is bypassed in the Sin/Sout path. When low, the offset nulling filter in the Sin/Sout path is active and will remove DC offset on the Rin input signal. 2 HCLR When high, the H register in the adaptive filter is cleared. When low, the H register is not cleared 1 ADAPT- When high, echo canceller adaptation is disabled. When low, the echo canceller adapts to the echo path characteristics.

0 ECBY When high, the echo estimate from th e adaptive filter is not subtracted from

the Send path. When low, the echo estimate is subtracted from the Send path. Read/Write Page 0, Address: 21H Reset Value: 00H 76543210 Reserved ASC- NLP- INJ- HPF- HCLR ADAPT- ECBY

Zarlink Semiconductor Inc. Register Table 13 - STATUS Acoustic Echo Canceller Status Register (AECSR1) Register Table 14 - Acoustic Echo Canceller Status register 2 (AECSR2) Bit Name Description 7 ACMUTH Energy comparison for mu value.’1’ indicates enough echo suppression. 6 ACMUND When low, indicates that the Rin/ Rout Receive path has no active signal. 5 HWLNG When high indicates that howling is occurring in the loop. A related ’false howling’ bit (HFLAG) in bit 5 of LSR is created as part of the howling-detect decision making. 4 NLPUTH Peak comparison with NLP up threshold.’1’ indicates not enough echo suppression. 3 NLPDC When high indicates that the NLP is activated. 2 DT When high, double-talk is present.

1 NB This bit indicates a LOGICAL-OR of status bits NBS + NBR (from LSR

register).

0 NBS When high, a narrowband signal has been detected in the Send (Sin/Sout)

path. Bit Name Description 7-4 Reserved 4 DHCLR Indicate the divergence of adaptation. "1" indicate s that strong divergence occurs with error energy is at least double the input signal energy. Reserved (anything written on it will be overwritten by temporary variable in the program). 3 ACMUFL Adaptation floor decision. ’1’ indica tes the reference is below the adaptation floor, no adaptation.

2 Reserved

1 ACMUNSP Indicates strong near-end speech.

0 Reserved

Read Page 0, Address: 22H Reset Value: 00H 76543210 ACMUTH ACMUND HWLNG NLPUTH NLPDCW DT NB NBS Read Page 0, Address: 23H Reset Value: 00H 76543210 Reserved Reserved Reserved DHCLR ACMUFL ACMULOW ACMUNSP NLPDCLD

Zarlink Semiconductor Inc. Register Table 15 - Acoustic LMS Filter Length Registers (ALMSFR1) & (ALMSFR2) Register Table 16 - Decay Step Size Control Register (DSSCR) Bit Name Description 6-0 F6-F0 Allows the acoustic LMS filter length to be reduced. The register value is in terms of milliseconds. 15-7 L7-L0 Maps to Rout limiter value, Limit = 0L 8L7L6 L5L4L3L2 L1L000 0000, Range: 040h - 7FC0h, plus 00h point value. Default: 1F40h Bit Name Description 7-3 L4-L0 Sout Limit Value : Stores the variable limit for Sout. The interpretation of these bits is not direct: 00111 maps to default value = 1F40h. Limit level = 4L3L2 L1L011 0100 0000, range: 0340h - 7F40h. 2-0 SSC2-SSC0 Decay Step Size Control : This register controls the step size (SS) to be used during the exponential decay of MU. Read/Write Page 0, Address: 25H Reset Value: 3EH Read/Write Page 0, Address: 24H Reset Value: 80H 15 14 13 12 11 10 9 8 L7 L6 L5 L5 L4 L3 L2 L1 76543210 L0 F6 F5 F4 F3 F2 F1 F0 Read/Write Page 0, Address: 26H Reset Value: 3DH 76543210 L4 L3 L2 L1 L0 SSC2 SSC1 SSC0

Zarlink Semiconductor Inc. Register Table 17 - Decay Step Number Register (DSNR) Bit Name Description 7-0 NS7-NS0 Decay Step Number : This register defines t he number of steps to be used for the decay of MU where each step has a period of SS taps (see SSC2-0). Read/Write Page 0, Address: 27H Reset Value: 06H 76543210 NS7 NS6 NS5 NS4 NS3 NS2 NS1 NS0 Amplitude of MU Time Step Size (SS) 1.0 2-16 FIR Filter Length (896 taps) Number of Steps (NS7-0) The Exponential Decay registers (Decay Step Number and Decay Step Size) allow the LMS adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the echo response is known to have a roughly exponen tial decay of the echo impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the adaptive filter. Note that in the following register descriptions, one tap is equivalent to 125 ms. SSC2-0 Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4 x2 SSC2-0. For example; If SSC 2-0 = 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default value of SSC2-0 is 05h. L4-0 Sout Limit Value : Stores the variable limit for Sout. The interpretation of these bits is not direct: 00111 maps to default value = 1F40h. Limit level = 0L 4L3L2 L1L011 0100 0000 , range: 0340h - 7F40h. NS7-0 Decay Step Number : This register defines the number of steps to be used for the decay of MU where each step has a period of SS taps (see SSC2-0). The start of the exponential decay is defined as: Filter Length (896) - [Decay Step Number (NS7-0) x Step Size (SS)] where SS = 4 x2 SSC2-0. For example, if NS7-0=4 and SSC2-0=4, then the exponential decay start value is 896 - [NS7-0 x SS] = 896 - [4 x (4x2 4)] = 640 taps for a filter length of 896 taps.

Zarlink Semiconductor Inc. Register Table 18 - Near-End Speech Detection Threshold Registers (NESDT1) & (NESDT2) Register Table 19 - Near-End Speech Detection Threshold Registers (DTHOT1) & (DTHOT2) Bit Name Description 15-0 MUURAT15- MUURAT0 Threshold for deciding near end speech (mu = 0). 1000h = 1.0. Bit Name Description 13-15 DTTH2DTTH0 Double Talk Threshold- in 6 dB increments from -30 dB to (0h = -30 dB, 7h = +12 dB 12-0 DTHOT12-DTHOT0 Double-Talk hand-over time Read/Write Page 0, Address: 29H Reset Value: 04H 15 14 13 12 11 10 9 8 MUURAT15 MUURAT14 MUURAT13 MUURAT12 MUURAT11 MUURAT10 MUURAT9 MUURAT8 Read/Write Page 0, Address: 28H Reset Value: 96H 76543210 MUURAT7 MUURAT6 MUURAT15 MUURAT4 MUURAT3 MUURAT2 MUURAT1 MUURAT0 Read/Write Page 0, Address: 31H Reset Value: 04H 15 14 13 12 11 10 9 8 DTTH2 DTTH1 DTTH1 DTHOT12 DTHOT11 DTHOT10 DTHOT9 DTHOT8 Read/Write Page 0, Address: 30H Reset Value: 96H 76543210 DTHOT7 DTHOT6 DTHOT5 DTHOT4 DTHOT3 DTHOT2 DTHOT1 DTHOT0

Zarlink Semiconductor Inc. Figure 10 - Automatic Rout Gain Reduction (RoutGR) Register Table 20 - NLP Threshold Register Bit Name Description

0 RoutGR This bit will provide an automatic signal reduction on Rout by 12 db when

double talk is present with this bit set to 1. Bit Name Description 15-0 NLPTH15- NLPTH0 This register allows the user to program the level of the Non-Linear Processor Threshold. The 16 bit 2’s complement linear value defaults to 1AAh. The maximum value is 7FFFh = 0.9999. Higher value corresponds to higher threshold. The high byte is in Register 2 and the low byte is in Register 1. Read/Write Page 0, Address: 32H Reset Value: 2AH 76543210 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RoutGR Read/Write Page 01, Address: 35H Reset Value: 01H 15 14 13 12 11 10 9 8 NLPTH15 NLPTH14 NLPTH13 NLPTH12 NLPTH11 NLPTH10 NLPTH9 NLPTH8 Read/Write Page AA, Address: 34H Reset Value: AAH 76543210 NLPTH7 NLPTH6 NLPTH15 NLPTH4 NLPTH3 NLPTH2 -NLPTH1 NLPTH0

Zarlink Semiconductor Inc. Register Table 21 - Send (Sin) Peak Detect Registers (SPDR1) & (SPDR2) Register Table 22 - Send Error Peak Detect Registers (SEPDR1) & (SEPDR2) Bit Name Description 15-0 SIPD15-SIPD0 These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level at reference point S 1 (see Figure 1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1. Bit Name Description 15-0 SEPD15-SEPD0 These peak detector registers allow the user to monitor the error signal peak level in the Send path at reference point S 2 (see Figure 1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1. Read/Write Page 0, Address: 37H Reset Value: 00H 15 14 13 12 11 10 9 8 SIPD15 SIPD14 SIPD13 SIPD12 SIPD11 SIPD10 SIPD9 SIPD8 Read/Write Page 0, Address: 36H Reset Value: 00H 76543210 SIPD7 SIPD6 SIPD15 SIPD4 SIPD3 SIPD2 SIPD1 SIPD0 Read/Write Page 0, Address: 39H Reset Value: 00H 15 14 13 12 11 10 9 8 SEPD15 SEPD14 SEPD13 SEPD12 SEPD11 SEPD10 SEPD9 SEPD8 Read/Write Page 0, Address: 38H Reset Value: 00H 76543210 SEPD7 SEPD6 SEPD15 SEPD4 SEPD3 SEPD2 SEPD1 SEPD0

Zarlink Semiconductor Inc. Register Table 23 - Receive (Rout) Peak Detect Registers (RPDR1) & (RPDR2) Bit Name Description 15-0 ROPD15- ROPD0 These peak detector registers allow the user to monitor the receive out signal (Rout) peak signal level at reference point R1 (see Figure 1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register 2 and the low byte is in Register 1. Bit Name Description 15-0 A_AS15-0 Actual mu sent to acoustic LMS. This register is where we can feed externally calculated mu value. This register allows the user to program control the adaptation speed. The default value is 1000h corresponding to decimal value of 2.0. The high byte is in Register 2 and the low byte is in Register 1. Smaller values correspond to slower adaptation speed. Register Table 24 - Adaptation Speed Registers (ASR1) & (ASR2) Read/Write Page 0, Address: 3BH Reset Value: 00H 15 14 13 12 11 10 9 8 ROPD15 ROPD14 ROPD13 ROPD12 ROPD11 ROPD10 ROPD9 ROPD8 Read/Write Page 0, Address: 3AH Reset Value: 00H 76543210 ROPD7 ROPD6 ROPD15 ROPD4 ROPD3 ROPD2 ROPD1 ROPD0 Read/Write Page 0, Address: 3DH Reset Value: 10H 15 14 13 12 11 10 9 8 A_AS15 A_AS14 A_AS13 A_AS12 A_AS11 A_AS10 A_AS9 A_AS8 Read/Write Page 0, Address: 3CH Reset Value: 00H 76543210 A_AS7 A_AS6 A_AS5 A_AS4 A_AS3 A_AS2 A_AS1 A_AS0

Zarlink Semiconductor Inc. Register Table 25 - BRC Bootload RAM Control Register (BRCR) Register Table 26 - Noise Level Registers R Path (NLRPR1) & (NLRPR2) Bit Name Description 7-4 Unused Must be set to 0 3 RAM/ROM When high, device executes from RAM. When low, device executes from ROM. 2 BOOT BIT When high, puts device in bootload mode. When low, bootload is disabled. 1 PAGE H Controls the register page being accessed by address 00h-3Fh. 00 = page 0 (default), 01 = page 1, 10= page 2, 11 = page 30 PAGE L Bit Name Description 15-0 NLVRL15-0 Estimated noise level in R path. Read/Write Page 0/1/2/3, Address: 3FH Reset Value: 00H 76543210 - - - - ROM/RAM BOOT BIT PAGEH PAGEL Read/Write Page 1, Address: 1BH Reset Value: 10H 15 14 13 12 11 10 9 8 NLVRL15 NLVRL14 NLVRL13 NLVRL12 NLVRL11 NLVRL10 NLVRL9 NLVRL8 Read/Write Page 1, Address: 1AH Reset Value: 00H 76543210 NLVRL7 NLVRL6 NLVRL5 NLVRL4 NLVRL3 NLVRL2 NLVRL1 NLVRL0

Zarlink Semiconductor Inc. Register Table 27 - Noise Level S Path Registers (NLSPR1) & (NLSPR2) Register Table 28 - AGC Gain Register (AGCGR1) & (AGCGR2) Bit Name Description 15-0 NLVRL15-0 Estimated noise level in S path. Bit Name Description 15-0 AGCGN15-0 AGC gain value (1=4000h) Read/Write Page 1, Address: 3BH Reset Value: 00H 15 14 13 12 11 10 9 8 NLVSL15 NLVSL14 NLVSL13 NLVSL12 NLVSL11 NLVSL10 NLVSL9 NLVSL8 Read/Write Page 1, Address: 3AH Reset Value: 00H 76543210 NLVSL7 NLVSL6 NLVSL5 NLVSL4 NLVSL3 NLVSL2 NLVSL1 NLVSL0 Read/Write Page 2, Address: 1DH Reset Value: 08H 15 14 13 12 11 10 9 8 AGCGN15 AGCGN14 AGCGN13 AGCGN12 AGCGN11 AGCGN10 AGCGN9 AGCGN8 Read/Write Page 2, Address: 1CH Reset Value: 00H 76543210 AGCGN7 AGCGN6 AGCGN5 AGCGN4 AGCGN3 AGCGN2 AGCGN1 AGCGN0

Zarlink Semiconductor Inc. Register Table 29 - Noise Threshold for Noise Reduction Register (NRTH) Register Table 30 - Noise reduction Register Bit Name Description 7-0 NRTH7-0 This register scales the no ise threshold for noise reduction. Bit Name Description 7-0 BETA7-0 This register sets the mi nimum noise reduction for each sample. Read/Write Page 3, Address: 15H Reset Value: 20H 76543210 NRTH7 NRTH6 NRTH5 NRTH4 NRTH3 NRTH2 NRTH1 NRTH0 Read/Write Page 3, Address: 17H Reset Value: 20H 76543210 BETA7 BETA6 BETA5 BETA4 BETA3 BETA2 BETA1 BETA0

Zarlink Semiconductor Inc.

8.0 Electrical Characteristics

• Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. *DC Electrical Characteristics are over recommended temperature and supply voltage. Absolute Maximum Ratings* Parameter Symbol Min. Max. Units 1 Supply Voltage V DD-VSS -0.5 5.0 V 2 Input Voltage V i VSS-0.3 5.5 V 3 Output Voltage Swing V o VSS-0.3 5.5 V

4 Continuous Current on any digital pin I i/o ±20 mA

5 Storage Temperature T ST -65 150 °C

6 Package Power Dissipation P D 90 (typ) mW

Recommended Operating Conditions - Voltages are with respect to ground (V SS) unless otherwise stated. Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Supply Voltage V DD 2.7 3.3 3.6 V 2 Input High Voltage 1.4 V DD V 3 Input Low Voltage V SS 0.4 V

4 Operating Temperature T A -40 +85 °C

Characteristics Min. Typ. Max. Units Test Conditions

1 Acoustic Echo Return 6 dB Measured from Rout -> Sin (using the

Customer Gain Control registers) Characteristics Sym. Min. Typ. ‡ Max. Units Conditions/Notes Standby Supply Current: I CC 37 0 µA RESET = 0 Operating Supply Current: I DD 20 mA RESET = 1, clocks active 2 Input HIGH voltage V IH 0.7VDD V 3 Input LOW voltage V IL 0.3VDD V 4 Input leakage current I IH/IIL 0.1 10 µAV IN=VSS to VDD 5 High level output voltage V OH 0.8 VDD VI OH=2.5 mA 6 Low level output voltage V OL 0.4V V I OL=5.0 mA

7 High impedance leakage I OZ 11 0 µAV IN=VSS to VDD

8 Output capacitance C o 10 pF

9 Input capacitance C i 8p F

Zarlink Semiconductor Inc. † Timing is over recommended temperature and power supply voltages. Characteristics Sym. Min. Typ. Max. Units Test Notes 1 MCLK Frequency f CLK 19.15 20.5 MHz

2 BCLK/C4i Clock High t BCH,

3 BCLK/C4i Clock Low t BLL,

4 BCLK/C4i Period t BCP 240 7900 ns

5 SSI Enable Strobe to Data Delay (first

bit) tSD 80 ns C L = 150 pF

6 SSI Data Output Delay (excluding

first bit) tDD 80 ns C L = 150 pF

7 SSI Output Active to High Impedance t AHZ 80 ns C L = 150 pF

8 SSI Enable Strobe Signal Setup t SSS 10 t BCP

-15 ns

9 SSI Enable Strobe Signal Hold t SSH 15 t BCP

-10 ns

10 SSI Data Input Setup t DIS 10 ns

11 SSI Data Input Hold t DIH 15 ns

12 ST-BUS/GCI F0i Setup t F0iS 20 150 ns

13 ST-BUS/GCI F0i Hold t F0iH 20 150 ns

14 ST-BUS/GCI Data Output delay t DSD 80 ns C L = 150 pF

15 ST-BUS/GCI Output Active to High

tASHZ 80 ns C L = 150 pF

16 ST-BUS/GCI Data Input Hold time t DSH 20 ns

17 ST-BUS/GCI Data Input Setup time t DSS 20 ns

Zarlink Semiconductor Inc. † Timing is over recommended temperature range and recommended power supply voltages. Figure 11 - Master Clock - MCLK Characteristics Sym. Min. Typ. Max. Units Test Notes

1 Input Data Setup t IDS 30 ns

2 Input Data Hold t IDH 30 ns

3 Output Data Delay t ODD 100 ns C L = 150 pF

4 Serial Clock Period t SCP 500 ns

5 SCLK Pulse Width High t SCH 250 ns

6 SCLK Pulse Width Low t SCL 250 ns

7 CS Setup-Intel t CSSI 200 ns

8C S Setup-Motorola t CSSM 100 ns 9C S Hold t CSH 100 ns

10 CS to Output High Impedance t OHZ 100 ns C L = 150 pF

Characteristic Symbol CMOS Level Units CMOS reference level V CT 0.5*VDD V Input HIGH level V H 0.9*VDD V Input LOW level V L 0.1*VDD V Rise/Fall HIGH measurement point V HM 0.7*VDD V Rise/Fall LOW measurement point V LM 0.3*VDD V Table 8 - Reference Level Definition for Timing Measurements MCLK (I) VH VL VCT T=1/fCLK Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions)

Zarlink Semiconductor Inc. Figure 16 - Motorola Serial Microport Timing DATA2 (I) VH VL VCT SCLK (I) VH VL VCT CS (I) VH VL VCT DATA1 (O) VCT tIDS tIDH tODD tCSSM tCSH tOHZ tSCH tSCL tSCP (Input) (Output) Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions)

APPRD. c Zarlink Semiconductor 2004. All rights reserved.

APPRD. c Zarlink Semiconductor 2003 All rights reserved. ISSUE Previous package codes Package Code

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