MT9173AE

MT9173 MITEL | Alldatasheet

Document overview

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Technical content

Features

• Receive sync output pulse
• Full duplex transmission over a single twisted pair
• Selectable 80 or 160 kbit/s line rate
• Adaptive echo cancellation
• Up to 3km (9173) and 4 km (9174) loop reach
• ISDN compatible (2B+D) data format
• Transparent modem capability
• Frame synchronization and clock extraction
• MITEL ST -BUS compatible
• Low power (typically 50 mW), single 5V supply

Applications

• T DD Digital PCS (DECT, CT2, PHS) base stations requiring cell synchronization
• Digital subscriber lines
• High speed data transmission over twisted wires
• Digital PABX line cards and telephone sets
• 80 or 160 kbit/s single chip modem Figure 1 - Functional Block Diagram DSTi/Di CDSTi/ F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 RegC DSTo/Do CDSTo/ CDo Transmit Interface Prescrambler Scrambler Control Register Transmit/ Clock Receive Timing & Control Status Transmit Timing Master Clock Phase Locked Sync Detect Receive DPLL Receive Interface De - Prescrambler Descrambler Differentially Encoded Biphase Receiver Differentially Encoded Biphase Transmitter Transmit Filter & Line Driver Receive Filter MUX Address Echo Canceller Error Signal Echo Estimate V Bias VDD VSS VBias VRef LOUT LOUT DIS Precan LIN OSC2 OSC1 CDi RxSB ISSUE 2 March 1997

Description

The MT9173 (DSIC) and MT9174 (DNIC) are functionally identical to the MT9171/72 except for the addition of one feature. The MT9173/74 include a digital output pin indicating the temporal position of the received "SYNC" bit of the biphase transmission. This feature is especially useful for systems such as PCS wireless base station applications requiring close synchronization between microcells. The MT9173 and MT9174 are identical except for the MT9173 having a shorter loop reach. The generic "DNIC" will be used to reference both devices unless otherwise noted. The MT9173/74 are fabricated in Mitel’s ISO 2-CMOS process.

Ordering Information

MT9173AE 24 Pin Plastic DIP (300mil) MT9173AN 24 Pin SSOP MT9173AP 28 Pin PLCC MT9174AE 24 Pin Plastic DIP (300 mil) MT9174AN 24 Pin SSOP MT9174AP 28 Pin PLCC -40°C to +85°C MT9173/74 Digital Subscriber Interface CircuitwithRxSB Digital Network Interface CircuitwithRxSB ISO2-CMOS ST -BUS FAMIL Y

MT9173/74 Preliminary Information 9-138 Figure 2 - Pin Connections Pin Description Pin # Name Description 24 28 12 L OUT Line Out.Transmit Signal output (Analog). Referenced to VBias. 23 V Bias Internal Bias Voltage output. Connect via 0.33µF decoupling capacitor to VDD . 34 V Ref Internal Reference Voltage output. Connect via 0.33µF decoupling capacitor to VDD . 4,5, 5,7, MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the various operating modes for a particular application. See Table 1 for the operating modes. 7 9 RegC Regulator Control output (Digital). A 512 kHz clock used for switch mode power supplies. Unused in MAS/MOD mode and should be left open circuit. 8 10 RxSB Receive Sync Bit output (Digital). In DN mode, this output is held high until receive synchronization occurs (i.e., until the sync bit in Status Register =1). Once low, indicating synchronized transmission, a high going pulse (6.24µs wide pulse @ 160 kb/s and 12.5µs wide @ 80 kb/s) indicates the temporal position of the receive "SYNC" bit in the biphase line transmission. Inactive and low in MOD mode. 91 1 F0/CLD Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative pulse input for the MASTER indicating the start of the active channel times of the device. Output for the SLAVE indicating the start of the active channel times of the device. Output in MOD mode providing a pulse indicating the start of the C-channel. 10 12 CDSTi/ CDi Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control & signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 11 13 CDSTo/ CDo Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial control & signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 12 14 V SS Negative Power Supply (0V). 13 15 DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 14 16 DSTi/Di Data ST-BUS In/Data In(Digital). A 2.048 Mbit/s serial PCM/data input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.

28 PIN PLCC

24 PIN PDIP/ SSOP

Preliminary Information MT9173/74 9-139 15 17 F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns wide negative pulse indicating the end of the active channel times of the device to allow daisy chaining. In MOD mode provides the receive bit rate clock to the system. 16 19 C4/TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin provides the transmit bit rate clock to the system. 17 21 OSC2 Oscillator Output. CMOS Output. Characteristics for OSC1 input requirements. 20 23 Precan Precanceller Disable. When held to Logic ’1’ ,the internal path from LOUT to the precanceller is forced to VBias thus bypassing the precanceller section. When logic ’0’, the LOUT to the precanceller path is enabled and functions normally. An internal pulldown (50 kΩ ) is provided on this pin. 18 1,6, 18, 20, NC No Connection. Leave open circuit 21 24 L OUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When logic “0”, LOUT functions normally. An internal pulldown (50 kΩ ) is provided on this pin. 22 26 TEST Test Pin. Connect to VSS . 23 27 L IN Receive Signalinput (Analog). 24 28 V DD Positive Power Supply (+5V) input. Pin Description (continued) Pin # Name Description 24 28

Preliminary Information MT9173/74 9-141 Functional Description The MT9173 and MT9174 are multifunction devices capable of providing high speed, full duplex digital transmission at up to 160 kbit/s over a twisted wire pair. They use adaptive echo-cancelling techniques and transfer data in a format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including PCS wireless base stations, smart telephone sets, workstations, data terminals and computers. The device supports the 2B+D channel format (two 64 kbit/s B-channels and one 16 kbit/s D- channel) over two wires as recommended by the CCITT. The line data is converted to and from the ST -BUS format on the system side of the network to allow for easy interfacing with other components such as the S-interface device in an NT1 arrangement, or to digital PABX components. Smart telephone sets with data and voice capability can be easily implemented using the MT9173/74 as a line interface. The device’s high bandwidth and long loop length capability allows its use in a wide variety of sets. This can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in both the home and central office or remote concentration equipment. Within the subscriber equipment the MT9173/74 would terminate the line and encode/ decode the data and voice for transmission while additional electronics could provide interfaces for a standard telephone set and any number of data ports supporting standard data rates for such things as computer communications and telemetry for remote meter reading. Digital workstations with a high degree of networking capability can be designed using the DNIC for the line interface, offering up to 160 kbit/s data transmission over existing telephone lines. The MT9173/74 could also be valuable within existing computer networks for connecting a large number of terminals to a computer or for intercomputer links. With the DNIC, this can be accomplished at up to 160 kbit/s at a very low cost per line for terminal to computer links and in many cases this bandwidth would be sufficient for computer to computer links. Figure 1 shows the block diagram of the MT9173/74. The DNIC provides a bidirectional interface between the DV (data/voice) port and a full duplex line operating at 80 or 160 kbit/s over a single pair of twisted wires. The DNIC has three serial ports. The DV port (DSTi/Di, DSTo/Do), the CD (control/data) port (CDSTi/CDi, CDSTo/CDo) and a line port (L IN, LOUT ). The data on the line is made up of information from the DV and CD ports. The DNIC must combine information received from both the DV and CD ports and put it onto the line. At the same time, the data received from the line must be split into the various channels and directed to the proper ports. The usable data rates are 72 and 144 kbit/s as required for the basic rate interface in ISDN. Full duplex transmission is made possible through on board adaptive echo cancellation. The DNIC has various modes of operation which are selected through the mode select pins MS0-2. The two major modes of operation are the MODEM (MOD) and DIGITAL NETWORK (DN) modes. MOD mode is a transparent 80 or 160 kbit/s modem. In DN mode the line carries the B and D channels formatted for the ISDN at either 80 or 160 kbit/s. In the DN mode the DV and CD ports are standard ST - BUS and in MOD mode they are transparent serial data streams at 80 or 160 kbit/s. Other modes include: MASTER (MAS) or SLAVE (SLV) mode, where the timebase and frame synchronization are provided externally or are extracted from the line and DUAL or SINGLE (SINGL) port modes, where both the DV and CD ports are active or where the CD port is inactive and all information is passed through the DV port. For a detailed description of the modes see “Operating Modes” section. In DIGITAL NETWORK (DN) mode there are three channels transferred by the DV and CD ports. They are the B, C and D channels. The B1 and B2 channels each have a bandwidth of 64 kbit/s and are used for carrying PCM encoded voice or data. These channels are always transmitted and received through the DV port (Figures 3, 4, 5, 6). The C- channel, having a bandwidth of 64 kbit/s, provides a means for the system to control the DNIC and for the DNIC to pass status information back to the system. The C-channel has a Housekeeping (HK) bit which is the only bit of the C-channel transmitted and received on the line. The 2B+D channel bits and the HK bit are double-buffered. The D-channel can be transmitted or received on the line with either an 8, 16 or 64 kbit/s bandwidth depending on the DNIC’s mode of operation. Both the HK bit and the D- channel can be used for end-to-end signalling or low speed data transfer. In DUAL port mode the C and D channels are accessed via the CD port (Figure 7) while in SINGL port mode they are transferred through the DV port (Figures 5, 6) along with the B1 and B2 channels.

Preliminary Information MT9173/74 9-143 In DIGITAL NETWORK (DN) mode, upon entering the DNIC from the DV and CD ports, the B-channel data, D-channel D0 (and D1 for 160 kbit/s), the HK bit of the C-channel (160kbit/s only) and a SYNC bit are combined in a serial format to be sent out on the line by the Transmit Interface (Figures 11, 12). The SYNC bit produces an alternating 1-0 pattern each frame in order for the remote end to extract the frame alignment from the line. It is possible for the remote end to lock on to a data bit pattern which simulates this alternating 1-0 pattern that is not the true SYNC. To decrease the probability of this happening the DNIC may be programmed to put the data through a prescrambler that scrambles the data according to a predetermined polynomial with respect to the SYNC bit. This greatly decreases the probability that the SYNC pattern can be reproduced by any data on the line. In order for the echo canceller to function correctly, a dedicated scrambler is used with a scrambling algorithm which is different for the SLV and MAS modes. These algorithms are calculated in such a way as to provide orthogonality between the near and far end data streams such that the correlation between the two signals is very low. For any two DNICs on a link, one must be in SLV mode with the other in MAS mode. The scrambled data is differentially encoded which serves to make the data on the line polarity-independent. It is then biphase encoded as shown in Figure 10. See “Line Interface” section for more details on the encoding. Before leaving the DNIC the differentially encoded biphase data is passed through a pulse-shaping bandpass transmit filter that filters out the high and low frequency components and conditions the signal for transmission on the line. The composite transmit and receive signal is received at L IN. On entering the DNIC this signal passes through a Precanceller which is a summing amplifier and lowpass filter that partially cancels the near-end signal and provides first order antialiasing for the received signal. Internal, partial cancellation Figure 7 - CD Port (Modes 2,6) Figure 8 - CD Port (Modes 1,5) CDSTo CDSTi F0o C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 C 0 C 0 3.9µsec 62.5µsec 125 µsec Channel Time 0 Channel Time 16 CLD TCK CDi CDo C

0 C 1 C 2 C 3 C 4 C 5 C 6 C 7C 6 C 7 C 0 C 1

C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7C 6 C 7 C 0 C 1

subtracted from the precancelled received signal. comparator and passed to the biphase receiver. this new estimate is stored back in RAM. the following devices receiving its predecessor’sF0o. In MOD mode, all the ports have a different format. clocks for transmit and receive data, respectively. relationship to the data on the DV port. Table 1. Mode Select Pins

whether DN or MOD mode is used. SINGL port option only exists in DN mode. Table 2. Mode Definitions Table 3. Pin Configurations and the DV port transferring the B1& B2 channels. port is disabled and CDSTi should be pulled high.

2.048 Mbits/s and the line at 80 or 160 kbits/s configured according to the applicable ISDN

-The D-channel is transferred before the C-channel followingF0. C-D C BEFORE D-CHANNEL -The C-channel is transferred before the D-channel followingF0. modes of operation DV and CD ports are enabled during the appropriate channel times.

0 F0 Input F0o Output C4 Input

1 CLD Output RCK Output TCK Output

2 F0 Input F0o Output C4 Input

3 F0 Input F0o Output C4 Input

4 F0 Output F0o Output C4 Output

5 CLD Output RCK Output TCK Output

6 F0 Output F0o Output C4 Output

7 F0 Input F0o Output C4 Input

MT9173/74 Preliminary Information 9-146 determine which of the DNICs is using the externally supplied clock and which is phase locking to the data on the line. Due to jitter and end to end delay, one end must be the master to generate all the timing for the link and the other must extract the timing from the receive data and synchronize itself to this timing in order to recover the synchronous data. DUAL port mode allows the user to use two separate serial busses: the DV port for PCM/data (B channels) and the CD port for control and signalling information (C and D channels). In the SINGL port mode, all four channels are concatenated into one serial stream and input to the DNIC via the DV port. The order of the C and D channels may be changed only in DN/ DUAL mode. The DNIC may be configured to transfer the D-channel in channel 0 and the C- channel in channel 16 or vice versa. One other feature exists; ODE, where both the DV and CD ports are tristated in order that no devices are damaged due to excessive loading while all DNICs are in a random state on power up in a daisy chain arrangement. DV Port (DSTi/Di, DSTo/Do) The DV port transfers data or PCM encoded voice to and from the line according to the particular mode selected by the mode select pins. The modes affecting the configuration of the DV port are MOD or DN and DUAL or SINGL. In DN mode the DV port operates as an ST -BUS at 2.048 Mbit/s with 32, 8 bit channels per frame as shown in Figure 9. In this mode the DV port channel configuration depends upon whether DUAL or SINGL port is selected. When DUAL port mode is used, the C and D channels are passed through the CD port and the B1 and B2 channels are passed through the DV port. At 80 kbit/s only one channel of the available 32 at the DV port is utilized, this being channel 0 which carries the B1-channel. This is shown in Figure 3. At 160 kbit/s, two channels are used, these being 0 and 16 carrying the B1 and B2 channels, respectively. This is shown in Figure 4. When SINGL port mode is used, channels B1, B2, C and D are all passed via the DV port and the CD port is disabled. See CD port description for an explanation of the C and D channels. The D-channel is always passed during channel time 0 followed by the C and B1 channels in channel times 1 and 2, respectively for 80 kbit/s. See Figure 5. For 160 kbit/s the B2 channel is added and occupies channel time 3 of the DV port. See Figure 6. For all of the various configurations the bit orders are shown by the respective diagram. In MOD mode the DV and CD ports no longer operate at 2.048 Mbits/s but are continuous serial bit streams operating at the bit rate selected of 80 or 160 kbit/s. While in the MOD mode only DUAL port operation can be used. In order for more than one DNIC to be connected to any one DV and CD port, making more efficient use of the busses, the DSTo and CDSTo outputs are put into high impedance during the inactive channel times of the DNIC. This allows additional DNICs to be cascaded onto the same DV and CD ports. When used in this way a signal called F0o is used as an indication to the next DNIC in a daisy chain that its channel time is now active. Only the first DNIC in the chain receives the system frame pulse and all others receive the F0o from its predecessor in the chain. This allows up to 16 DNICs to be cascaded. CD Port (CDSTi/CDi, CDSTo/CDo) The CD port is a serial bidirectional port used only in DUAL port mode. It is a means by which the DNIC receives its control information for things such as setting the bit rate, enabling internal loopback tests, sending status information back to the system and transferring low speed signalling data to and from the line. The CD port is composed of the C and D-Channels. The C-channel is used for transferring control and status information between the DNIC and the system. The D-channel is used for sending and Figure 9 - ST-BUS Format Channel Channel Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 125 µsec Channel Channel Channel Channel Channel ST-BUS Most Significant Bit (First) Least Significant Bit (Last) 3.9µsec

while transmitting a C-channel on CDSTo. transmitted on CDSTo. This is shown in Figure 7. 1 for a listing of the byte orientations. received in the B1-channel timeslot. written to the Diagnostics Register (Table 5). Table 4. Control Register -At 160 kbit/s full convergence requires 850 ms with ATTACK held high for the first 240 frames or 30 ms. -At 80 kbit/s full convergence requires 1.75 s with ATTACK held high for the first 480 frames or 60 ms. depending upon the status of bit-3. 0 Reg Sel-1 Register Select-1. Must be set to ’0’ to select the Control Register. 1 Reg Sel-2 Register Select-2. Must be set to ’0’ to select the Control Register. "1", the Diagnostics Register will not be reset. 3 BRS Bit Rate Select. When set to ’0’ selects 80 kbit/s. When set to ’1’, selects 160 kbit/s.

4 DINB

timeslot on the line providing a 64 kbit/s D-channel link.

5 PSEN

6 ATTACK

canceller will require the normal amount of time to converge to a reflection coefficient.

➂ Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode. ➃ Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode. Table 5. Diagnostic Register depending upon the status of bit-3. ➁ Do not use LOUT to LIN loopback in DN/SLV mode. ➂ Do not use DSTo to DSTi loopback in MOD/MAS mode. PSEN, DINB, DRR and all diagnostics are disabled. PSEN, DINB, DRR and all diagnostics are disabled. 0 Reg Sel-1 Register Select-1. Must be set to ’0’ to select the Diagnostic Register. 1 Reg Sel-2 Register Select-2. Must be set to ’1’ to select the Diagnostic Register. 0 0 All loopback testing functions disabled. Normal operation. 0 1 DSTi internally looped back into DSTo for system diagnostics. recovery circuitry. When set to ’0’, the operation continues in synchronization. ’0’, LOUT pin functions normally. 7 Not Used Must be set to ’0’ for normal operation.

Table 6. Status Register

0 SYNC Synchronization - When set this bit indicates that synchronization to the received

line data sync pattern has been acquired. For DN mode only. noise. The farther this 2 bit value is from 0 the better the SNR. 3 Rx HK Housekeeping - This bit is the received housekeeping (HK) bit from the far end. 4-6 Future Future Functionality.These bits return Logic 1 when read. return a logic “0” for this bit. positive going transition indicating a logic "1". which are critical for adaptive echo cancellation. extraction at the receiving end. There is no D.C. made available to be put onto the line biased at VBias. B2 channels are transmitted.

Preliminary Information MT9173/74 9-151 Typical connection diagrams are shown in Figures 13 and 14 for the DN mode as a MASTER and SLAVE, respectively. L OUT is connected to the coupling transformer through a resistor R2 and capacitors C2 and C2’ to match the line characteristic impedance. Suggested values of R2, C2 and C2’ for 80 and 160 kbit/s operation are provided in Figures 13 and 14. Overvoltage protection is provided by R1, D1 and D2. C1 is present to properly bias the received line signal for the L IN input. A 2:1 coupling transformer is used to couple to the line with a secondary center tap for optional phantom power feed. Varistors have been shown for surge protection against such things as lightning strikes. If the scramblers power up with all zeros in them, they are not capable of randomizing all-zeros data sequence. This increases the correlation between the transmit and receive data which may cause loss of convergence in the echo canceller and high bit error rates. In DN mode the insertion of the SYNC pattern will provide enough pseudo-random activity to maintain convergence. In MOD mode the SYNC pattern is not inserted. For this reason, at least on ”1” must be fed into the DNIC on power up to ensure that the scramblers will randomize any subsequent all-zeros sequence. Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s DV Port ST-BUS CD Port ST-BUS Master Clocks Mode Select Lines +5V 0.33µF 0.33µF DSTi DSTo CDSTi CDSTo MS0 MS1 MS2 VRef VBias LOUT LIN OSC1 OSC2 F0o NC D.C. coupled, Frequency locked 10.24 MHz clock. R2 = 390Ω R1 = 47Ω C2’ = 1.5 nF C2 = 22 nF +5V D1 = D2 = MUR405 2 : 1 1.0µF Line Feed Voltage For 80 kbit/s: C2’ = 3.3 nF C1 = 0.33 µF

68 Volts

(Typ)

2.5 Joules

0.02 Watt

Note: Low leakage diodes (1 & 2) are required so that the DC voltage at L IN ≈ VBias To Next DNIC MT9173/74 Characteristics DN Mode. Clock Timing Refer to AC Electrical RxSBTo Time Measurement Circuitry DV Port ST-BUS CD Port ST-BUS Master Clocks Mode Select Lines +5V 0.33µF 0.33µF DSTi DSTo CDSTi CDSTo MS0 MS1 MS2 VRef VBias LOUT LIN OSC1 OSC2 R2 = 390Ω R1 = 47Ω C2’ = 1.5 nF C2 = 22 nF +5V D1 = D2 = MUR405 2:1 1.0µF For 80 kbit/s: C2’ = 3.3 nF C1 = 0.33 µF (Typ) Note: Low leakage diodes (1 & 2) are required so that the DC voltage at LIN ≈ VBias

10.24 MHz XTAL

C3=33pF=C4 Supply MT9173/74 RxSBTo hardware SYNC Indicator (optional)

MT9173/74 Preliminary Information 9-152 ** Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. † Parameters over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. † Parameters over recommended temperature & power supply voltage ranges. Absolute Maximum Ratings** - Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Symbol Min Max Units 1 Supply Voltage V DD -0.3 7 V 2 Voltage on any pin (other than supply) V Max -0.3 V DD +0.3 V

3 Current on any pin (other than supply) I Max 40 mA

4 Storage Temperature T ST -65 +150 °C

5 Package Power Dissipation (Derate 16mW/°C above 75°C) PDiss 750 mW

Recommended Operating Conditions† - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ* Max Units Test Conditions 1 Operating Supply Voltage V DD 4.75 5.00 5.25 V

2 Operating Temperature T OP -40 +85 °C

3 Input High Voltage (except OSC1) VIH 2.4 V DD V for 400 mV noise margin 4 Input Low Voltage (except OSC1) V IL 0 0.4 V for 400 mV noise margin Characteristics Sym Min Typ* Max Units Test Conditions O U T P U T S Operating Supply Current I DD 10 mA 2 Output High Voltage (ex OSC2) V OH 2.4 V I OH =10mA

3 Output High Current

(except OSC2) IOH 10 mA Source current. V OH =2.4V 4 Output High Current - OSC2 I OH 10 µA Source current VOH =3.5V 5 Output Low Voltage (ex OSC2) V OL 0.4 V I OL =5mA

6 Output Low Current

(except OSC2) IOL 5 7.5 mA Sink current. V OL =0.4V 7 Output Low Current - OSC2 I OL 10 µA Sink current. VOL =1.5V 8 High Imped. Output Leakage I OZ 10 µAV IN=VSS to VDD

9 Output Voltage (V Ref)

(VBias) VO VBias-1.8 VDD /2 V V10 I N P U T S Input High Voltage (ex OSC1) VIH 2.0 V 12 Input Low Voltage (ex OSC1) V IL 0.8 V 13 Input High Voltage (OSC1) V IHo 4.0 V 14 Input Low Voltage (OSC1) V ILo 1.0 V

15 Input Leakage Current I IL 10 µAV IN=VSS to VDD

16 Input Pulldown Impedance

ZPD 50 k Ω

17 Input Leakage Current for

IIOSC 20 µA

Preliminary Information MT9173/74 9-153 † Timing is over recommended temperature & power supply voltages. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ➀ Duty cycle is measured at VDD /2 volts. † Timing is over recommended temperature & power supply voltages. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Notes: 1) When operating as a SLAVE the C4 clock has a 40% duty cycle. 2) When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e., FC =2.5xfC4 ). The relative phase between these two clocks (Φ in Fig. 17) is not critical and may vary from 0 ns to tC4P . However, the relative jitter must be less than JC (see Figure 17). Figure 15 -C4 Clock & Frame Pulse Alignment for ST-BUS Streams Characteristics Sym Min Typ* Max Units Test Conditions I N P U T S Input Voltage (L IN) VIN 5.0 V pp

2 Input Impedance (L IN)Z IN 20 k Ω fBaud=160 kHz

3 Crystal/Clock Frequency f C 10.24 MHz

4 Crystal/Clock Tolerance T C -100 0 +100 ppm

5a Crystal/Clock Duty Cycle ➀ DC C 40 50 60 % Normal temp. & V DD 5b Crystal/Clock Duty Cycle ➀ DC C 45 50 55 % Recommended at max./ min. temp. & VDD 6 Crystal/Clock Loading C L 33 50 pF From OSC1 & OSC2 to V SS . 7 O U T P U T S Output Capacitance (LOUT )C o 8p F

8 Load Resistance (L OUT )

(VBias, VRef) R Lout 500 100 Ω kΩ

9 Load Capacitance (L OUT )

(VBias, VRef) C Lout 0.1 20 pF µF Capacitance to VBias. 10 Output Voltage (L OUT )V o 3.2 4.3 4.6 V pp R Lout = 500Ω , CLout= 20pF Characteristics Sym Min Typ* Max Units Test Conditions

1 C4 Clock Period t C4P 244 ns

2 C4 Clock Width High or Low t C4W 122 ns In Master Mode - Note 1

3 Frame Pulse Setup Time t F0S 50 ns

4 Frame Pulse Hold Time t F0H 50 ns

5 Frame Pulse Width t F0W 244 ns

6 10.24 MHz Clock Jitter (wrtC4) J C ±15 ns Note 2 Channel 31 Bit 0 Channel 0 Bit 7 Channel 0 Bit 6 ST-BUS BIT CELLS

MT9173/74 Preliminary Information 9-154 Figure 16 -C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode Figure 17 - Frequency Locking for theC4 and OSC1 Clocks in MAS/DN Mode † Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Figure 18 -RCK, TCK & CLD Timing For MOD Mode Characteristics Sym 80 kbit/s 160 kbit/s Units Test ConditionsMin Typ* Max Min Typ* Max 1 TCK/RCK Clock Period t CP 12.5 6.25 µs 2 TCK/RCK Clock Width tCW 6.25 3.125 µs

3 TCK/RCK Clock Transition TimetCT 20 20 ns C L=40pF

4 CLD toTCK Setup Time tCLDS 3.125 1.56 µs 5 CLD toTCK Hold Time tCLDH 3.125 1.56 µs 6 CLD Width Low tCLDW 6.05 2.925 µs

7 CLD Period tCLDP 8xtCP 8xtCP µs

2.0V 0.8V 2.0V 0.8V tC4P tC4WtF0S tF0H tF0W tC4W OSC1 2.0V 0.8V 3.0V 2.0V JC Φ RCK TCK CLD tCT tCP tCLDS tCLDH tCW tCT tCLDW tCW 2.4V 0.4V 2.4V 0.4V 2.4V 0.4V tCP Note 1: TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the DV port.RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the Do output and may be skewed with respect toTCK due to end-to-end delay. Note 2: At the slave endTCK is phase locked toRCK. The rising edge ofTCK will lead the rising edge ofRCK by approximately 90o.

Preliminary Information MT9173/74 9-155 † Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Figure 19 - Data Timing For DN Mode † Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25 °C, for design aid only: not guaranteed and not subject to production testing. Note 1: Attenuation measured from Master LOUT to Slave LIN at 3/4baud frequency. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ* Max Units Test Conditions

1 DSTi/CDSTi Data Setup Time t RS 30 -10 ns

2 DSTi/CDSTi Data Hold Time t RH 50 10 ns

3a DSTo/CDSTo Data Delay t TD 60 120 ns C L=40pF 3b DSTo/CDSTo High Z to Data Delay tZTD 60 140 ns C L=40pF Characteristics Sym 80 kbit/s 160 kbit/s Units Test ConditionsMin Typ* Max Min Typ* Max

1 Di/CDi Data Setup Time t DS 150 150 ns

2 Di/CDi Data Hold Time t DH 4.5 2.5 µs

3 Do Data Delay Time t RD 70 70 ns C L=40pF

4 CDo Data Delay Time t TD 70 70 ns C L=40pF

Performance Characteristics of the MT9173 DSIC Characteristics Sym Min Typ* Max Units Test Conditions

1 Allowable Attenuation for Bit Error

Rate of 10-6 (Note 1) Afb 0 30 25 dB SNR ≥16.5dB (300kHz bandlimited noise)

2 Line Length at 80 kbit/s -24 AWG

-26 AWG L80 3.0 2.2 km attenuation - 6.9 dB/km attenuation - 10.0 dB/km

3 Line Length at 160 kbit/s -24 AWG

-26 AWG L160 3.0 2.2 km attenuation - 8.0 dB/km attenuation - 11.5 dB/km Performance Characteristics of the MT9174 DNIC Characteristics Sym Min Typ* Max Units Test Conditions Rate of 10-6 (Note 1) Afb 0 40 33 dB SNR ≥16.5dB (300kHz bandlimited noise) -26 AWG L80 5.0 3.4 km attenuation - 6.9 dB/km attenuation - 10.0 dB/km -26 AWG L160 4.0 3.0 km attenuation - 8.0 dB/km attenuation - 11.5 dB/km 2.0V 0.8V 2.4V 0.4V 2.0V 0.8V Bit Stream DSTi CDSTi DSTo CDSTo Bit Cell tTD tRS tRH tTDtZTD

MT9173/74 Preliminary Information 9-156 Figure 20 - Data Timing for Master Modem Mode Tx Bit Stream TCK Di CDI CDo Rx Bit Stream Do 2.4V 0.4V 2.0V 0.8V 2.4V 0.4V 2.4V 0.4V Bit Cell tDS tDH tTDtTD tRD tRD Bit Cell RCK

MT9173/74 Preliminary Information 9-158 Notes: