MT9171_06 ZARLINK | Alldatasheet

Document overview

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Technical content

Features

  • Full duplex transmission over a single twisted pair
  • Selectable 80 or 160 kbit/s line rate
  • Adaptive echo cancellation
  • Up to 3 km (9171) and 4 km (9172)
  • ISDN compatible (2B+D) data format
  • Transparent modem capability
  • Frame synchronization and clock extraction
  • Zarlink ST-BUS compatible
  • Low power (typically 50 mW), single 5 V supply

Applications

  • Digital subscriber lines
  • High speed data transmission over twisted wires
  • Digital PABX line cards and telephone sets
  • 80 or 160 kbit/s single chip modem

Description

The MT9171 (DSIC) and MT9172 (DNIC) are pin for pin compatible replacements for the MT8971 and MT8972, respectively. They are multi-function devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair. They use adaptive echo-cancelling techniques and transfer data in (2B+D) fo rmat compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modem March 2006

Ordering Information

MT9171/72AE 22 Pin PDIP Tubes MT9171/72AN 24 Pin SSOP Tubes MT9171/72AP 28 Pin PLCC T ubes MT9171/72APR 28 Pin PLCC Tape & Reel MT9171/72ANR 24 Pin SSOP Tape & Reel MT9171/72AE1 22 Pin PDIP* Tubes MT9171/72AP1 28 Pin PLCC* Tubes MT9171/72AN1 24 Pin SSOP* Tubes MT9171/72APR1 28 Pin PLCC* Tape & Reel MT9171/72ANR1 24 Pin SSOP* Tape & Reel *Pb Free Matte Tin -40°C to +85 °C ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Data Sheet Figure 1 - Functional Block Diagram DSTi/Di CDSTi/ F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 RegC DSTo/Do CDSTo/ CDo Transmit Interface Prescrambler Scrambler Control Register Transmit/ Clock Receive Timing & Control Status Transmit Timing Master Clock Phase Locked Sync Detect Receive DPLL Receive Interface De- Prescrambler Descrambler Differentially Encoded Biphase Receiver Differentially Encoded Biphase Transmitter Transmit Filter & Line Driver Receive Filter MUX Address Echo Canceller Error Signal Echo Estimate V Bias VDD VSS VBias VRef LOUT LOUT DIS Precan LIN OSC2 OSC1 CDi

Zarlink Semiconductor Inc. with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted. The MT9171/72 is fabricated in Zarlink’s ISO2-CMOS process. Figure 2 - Pin Connections Pin Description Pin # Name Description 22 24 28 11 2 L OUT Line Out. Transmit Signal output (Analog). Referenced to VBias. 22 3 V Bias Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to VDD. 33 4 V Ref Internal Reference Voltage output. Connect via 0.33 µF decoupling capacitor to VDD. 4,5, 4,5, 5,7, MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the various operating modes for a particular application. See Table 1 for the operating modes. 77 9 R e g C Regulator Control output (Digital). A 512 kHz clock used for switch mode power supplies. Unused in MAS/MOD mode and should be left open circuit. 89 1 0 F 0 /CLD Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative pulse input for the MASTER indicating the start of the active channel times of the device. Output for the SLAVE indicating the start of the active channel times of the device. Output in MOD mode providing a pulse indicating the start of the C- channel. 11 12

22 PIN PDIP

/CLD CDSTi/CDi CDSTo/CDo VSS VDD LIN TEST LOUT DIS Precan OSC1 OSC2 /TCK F0o/RCK DSTi/Di DSTo/Do

28 PIN PLCC

/TCK MS2 NC MS1 MS0 RegC F0/CLD NC CDSTi/CDi CDSTo/CDo VSS DSTo/Do NC F0o/RCK DSTi/Di 12 13

24 PIN SSOP

/CLD CDSTi/CDi CDSTo/CDo VSS NC VDD LIN TEST LOUT DIS Precan OSC1 OSC2 /TCK F0o/RCK DSTi/Di DSTo/Do NC

Zarlink Semiconductor Inc. 91 0 1 2 C D S T i / CDi Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control & signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 10 11 13 CDSTo/ CDo Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial control & signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 11 12 14 V SS Negative Power Supply (0 V). 12 13 15 DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 13 14 16 DSTi/Di Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 14 15 17 F0o /RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns wide negative pulse indicating the end of the active channel times of the device to allow daisy chaining. In MOD mode provides the receive bit rate clock to the system. 15 16 19 C4 /TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin provides the transmit bit rate clock to the system. 16 17 21 OSC2 Oscillator Output. CMOS Output. 18 20 23 Precan Precanceller Disable. When held to Logic ’1 ’, the internal path from LOUT to the precanceller is forced to VBias thus bypassing the precanceller section. When logic ’0’, the LOUT to the precanceller path is enabled and functions normally. An internal pulldown (50 kΩ) is provided on this pin. 1,6, 11, 18, 20, NC No Connection. Leave open circuit 19 21 24 L OUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When logic “0”, LOUT functions normally. An internal pulldown (50 kΩ) is provided on this pin. 20 22 26 TEST Test Pin. Connect to VSS. 21 23 27 L IN Receive Signal input (Analog). 22 24 28 V DD Positive Power Supply (+5 V) input. Pin Description (continued) Pin # Name Description 22 24 28

Zarlink Semiconductor Inc. Functional Description The MT9171/72 is a device which may be used in prac tically any application t hat requires high speed data transmission over two wires, including smart telephon e sets, workstations, data terminals and computers. The device supports the 2B+D channel format (two 64 kbit/s B-channels and one 16 kbit/s D-channel) over two wires as recommended by the CCITT. The line data is converted to and from the ST-BUS format on the system side of the network to allow for easy interfacing with other components such as the S-interface device in an NT1 arrangement, or to digital PABX components. Smart telephone sets with data and voice capability can be easily implemented using the MT9171/72 as a line interface. The device’s high bandwidth and long loop length capability allows its use in a wide variety of sets. This can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in both the home and central office or remote concentra tion equipment. Within the subscriber equipment the MT9171/72 would terminate the line and encode/ decode the data and voice for transmission while additional electronics could provide interfaces for a standard telephone set and any number of data ports supporting standard data rates for such things as computer communications and telemetry for remote meter reading. Digital workstations with a high degree of networking capability can be designed us ing the DNIC for the line interface, offering up to 160 kbit/s data transmission over exis ting telephone lines. The MT9 171/72 could also be valuable within existing computer networks for connecting a large number of terminals to a computer or for intercomputer links. With the DNIC, this can be accomplished at up to 16 0 kbit/s at a very low cost per line for terminal to computer links and in many cases this bandwidth would be sufficient for computer to computer links. Figure 1 shows the block diagram of the MT9171/72. T he DNIC provides a bidirecti onal interface between the DV (data/voice) port and a full duplex line operating at 80 or 160 kbit/s over a single pair of twisted wires. The DNIC has three serial ports. The DV port (DSTi/Di, DSTo/Do), the CD (control/data) port (CDSTi/CDi, CDSTo/CDo) and a line port (L IN, LOUT). The data on the line is made up of information from the DV and CD ports. The DNIC must combine information received from both the DV and CD ports and put it onto the line. At the same time, the data received from the line must be split into the various channels and directed to the proper ports. The usable data rates are 72 and 144 kbit/s as required for the basic rate interface in ISDN. Full duplex transmission is made possible through on board adaptive echo cancellation. The DNIC has various modes of operation which are selected through the mode select pins MS0-2. The two major modes of operation are the MODEM (MOD) and DIGITAL NETWORK (DN) modes. MOD mode is a transparent 80 or 160 kbit/s modem. In DN mode the line carries the B and D channels formatted for the ISDN at either 80 or 160 kbit/s. In the DN mode the DV and CD ports are standard ST-BUS and in MOD mode they are transparent serial data streams at 80 or 160 kbit/s. Other modes include: MASTER (MAS) or SLAVE (SLV) mode, where the timebase and frame synchronization are provided externally or ar e extracted from the line and DUAL or SINGLE (SINGL) port modes, where both the DV and CD ports are active or where the CD port is inactive and all information is passed through the DV port. For a detailed description of the modes see “Operating Modes” section. In DIGITAL NETWORK (DN) mode there are three channels transferred by the DV and CD ports. They are the B, C and D channels. The B1 and B2 channels each have a bandwidth of 64 kbit/s and are used for carrying PCM encoded voice or data. These channels are always transmit ted and received through the DV port (Figures 3, 4, 5, 6). The C-channel, having a bandwidth of 64 kbit/s, provides a means for the system to control the DNIC and for the DNIC to pass status information back to the system. The C-channel has a Housekeeping (HK) bit which is the only bit of the C-channel transmitted and received on the li ne. The 2B+D channel bits and the HK bit are double- buffered. The D-channel can be transmi tted or received on the line with eit her an 8, 16 or 64 kbit/s bandwidth depending on the DNIC’s mode of operation. Both the HK bit and the D-channel can be used for end-to-end signalling or low speed data transfer. In DUAL port mode the C and D channels are accessed via the CD port (Figure 7) while in SINGL port mode t hey are transferred through the DV port (F igures 5, 6) along with the B1 and B2 channels.

Zarlink Semiconductor Inc. extracted and the Receive Interface separates the channels and outputs them to the proper ports in the proper channel times. The destination of the various channels is the same as that received on the input DV and CD ports. The Transmit/Receive Timing and Control block generates all the clocks for the transmit and receive functions and controls the entire chip according to the control register. In order that more than one DNIC may be connected to the same DV and CD ports an F0o signal is generated which signals the next device in a daisy chain that its channel times are now active. In this arrangement only the first DNIC in the chain receives the system F0 with the following devices receiving its predecessor’s F0o. In MOD mode, all the ports have a different format. The line port again operates at 80 or 160 kbit/s, however, there is no synchronization overhead, only tr ansparent data. The DV and CD ports carry serial data at 80 or 160 kbit/s with the DV port transferring all the data for the line and the CD port carrying the C-channel only. In this mode the transfer of data at both ports is synchronized to the TCK and RCK clocks for transmit and receive data, respectively. The CLD signal goes low to indicate the start of the C-channel data on the CD port. It is used to load and latch the input and output C-channel but has no relationship to the data on the DV port. Operating Modes (MS0-2) The logic levels present on the mode select pins MS0, MS1 and MS2 program the DNIC for different operating modes and configure the DV and CD ports accordingly. Table 1 shows the modes corresponding to the state of MS0-2. These pins select the DNIC to operate as a MAST ER or SLAVE, in DUAL or SINGLE port operation, in MODEM or DIGITAL NETWORK mode and the order of the C and D channels on the CD port. Table 2 provides a description of each mode and Table 3 gives a pin configuration according to the mode selected for all pins that have variable functions. These functions vary depending on whether it is in MAS or SLV, and whether DN or MOD mode is used. Table 1 - Mode Select Pins E=Enabled X=Not Applicable Blanks are disabled Mode Select Pins Mode Operating Mode MS2 MS1 MS0 SLV MAS DUAL SINGL MO D DN D-C C-D ODE 00 0 0 E E E E E 00 1 1 E E E XX E 01 0 2 E E E E E 01 1 3 E E E E E 10 0 4 E E E E E 10 1 5 E E E XX E 11 0 6 E E E E E 11 1 7 E E E E

Zarlink Semiconductor Inc. Table 2 - Mode Definitions Table 3 - Pin Configurations The overall mode of operation of the DNIC can be programmed to be either a baseband modem (MOD mode) or a digital network transceiver (DN mode). As a baseband modem, transmit/receive data is passed transparently through the device at 80 or 160 kbit/s by the DV port. The CD port transfers the C-channel and D-Channel also at 80 or 160 kbit/s. In DN mode, both the DV and CD ports operate as ST-BUS streams at 2.048 Mbit/s. T he DV port transfers data over pins DSTi and DSTo while on the CD port, the CDSTi and CDSTo pins are used. The SINGL port option only exists in DN mode. Mode Function SLV SLAVE - The chip timebase is extracted from the received line data and the external 10.24 MHz crystal is phase locked to it to provide clocks for the entire device and are output for the external system to synchronize to. MAS MASTER - The timebase is derived from the externally supplied data clocks and 10.24 MHz clock which must be frequency locked. The transmit data is synchronized to the system timing with the receive data recovered by a clock extracted from the receive data and resynchronized to the system timing. DUAL DUAL PORT - Both the CD and DV ports are active with the CD port transferring the C&D channels and the DV port transferring the B1& B2 channels. SINGL SINGLE PORT - The B1& B2, C and D channels are all transferred through the DV port. The CD port is disabled and CDSTi should be pulled high. MOD MODEM - Baseband operation at 80 or 160 kbits/s. The line data is received and transmitted through the DV port at the baud rate selected. The C-channel is transferred through the CD port also at the baud rate and is synchronized to the CLD output. DN DIGITAL NETWORK - Intended for use in the digital network with the DV and CD ports operating at

2.048 Mbits/s and the line at 80 or 160 kbits/s configured according to the applicable ISDN

recommendation. D-C D BEFORE C-CHANNEL - The D-channel is transferred before the C-channel following F0. C-D C BEFORE D-CHANNEL - The C-channel is transferred before the D-channel following F0. ODE OUTPUT DATA ENABLE - When mode 7 is selected, the DV and CD ports are put in high impedance state. This is intended for power-up reset to avoid bus contention and possible damage to the device during the initial random state in a daisy chain configuration of DNICs. In all the other modes of operation DV and CD ports are enabled during the appropriate channel times. Mode /CLD F0o/RCK C4/TCK Name Input/Output Name Input/Output Name Input/Output 0F 0 Input F0o Output C4 Input 1C L D Output RCK Output TCK Output 2F 0 Input F0o Output C4 Input 3F 0 Input F0o Output C4 Input 4F 0 Output F0o Output C4 Output 5C L D Output RCK Output TCK Output 6F 0 Output F0o Output C4 Output 7F 0 Input F0o Output C4 Input

Zarlink Semiconductor Inc. CD Port (CDSTi/CDi, CDSTo/CDo) The CD port is a serial bidirectional port used only in DUAL port mode. It is a means by which the DNIC receives its control information for things such as setting the bi t rate, enabling internal loopback tests, sending status information back to the system and transferring low speed signalling data to and from the line. The CD port is composed of the C and D-Channels. The C-channel is used for transferring control and status information between the DNI C and the system. The D- channel is used for sendi ng and receiving signalling information and lower speed data between the line and the system. In DN/DUAL mode the DNIC receives a C- channel on CDSTi while transmitting a C-channel on CDSTo. Fifteen channel times later (halfway through the frame) a D-channel is received on CDSTi while a D-channel is transmitted on CDSTo. This is shown in Figure 7. The order of the C and D bytes in DUAL port mode can be reversed by the mode select pins. See Table 1 for a listing of the byte orientations. The D-channel exists only in DN mode and may be used for transferring low speed dat a or signalling information over the line at 8, 16 or 64 kbit/s (by using the DINB feature). The inform ation passes transparently through the DNIC and is transmitted to or received from the line at the bit rate selected in the Control Register. If the bit rate is 80 kbit/s, only D0 is transmitted and received. At 160 kbit/s, D0 and D1 are transmitted and received. When the DINB bit is set in the Control Regist er the entire D-channel is transmitted and received in the B1-channel timeslot. The C-channel is used for transferring control and st atus information between the DNIC and the system. The Control and Diagnostics Registers are accessed through the C-channel. They contain information to control the DNIC and carry out the diagnostics as well as the HK bit to be transmitted on the line as described in Tables 4 and 5. Bits 0 and 1 of the C-channel select between the Control and Diagnostics Register. If these bits are 0, 0 then the C-channel information is written to the Control Register (Table 4) . If they are 0, 1 the C- channel is written to the Diagnostics Register (Table 5). Bit Name Description 0 Reg Sel-1 Register Select-1. Must be set to ’0’ to select the Control Register. 1 Reg Sel-2 Register Select-2. Must be set to ’0’ to select the Control Register. 2 DRR Diagnostics Register Reset. Writing a "0" to this bit will cause a diagnostics register reset to occur coincident with the next frame pulse as in the MT8972A. When this bit is a logic "1", the Diagnostics Register will not be reset. 3 BRS Bit Rate Select. When set to ’0’ selects 80 kbit/s. When set to ’1’, selects 160 kbit/s. 4D I N B 2 D-Channel in B Timeslot. When ’0’, the D-channel bits (D0 or D0 and D1) corresponding to the selected bit rate (80 or 160 kbit/s) are transmitted during the normal D-channel bit times. When set to ’1’, the entire D-channel (D0-D7) is transmitted during the B1-channel timeslot on the line providing a 64 kbit/s D-channel link.

5 PSEN

2 Prescrambler/Deprescrambler Enable. When set to ’1’, the data prescrambler and deprescrambler are enabled. When set to ’0’, the data prescrambler and deprescrambler are disabled. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Reg Sel-1 Reg Sel-2 DRR BRS DINB PSEN ATTACK TxHK Default Mode Selection (Refer to Table 4a)

Zarlink Semiconductor Inc. Table 4 - Control Register Notes: 1. Suggested use of ATTACK: -At 160 kbit/s full convergence requires 850 ms with ATTACK held high for the first 240 frames or 30 ms. -At 80 kbit/s full convergence requires 1.75 s with ATTACK held high for the first 480 frames or 60 ms. 2. When bits 4-7 of the Control Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4 a, depending upon the status of bit-3. Table 4a - Default Mode Selection Notes: . Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode. 4. Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode. 6A T T A C K 2 Convergence Speedup. When set to ’1’, the echo canceller will converge to the reflection coefficient much faster. Used on power-up for fast convergence.1 When ’0’, the echo canceller will require the normal amount of time to converge to a reflection coefficient. 7T x H K 2 Transmit Housekeeping. When set to ’0’, logic zero is transmitted over the line as Housekeeping Bit. When set to ’1’, logic one is transmitted over the line as Housekeeping Bit. C-Channel (Bit 0-7) Internal Control Register Internal Diagnostic Register Description XXX01111 00000000 01000000 Default Mode-1 3: Bit rate is 80 kbit/s. ATTACK, PSEN, DINB, DRR and all diagnostics are disabled. TxHK=0. XXX11111 00010000 01000000 Default Mode-2 4 Bit rate is 160 kbit/s. ATTACK, PSEN, DINB, DRR and all diagnostics are disabled. TxHK=0. Bit Name Description 0 Reg Sel-1 Register Select-1. Must be set to ’0’ to select the Diagnostic Register. 1 Reg Sel-2 Register Select-2. Must be set to ’1’ to select the Diagnostic Register. 2,3 Loopback Bit 2 Bit 3 0 0 All loopback testing function s disabled. Normal operation. 0 1 DSTi internally looped back into DSTo for system diagnostics. 10L OUT is internally looped back into LIN for system diagnostics.2 1 1 DSTo is internally looped back into DSTi for end-to-end testing. 3 Bit Name Description bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Reg Sel-1 Reg Sel-2 DRR BRS DINB PSEN ATTACK TxHK Default Mode Selection (Refer to Table 4a) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Reg Sel-1 Reg Sel-2 Loopback FUN PSWAP DLO Not Used Default Mode Selection (Refer to Table 4a)

Zarlink Semiconductor Inc. Table 5 - Diagnostic Register Notes: 1. When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Tabl e 4a, depending upon the status of bit-3. 2. Do not use L OUT to L IN loopback in DN/SLV mode. 3. Do not use DSTo to DSTi loopback in MOD/MAS mode. The Diagnostics Register Reset bit (bit 2) of the Contro l Register determines the re set state of the Diagnostics Register. If, on writing to the Control R egister, this bit is set to logic “0”, the Diagnostics Register will be reset coincident with the frame pulse. When this bit is logic “1”, the Diagnostics Register will not be reset. In order to use the diagnostic features, the Diagnostics Register must be continuously written to. The output C-channel sends status information from the Status Register to the system along with the received HK bit as shown in Table 6. Table 6 - Status Register 4F U N 1 Force Unsync. When set to ’1’, the DNIC is forced out-of-sync to test the SYNC recovery circuitry. When set to ’0’, the operation continues in synchronization. 5 PSWAP 1 Polynomial Swap. When set to ’1’, the scrambling and descrambling polynomials are interchanged (use for MAS mode only). When set to ’0’, the polynomials retain their normal designations. 6D L O 1 Disable Line Out. When set to ’1’, the signal on LOUT is set to VBias. When set to ’0’, LOUT pin functions normally. 7 Not Used Must be set to ’0’ for normal operation. Status Register Name Function

0 SYNC Synchronization - When set this bit indicates that synchronization to the received

line data sync pattern has been acquired. For DN mode only. 1-2 CHQual Channel Quality - These bits provide an estimate of the receiver’s margin against noise. The farther this 2 bit value is from 0 the better the SNR. 3 Rx HK Housekeeping - This bit is the received housekeeping (HK) bit from the far end. 4-6 Future Future Functionality. These bits return Logic 1 when read. 7 ID This bit provides a hardware identifier for the DNIC revision. The MT9171/72 will return a logic “0” for this bit. (Logic “1” returned for MT8972A.) Bit Name Description bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Reg Sel-1 Reg Sel-2 Loopback FUN PSWAP DLO Not Used Default Mode Selection (Refer to Table 4a) 01234567 SYNC CHQual Rx HK Future Functionality ID

and CLD the channel boundaries of the data stream as shown in Figure 8. Figure 10. The scrambled NRZ data is differentially encoded meaning the prev ious differential encoded output is transition indicating a logic "1". superimposed on the signal from the remote end and any reflections or delayed symbols of the near end signal. 160 kbit/s a SYNC bit, the HK bit, two bits of the D-channel and both B1 and B2 channels are transmitted. at 80 or 160 kbit/s is present. No frame recovery information is present on the line in MOD mode.

Zarlink Semiconductor Inc. Figure 12 - Frame Format - 160 kbit/s (Modes 0, 2, 3, 4, 6) Typical connection diagrams are show n in Figures 13 and 14 for the DN mode as a MASTER and SLAVE, respectively. LOUT is connected to the coupling transformer thr ough a resistor R2 and capacitors C2 and C2’ to match the line characteristic impedance. Suggested values of R2, C2 and C2’ for 80 and 160 kbit/s operation are provided in Figures 13 and 14. Overvoltage protection is provided by R1, D1 and D2. C1 is present to properly bias the received line signal for the L IN input. A 2:1 coupling transformer is used to couple to the line with a secondary center tap for optional phantom power feed. Varistors have been shown for surge protection against such things as lightning strikes. If the scramblers power up with all zeros in them, they are not capable of randomizing all-zeros data sequence. This increases the correlation between the transmit and receive data which may cause loss of convergence in the echo canceller and high bit error rates. In DN mode the insertion of the SYNC pattern will provide enough pseudo-random activity to maintain convergence. In MOD mode the SYNC pattern is not inserted. For this reason, at least on ”1” must be fed into the DNIC on power up to ensure that the scramblers will randomize any subsequent all-zeros sequence. Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s LOUT SYNC HK0 D 1 D0 B10 B11 B12 B13 B14 B15 B16 B17 B20 B21 B22 B23 B24 B25 B26 B27 SYNC DV Port ST-BUS CD Port ST-BUS Master Clocks Mode Select Lines +5 V 0.33 µF 0.33 µF DSTi DSTo CDSTi CDSTo MS0 MS1 MS2 V Ref VBias LOUT LIN OSC1 OSC2 F0o NC D.C. coupled, Frequency locked 10.24 MHz clock. R2 = 390Ω R1 = 47Ω C2’ = 1.5 nF C2 = 22 nF +5V D1 = D2 = MUR405 2 : 1 1.0 µF Line Feed Voltage For 80 kbit/s: C2’ = 3.3 nF C1 = 0.33 µF

68 Volts

(Typ)

2.5 Joules

0.02 Watt

Note: Low leakage diodes (1 & 2) are required so that the DC voltage at L IN ≈ VBias To Next DNIC MT9171/72 Characteristics DN Mode. Clock Timing Refer to AC Electrical

Zarlink Semiconductor Inc. Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s DV Port ST-BUS CD Port ST-BUS Master Clocks Mode Select Lines +5 V 0.33 µF 0.33 µF DSTi DSTo CDSTi CDSTo MS0 MS1 MS2 V Ref VBias LOUT LIN OSC1 OSC2 R2 = 390 Ω R1 = 47 Ω C2’ = 1.5 nF C2 = 22 nF +5V D1 = D2 = MUR405 2:1 1.0 µF For 80 kbit/s: C2’ = 3.3 nF C1 = 0.33 µF (Typ) Note: Low leakage diodes (1 & 2) are required so that the DC voltage at LIN ≈ VBias

10.24 MHz XTAL

C3=33pF=C4 Supply MT9171/72

Zarlink Semiconductor Inc. ** Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. † Parameters over recommended temper ature & power supply voltage ranges. Absolute Maximum Ratings** - Voltages are with respect to ground (V SS) unless otherwise stated. Parameter Symbol Min. Max. Units 1 Supply Voltage V DD -0.3 7 V 2 Voltage on any pin (other than supply) V Max -0.3 V DD+0.3 V

3 Current on any pin (other than supply) I Max 40 mA

4 Storage Temperature T ST -65 +150 °C

5 Package Power Dissipation (Derate 16mW/°C above 75°C) PDiss 750 mW

Recommended Operating Conditions† - Voltages are with respect to ground (V SS) unless otherwise stated. Characteristics Sym. Min. Typ.* Max. Units Test Conditions 1 Operating Supply Voltage V DD 4.75 5.00 5.25 V

2 Operating Temperature T OP -40 +85 °C

3 Input High Voltage (except OSC1) V IH 2.4 V DD V for 400 mV noise margin 4 Input Low Voltage (except OSC1) V IL 0 0.4 V for 400 mV noise margin Characteristics Sym. Min. Typ. * Max. Units Test Conditions O U T P U T S Operating Supply Current I DD 10 mA 2 Output High Voltage (ex OSC2) V OH 2.4 V I OH=10mA

3 Output High Current

(except OSC2) IOH 10 mA Source current. V OH=2.4V 4 Output High Current - OSC2 I OH 10 µA Source current V OH=3.5V 5 Output Low Voltage (ex OSC2) V OL 0.4 V I OL=5mA

6 Output Low Current

(except OSC2) IOL 5 7.5 mA Sink current. V OL=0.4V 7 Output Low Current - OSC2 I OL 10 µA Sink current. V OL=1.5V 8 High Imped. Output Leakage I OZ 10 µAV IN=VSS to VDD

9 Output Voltage (V Ref)

(VBias) VO VBias-1.8 VDD/2 V V

Zarlink Semiconductor Inc. * Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. † Parameters over recommended temperature & power supply voltage ranges. † Timing is over recommended temperature & power supply voltages. * Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. 1. Duty cycle is measured at V DD/2 volts. I N P U T S Input High Voltage (ex OSC1) V IH 2.0 V 12 Input Low Voltage (ex OSC1) V IL 0.8 V 13 Input High Voltage (OSC1) V IHo 4.0 V 14 Input Low Voltage (OSC1) V ILo 1.0 V

15 Input Leakage Current I IL 10 µAV IN=VSS to VDD

16 Input Pulldown Impedance

ZPD 50 k Ω

17 Input Leakage Current for

IIOSC 20 µA Characteristics Sym. Min. Typ. * Max. Units Test Conditions I N P U T S Input Voltage (L IN) VIN 5.0 V pp

2 Input Impedance (L IN)Z IN 20 k Ω fBaud=160 kHz

3 Crystal/Clock Frequency f C 10.24 MHz

4 Crystal/Clock Tolerance T C -100 0 +100 ppm

5a Crystal/Clock Duty Cycle 1 DCC 40 50 60 % Normal temp. & V DD 5b Crystal/Clock Duty Cycle 1 DCC 45 50 55 % Recommended at max./ min. temp. & VDD 6 Crystal/Clock Loading C L 33 50 pF From OSC1 & OSC2 to V SS. 7 O U T P U T S Output Capacitance (L OUT)C o 8p F

8 Load Resistance (L OUT)

(VBias, VRef) RLout 500 100 Ω kΩ

9 Load Capacitance (L OUT)

(VBias, VRef) CLout 0.1 20 pF µF Capacitance to VBias. 10 Output Voltage (L OUT)V o 3.2 4.3 4.6 V pp RLout = 500Ω, CLout = 20pF Characteristics Sym. Min. Typ. * Max. Units Test Conditions

Zarlink Semiconductor Inc. † Timing is over recommended temperature & power supply voltages. * Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Notes: 1) When operating as a SLAVE the C4 clock has a 40% duty cycle. 2) When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e., FC=2.5xf C4). The relative phase between these two clocks ( Φ in Fig. 17) is not critical and may vary from 0 ns to t C4P. However, the relative jitter must be less than J C (see Figure 17). Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode Characteristics Sym. Min. Typ.* Max. Units Test Conditions 1C 4 Clock Period t C4P 244 ns 2C 4 Clock Width High or Low t C4W 122 ns In Master Mode - Note 1

3 Frame Pulse Setup Time t F0S 50 ns

4F r a m e P u l s e H o l d T i m e t F0H 50 ns 5F r a m e P u l s e W i d t h t F0W 244 ns 6 10.24 MHz Clock Jitter (wrt C4 )J C ±15 ns Note 2 Channel 31 Bit 0 Channel 0 Bit 7 Channel 0 Bit 6 ST-BUS BIT CELLS 2.0V 0.8V 2.0V 0.8V tC4P tC4WtF0S tF0H tF0W tC4W OSC1 2.0V 0.8V 3.0V 2.0V JC Φ

Zarlink Semiconductor Inc. † Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25 °C, for design aid only: not guaranteed and not subject to production testing. Figure 18 - RCK , TCK & CLD Timing For MOD Mode Characteristics Sym. 80 kbit/s 160 kbit/s Units Test 1T C K /RCK Clock Period t CP 12.5 6.25 ms 2 TCK/RCK Clock Width tCW 6.25 3.125 ms

3 TCK/RCK Clock Transition

tCT 20 20 ns C L=40pF 4C L D to TCK Setup Time tCLDS 3.125 1.56 ms 5C L D to TCK Hold Time tCLDH 3.125 1.56 ms 6C L D Width Low tCLDW 6.05 2.925 ms 7C L D Period tCLDP 8xtCP 8xtCP ms RCK TCK CLD tCT tCP tCLDS tCLDH tCW tCT tCLDW tCW 2.4V 0.4V 2.4V 0.4V 2.4V 0.4V tCP Note 1: TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the DV port. RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the Do output and may be skewed with respect to TCK due to end-to-end delay. Note 2: At the slave end TCK is phase locked to RCK. The rising edge of TCK will lead the rising edge of RCK by approximately 90o.

Zarlink Semiconductor Inc. † Timing is over recommended temperature & power supply voltage ranges. Figure 19 - Data Timing For DN Mode † Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25 °C, for design aid only: not guaranteed and not subject to production testing. Characteristics Sym. Min. Typ.* Max. Units Test Conditions

1 DSTi/CDSTi Data Setup Time t RS 30 ns

2 DSTi/CDSTi Data Hold Time t RH 50 ns

3a DSTo/CDSTo Data Delay t TD 120 ns C L=40pF 3b DSTo/CDSTo High Z to Data Delay t ZTD 140 ns C L=40pF Characteristics Sym. 80 kbit/s 160 kbit/s Units Test

1 Di/CDi Data Setup Time t DS 150 150 ns

2 Di/CDi Data Hold Time t DH 4.5 2.5 µs

3 Do Data Delay Time t RD 70 70 ns C L=40pF

4 CDo Data Delay Time t TD 70 70 ns C L=40pF

Performance Characteristics of the MT9171 DSIC Characteristics Sym. Min. Typ. * Max. Units Test Conditions

1 Allowable Attenuati on for Bit Error

Rate of 10-6 (Note 1) Afb 0 30 25 dB SNRŠ16.5dB (300kHz bandlimited noise)

2 Line Length at 80 kbit/s -24 AWG

-26 AWG L80 3.0 2.2 km attenuation - 6.9 dB/km attenuation - 10.0 dB/km

3 Line Length at 160 kbit/s -24 AWG

-26 AWG L160 3.0 2.2 km attenuation - 8.0 dB/km attenuation - 11.5 dB/km 2.0V 0.8V 2.4V 0.4V 2.0V 0.8V Bit Stream DSTi CDSTi DSTo CDSTo Bit Cell tTD tRS tRH tTDtZTD

Zarlink Semiconductor Inc. Note 1: Attenuation measured from Master L OUT to Slave L IN at 3/4baud frequency. * Typical figures are at 25 °C, for design aid only: not guaranteed and not subject to production testing. Figure 20 - Data Timing for Master Modem Mode Performance Characteristics of the MT9172 DNIC Characteristics Sym. Min. Typ. * Max. Units Test Conditions Rate of 10-6 (Note 1) Afb 04 0 3 3d B S N R ≥16.5dB (300 kHz bandlimited noise) -26 AWG L80 5.0 3.4 km attenuation - 6.9 dB/km attenuation - 10.0 dB/km -26 AWG L160 4.0 3.0 km attenuation - 8.0 dB/km attenuation - 11.5 dB/km Tx Bit Stream TCK Di CDI CDo Rx Bit Stream Do 2.4V 0.4V 2.0V 0.8V 2.4V 0.4V 2.4V 0.4V Bit Cell tDS tDH tTDtTD tRD tRD Bit Cell RCK

Zarlink Semiconductor Inc. Figure 21 - Data Timing for Slave Modem Mode TCK Di CDI CDo Do 2.4V 0.4V 2.0V 0.8V 2.4V 0.4V 2.4V 0.4V tDS tDH tTDtTD RCK ¼ tCP

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