MT9172AE

MT9171 ZARLINK | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 25

Technical content

Features

• Full duplex transmission over a single twisted pair
• Selectable 80 or 160 kbit/s line rate
• Adaptive echo cancellation
• Up to 3km (9171) and 4 km (9172)
• ISDN compatible (2B+D) data format
• Transparent modem capability
• Frame synchronization and clock extraction
• Zarlink ST -BUS compatible
• Low power (typically 50 mW), single 5V supply

Applications

• Digital subscriber lines
• High speed data transmission over twisted wires
• Digital PABX line cards and telephone sets
• 80 or 160 kbit/s single chip modem Figure 1 - Functional Block Diagram DSTi/Di CDSTi/ F0/CLD C 4/TC K F0o/RC K MS0 MS1 MS2 RegC DSTo/Do CDSTo/ CDo Transmit Interface Prescrambler Scrambler Control Register Transmit/ Clock Receive Timing & Control Status Transmit Timing Master Clock Phase Locked Sync Detect Receive DPLL Receive Interface De - Prescrambler Descrambler Differentially Encoded Biphase Receiver Differentially Encoded Biphase Transmitter Transmit Filter & Line Driver Receive Filter MUX Address Echo Canceller Error Signal Echo Estimate V Bias VDD VSS VBias VRef LOUT LOUT DIS Precan LIN OSC2 OSC1 CDi DS5130 ISSUE 3 February 1999

Description

MT9171 (DSIC) and MT9172 (DNIC) are pin for pin compatible replacements for the MT8971 and MT8972, respectively. They are multi-function devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair. They use adaptive echo-cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modem with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted. The MT9171/72 is fabricated in Zarlink’s ISO CMOS process.

Ordering Information

MT9171AE 22 Pin Plastic DIP (400 mil) MT9171AN 24 Pin SSOP MT9171AP 28 Pin PLCC MT9172AE 22 Pin Plastic DIP (400 mil) MT9172AN 24 Pin SSOP MT9172AP 28 Pin PLCC -40 C to C MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit ISO -CMOS ST -BUS FAMIL Y

Figure 2 - Pin Connections Pin Description Pin # Name Description22 24 28 11 2 L OUT Line Out. Transmit Signal output (Analog). Referenced to V Bias 22 3 V Bias Internal Bias Voltage output. Connect via 0.33 µ F decoupling capacitor to V DD 33 4 V Ref Internal Reference Voltage output. Connect via 0.33 µ F decoupling capacitor to V DD 4,5, 4,5, 5,7, MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the various operating modes for a particular application. See Table 1 for the operating modes. 7 7 9 RegC Regulator Control output (Digital). A 512 kHz clock used for switch mode power supplies. Unused in MAS/MOD mode and should be left open circuit. 8 9 10 F0 /CLD Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative pulse input for the MASTER indicating the start of the active channel times of the device. Output for the SLAVE indicating the start of the active channel times of the device. Output in MOD mode providing a pulse indicating the start of the C- channel. 9 10 12 CDSTi/ CDi Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control & signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 10 11 13 CDSTo/ CDo Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial control & signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 11 12 14 V SS Negative Power Supply (0V). 12 13 15 DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 11 12

22 PIN PDIP

C 4/TC K F0o/RC K DSTi/Di DSTo/Do

28 PIN PLCC

C 4/TC K MS2 NC MS1 MS0 RegC F 0/CLD NC CDSTi/CDi CDSTo/CDo VSS DSTo/Do NC F0o/RC K DSTi/Di 12 13

24 PIN SSOP

F 0/CLD CDSTi/CDi CDSTo/CDo VSS NC VDD LIN TEST LOUT DIS Precan OSC1 OSC2 C 4/TC K F0o/RC K DSTi/Di DSTo/Do NC

(Digital). A 2.048 Mbit/s serial PCM/data input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 14 15 17 F0o /RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns wide negative pulse indicating the end of the active channel times of the device to allow daisy chaining. In MOD mode provides the receive bit rate clock to the system. 15 16 19 C4 /TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin provides the transmit bit rate clock to the system. 16 17 21 OSC2 Oscillator Output . CMOS Output. 17 19 22 OSC1 Oscillator Input 18 20 23 Precan Precanceller Disable. When held to Logic ’1 the internal path from L OUT to the precanceller is forced to V Bias thus bypassing the precanceller section. When logic ’0’, the L OUT to the precanceller path is enabled and functions normally. An internal pulldown (50 k Ω ) is provided on this pin. 1,6, 11, 18, 20, NC No Connection. Leave open circuit 19 21 24 L OUT DIS L OUT Disable. When held to logic “1”, L OUT is disabled (i.e., output = V Bias ). When logic “0”, L OUT functions normally. An internal pulldown (50 k Ω ) is provided on this pin. 20 22 26 TEST Test Pin. Connect to V SS 21 23 27 L IN Receive Signal input (Analog). 22 24 28 V DD Positive Power Supply (+5V) input. Pin Description (continued) Pin # Name Description22 24 28

Advance Information MT9171/72 9-119 Functional Description The MT9171/72 is a device which may be used in practically any application that requires high speed data transmission over two wires, including smart telephone sets, workstations, data terminals and computers. The device supports the 2B+D channel format (two 64 kbit/s B-channels and one 16 kbit/s D- channel) over two wires as recommended by the CCITT. The line data is converted to and from the ST - BUS format on the system side of the network to allow for easy interfacing with other components such as the S-interface device in an NT1 arrangement, or to digital PABX components. Smart telephone sets with data and voice capability can be easily implemented using the MT9171/72 as a line interface. The device’s high bandwidth and long loop length capability allows its use in a wide variety of sets. This can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in both the home and central office or remote concentration equipment. Within the subscriber equipment the MT9171/72 would terminate the line and encode/ decode the data and voice for transmission while additional electronics could provide interfaces for a standard telephone set and any number of data ports supporting standard data rates for such things as computer communications and telemetry for remote meter reading. Digital workstations with a high degree of networking capability can be designed using the DNIC for the line interface, offering up to 160 kbit/s data transmission over existing telephone lines. The MT9171/72 could also be valuable within existing computer networks for connecting a large number of terminals to a computer or for intercomputer links. With the DNIC, this can be accomplished at up to 160 kbit/s at a very low cost per line for terminal to computer links and in many cases this bandwidth would be sufficient for computer to computer links. Figure 1 shows the block diagram of the MT9171/72. The DNIC provides a bidirectional interface between the DV (data/voice) port and a full duplex line operating at 80 or 160 kbit/s over a single pair of twisted wires. The DNIC has three serial ports. The DV port (DSTi/Di, DSTo/Do), the CD (control/data) port (CDSTi/CDi, CDSTo/CDo) and a line port (L IN, LOUT ). The data on the line is made up of information from the DV and CD ports. The DNIC must combine information received from both the DV and CD ports and put it onto the line. At the same time, the data received from the line must be split into the various channels and directed to the proper ports. The usable data rates are 72 and 144 kbit/s as required for the basic rate interface in ISDN. Full duplex transmission is made possible through on board adaptive echo cancellation. The DNIC has various modes of operation which are selected through the mode select pins MS0-2. The two major modes of operation are the MODEM (MOD) and DIGITAL NETWORK (DN) modes. MOD mode is a transparent 80 or 160 kbit/s modem. In DN mode the line carries the B and D channels formatted for the ISDN at either 80 or 160 kbit/s. In the DN mode the DV and CD ports are standard ST - BUS and in MOD mode they are transparent serial data streams at 80 or 160 kbit/s. Other modes include: MASTER (MAS) or SLAVE (SLV) mode, where the timebase and frame synchronization are provided externally or are extracted from the line and DUAL or SINGLE (SINGL) port modes, where both the DV and CD ports are active or where the CD port is inactive and all information is passed through the DV port. For a detailed description of the modes see “Operating Modes” section. In DIGITAL NETWORK (DN) mode there are three channels transferred by the DV and CD ports. They are the B, C and D channels. The B1 and B2 channels each have a bandwidth of 64 kbit/s and are used for carrying PCM encoded voice or data. These channels are always transmitted and received through the DV port (Figures 3, 4, 5, 6). The C- channel, having a bandwidth of 64 kbit/s, provides a means for the system to control the DNIC and for the DNIC to pass status information back to the system. The C-channel has a Housekeeping (HK) bit which is the only bit of the C-channel transmitted and received on the line. The 2B+D channel bits and the HK bit are double-buffered. The D-channel can be transmitted or received on the line with either an 8, 16 or 64 kbit/s bandwidth depending on the DNIC’s mode of operation. Both the HK bit and the D- channel can be used for end-to-end signalling or low speed data transfer. In DUAL port mode the C and D channels are accessed via the CD port (Figure 7) while in SINGL port mode they are transferred through the DV port (Figures 5, 6) along with the B1 and B2 channels.

subtracted from the precancelled received signal. comparator and passed to the biphase receiver. this new estimate is stored back in RAM. the following devices receiving its predecessor’s F0o. In MOD mode, all the ports have a different format. clocks for transmit and receive data, respectively. relationship to the data on the DV port. whether DN or MOD mode is used. Table 1. Mode Select Pins

SINGL port option only exists in DN mode. Table 2. Mode Definitions Table 3. Pin Configurations and the DV port transferring the B1& B2 channels. port is disabled and CDSTi should be pulled high.

2.048 Mbits/s and the line at 80 or 160 kbits/s configured according to the applicable ISDN

• The D-channel is transferred before the C-channel following F0.

C-D C BEFORE D-CHANNEL - The C-channel is transferred before the D-channel following F0. modes of operation DV and CD ports are enabled during the appropriate channel times.

1 CLD Output RCK Output TCK Output

5 CLD Output RCK Output TCK Output

received in the B1-channel timeslot. written to the Diagnostics Register (Table 5). Table 4. Control Register -At 160 kbit/s full convergence requires 850 ms with ATTACK held high for the first 240 frames or 30 ms. -At 80 kbit/s full convergence requires 1.75 s with ATTACK held high for the first 480 frames or 60 ms. depending upon the status of bit-3. 0 Reg Sel-1 Register Select-1. Must be set to ’0’ to select the Control Register. 1 Reg Sel-2 Register Select-2. Must be set to ’0’ to select the Control Register. "1", the Diagnostics Register will not be reset. 3 BRS Bit Rate Select. When set to ’0’ selects 80 kbit/s. When set to ’1’, selects 160 kbit/s.

4 DINB

timeslot on the line providing a 64 kbit/s D-channel link.

5 PSEN

canceller will require the normal amount of time to converge to a reflection coefficient.

➂ Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode. ➃ Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode. Table 5. Diagnostic Register depending upon the status of bit-3. ➁ Do not use LOUT to LIN loopback in DN/SLV mode. ➂ Do not use DSTo to DSTi loopback in MOD/MAS mode. PSEN, DINB, DRR and all diagnostics are disabled. PSEN, DINB, DRR and all diagnostics are disabled. 0 Reg Sel-1 Register Select-1. Must be set to ’0’ to select the Diagnostic Register. 1 Reg Sel-2 Register Select-2. Must be set to ’1’ to select the Diagnostic Register. 0 0 All loopback testing functions disabled. Normal operation. 0 1 DSTi internally looped back into DSTo for system diagnostics. recovery circuitry. When set to ’0’, the operation continues in synchronization.

5 PSWAP

6 DLO

’0’, LOUT pin functions normally. 7 Not Used Must be set to ’0’ for normal operation.

Table 6. Status Register

0 SYNC Synchronization - When set this bit indicates that synchronization to the received

line data sync pattern has been acquired. For DN mode only. noise. The farther this 2 bit value is from 0 the better the SNR. 3 Rx HK Housekeeping - This bit is the received housekeeping (HK) bit from the far end. 4-6 Future Future Functionality. These bits return Logic 1 when read. positive going transition indicating a logic "1". which are critical for adaptive echo cancellation. extraction at the receiving end. There is no D.C. made available to be put onto the line biased at VBias. delayed symbols of the near end signal. B2 channels are transmitted.

Advance Information MT9171/72 9-129 Typical connection diagrams are shown in Figures 13 and 14 for the DN mode as a MASTER and SLAVE, respectively. L OUT is connected to the coupling transformer through a resistor R2 and capacitors C2 and C2’ to match the line characteristic impedance. Suggested values of R2, C2 and C2’ for 80 and 160 kbit/s operation are provided in Figures 13 and 14. Overvoltage protection is provided by R1, D1 and D2. C1 is present to properly bias the received line signal for the L IN input. A 2:1 coupling transformer is used to couple to the line with a secondary center tap for optional phantom power feed. Varistors have been shown for surge protection against such things as lightning strikes. If the scramblers power up with all zeros in them, they are not capable of randomizing all-zeros data sequence. This increases the correlation between the transmit and receive data which may cause loss of convergence in the echo canceller and high bit error rates. In DN mode the insertion of the SYNC pattern will provide enough pseudo-random activity to maintain convergence. In MOD mode the SYNC pattern is not inserted. For this reason, at least on ”1” must be fed into the DNIC on power up to ensure that the scramblers will randomize any subsequent all-zeros sequence. Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s DV Port ST-BUS CD Port ST-BUS Master Clocks Mode Select Lines +5V 0.33 µF 0.33 µF DSTi DSTo CDSTi CDSTo C 4 MS0 MS1 MS2 VRef VBias LOUT LIN OSC1 OSC2 F0o NC D.C. coupled, Frequency locked 10.24 MHz clock. R2 = 390Ω R1 = 47Ω C2’ = 1.5 nF C2 = 22 nF +5V D1 = D2 = MUR405 2 : 1 1.0 µF Line Feed Voltage For 80 kbit/s: C2’ = 3.3 nF C1 = 0.33 µF

68 Volts

(Typ)

2.5 Joules

0.02 Watt

Note: Low leakage diodes (1 & 2) are required so that the DC voltage at L IN ≈ VBias To Next DNIC MT9171/72 Characteristics DN Mode. Clock Timing Refer to AC Electrical DV Port ST-BUS CD Port ST-BUS Master Clocks Mode Select Lines +5V 0.33 µF 0.33 µF DSTi DSTo CDSTi CDSTo C 4 MS0 MS1 MS2 V Ref VBias LOUT LIN OSC1 OSC2 R2 = 390Ω R1 = 47Ω C2’ = 1.5 nF C2 = 22 nF +5V D1 = D2 = MUR405 2:1 1.0 µF For 80 kbit/s: C2’ = 3.3 nF C1 = 0.33 µF (Typ) Note: Low leakage diodes (1 & 2) are required so that the DC voltage at LIN ≈ VBias

10.24 MHz XTAL

C3=33pF=C4 Supply MT9171/72

MT9171/72 Advance Information 9-130 ** Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. † Parameters over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. † Parameters over recommended temperature & power supply voltage ranges. Absolute Maximum Ratings** - Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Symbol Min Max Units 1 Supply Voltage V DD -0.3 7 V 2 Voltage on any pin (other than supply) V Max -0.3 V DD +0.3 V

3 Current on any pin (other than supply) I Max 40 mA

4 Storage Temperature T ST -65 +150 °C

5 Package Power Dissipation (Derate 16mW/°C above 75°C) PDiss 750 mW

Recommended Operating Conditions† - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ* Max Units Test Conditions 1 Operating Supply Voltage V DD 4.75 5.00 5.25 V

2 Operating Temperature T OP -40 +85 °C

3 Input High Voltage (except OSC1) VIH 2.4 V DD V for 400 mV noise margin 4 Input Low Voltage (except OSC1) V IL 0 0.4 V for 400 mV noise margin Characteristics Sym Min Typ* Max Units Test Conditions O U T P U T S Operating Supply Current I DD 10 mA 2 Output High Voltage (ex OSC2) V OH 2.4 V I OH =10mA

3 Output High Current

(except OSC2) IOH 10 mA Source current. V OH =2.4V 4 Output High Current - OSC2 I OH 10 µA Source current VOH =3.5V 5 Output Low Voltage (ex OSC2) V OL 0.4 V I OL =5mA

6 Output Low Current

(except OSC2) IOL 5 7.5 mA Sink current. V OL =0.4V 7 Output Low Current - OSC2 I OL 10 µA Sink current. VOL =1.5V 8 High Imped. Output Leakage I OZ 10 µAV IN=VSS to VDD

9 Output Voltage (V Ref)

(VBias) VO VBias-1.8 VDD /2 V V10 I N P U T S Input High Voltage (ex OSC1) VIH 2.0 V 12 Input Low Voltage (ex OSC1) V IL 0.8 V 13 Input High Voltage (OSC1) V IHo 4.0 V 14 Input Low Voltage (OSC1) V ILo 1.0 V

15 Input Leakage Current I IL 10 µAV IN=VSS to VDD

16 Input Pulldown Impedance

ZPD 50 k Ω

17 Input Leakage Current for

IIOSC 20 µA

Advance Information MT9171/72 9-131 † Timing is over recommended temperature & power supply voltages. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ➀ Duty cycle is measured at VDD /2 volts. † Timing is over recommended temperature & power supply voltages. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Notes: 1) When operating as a SLAVE the C4 clock has a 40% duty cycle. 2) When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e., FC =2.5xfC4 ). The relative phase between these two clocks (Φ in Fig. 17) is not critical and may vary from 0 ns to tC4P . However, the relative jitter must be less than JC (see Figure 17). Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams Characteristics Sym Min Typ* Max Units Test Conditions I N P U T S Input Voltage (L IN) VIN 5.0 V pp

2 Input Impedance (L IN)Z IN 20 k Ω fBaud=160 kHz

3 Crystal/Clock Frequency f C 10.24 MHz

4 Crystal/Clock Tolerance T C -100 0 +100 ppm

5a Crystal/Clock Duty Cycle ➀ DC C 40 50 60 % Normal temp. & V DD 5b Crystal/Clock Duty Cycle ➀ DC C 45 50 55 % Recommended at max./ min. temp. & VDD 6 Crystal/Clock Loading C L 33 50 pF From OSC1 & OSC2 to V SS . 7 O U T P U T S Output Capacitance (LOUT )C o 8p F

8 Load Resistance (L OUT )

(VBias, VRef) R Lout 500 100 Ω kΩ

9 Load Capacitance (L OUT )

(VBias, VRef) C Lout 0.1 20 pF µF Capacitance to VBias. 10 Output Voltage (L OUT )V o 3.2 4.3 4.6 V pp R Lout = 500Ω , CLout = 20pF Characteristics Sym Min Typ* Max Units Test Conditions 1C 4 Clock Period t C4P 244 ns 2C 4 Clock Width High or Low t C4W 122 ns In Master Mode - Note 1

3 Frame Pulse Setup Time t F0S 50 ns

4 Frame Pulse Hold Time t F0H 50 ns

5 Frame Pulse Width t F0W 244 ns

6 10.24 MHz Clock Jitter (wrt C4)J C ±15 ns Note 2 Channel 31 Bit 0 Channel 0 Bit 7 Channel 0 Bit 6 ST-BUS BIT CELLS

MT9171/72 Advance Information 9-132 Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode † Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Figure 18 - RCK, TCK & CLD Timing For MOD Mode Characteristics Sym 80 kbit/s 160 kbit/s Units Test ConditionsMin Typ* Max Min Typ* Max 1 TCK /RCK Clock Period t CP 12.5 6.25 µs 2 TCK /RCK Clock Width tCW 6.25 3.125 µs

3 TCK /RCK Clock Transition TimetCT 20 20 ns C L=40pF

4 CLD to TCK Setup Time tCLDS 3.125 1.56 µs 5 CLD to TCK Hold Time tCLDH 3.125 1.56 µs 6 CLD Width Low tCLDW 6.05 2.925 µs

7 CLD Period tCLDP 8xtCP 8xtCP µs

2.0V 0.8V 2.0V 0.8V tC4P tC4WtF0S tF0H tF0W tC4W OSC1 2.0V 0.8V 3.0V 2.0V JC Φ RCK TCK CLD tCT tCP tCLDS tCLDH tCW tCT tCLDW tCW 2.4V 0.4V 2.4V 0.4V 2.4V 0.4V tCP Note 1: TC K and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the DV port. RC K, also generated on chip, is extracted from the receive data and only clocks out the data at the Do output and may be skewed with respect to TC K due to end-to-end delay. Note 2: At the slave end TC K is phase locked to RC K. The rising edge of TCK will lead the rising edge of RCK by approximately 90o.

Advance Information MT9171/72 9-133 † Timing is over recommended temperature & power supply voltage ranges. Figure 19 - Data Timing For DN Mode † Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Note 1: Attenuation measured from Master LOUT to Slave LIN at 3/4baud frequency. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ* Max Units Test Conditions

1 DSTi/CDSTi Data Setup Time t RS 30 ns

2 DSTi/CDSTi Data Hold Time t RH 50 ns

3a DSTo/CDSTo Data Delay t TD 120 ns C L=40pF 3b DSTo/CDSTo High Z to Data Delay tZTD 140 ns C L=40pF Characteristics Sym 80 kbit/s 160 kbit/s Units Test ConditionsMin Typ* Max Min Typ* Max

1 Di/CDi Data Setup Time t DS 150 150 ns

2 Di/CDi Data Hold Time t DH 4.5 2.5 µs

3 Do Data Delay Time t RD 70 70 ns C L=40pF

4 CDo Data Delay Time t TD 70 70 ns C L=40pF

Performance Characteristics of the MT9171 DSIC Characteristics Sym Min Typ* Max Units Test Conditions

1 Allowable Attenuation for Bit Error

Rate of 10-6 (Note 1) Afb 0 30 25 dB SNR ≥16.5dB (300kHz bandlimited noise)

2 Line Length at 80 kbit/s -24 AWG

-26 AWG L80 3.0 2.2 km attenuation - 6.9 dB/km attenuation - 10.0 dB/km

3 Line Length at 160 kbit/s -24 AWG

-26 AWG L160 3.0 2.2 km attenuation - 8.0 dB/km attenuation - 11.5 dB/km Performance Characteristics of the MT9172 DNIC Characteristics Sym Min Typ* Max Units Test Conditions Rate of 10-6 (Note 1) Afb 0 40 33 dB SNR ≥16.5dB (300kHz bandlimited noise) -26 AWG L80 5.0 3.4 km attenuation - 6.9 dB/km attenuation - 10.0 dB/km -26 AWG L160 4.0 3.0 km attenuation - 8.0 dB/km attenuation - 11.5 dB/km 2.0V 0.8V 2.4V 0.4V 2.0V 0.8V Bit Stream DSTi CDSTi DSTo CDSTo Bit Cell tTD tRS tRH tTDtZTD

MT9171/72 Advance Information 9-134 Figure 20 - Data Timing for Master Modem Mode Tx Bit Stream TCK Di CDI CDo Rx Bit Stream Do 2.4V 0.4V 2.0V 0.8V 2.4V 0.4V 2.4V 0.4V Bit Cell tDS tDH tTDtTD tRD tRD Bit Cell RCK

Advance Information MT9171/72 9-135 Figure 21 - Data Timing for Slave Modem Mode TCK Di CDI CDo Do 2.4V 0.4V 2.0V 0.8V 2.4V 0.4V 2.4V 0.4V tDS tDH tTDtTD RCK π tCP

www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I 2C Patent rights to use these components in and I 2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE For more information about all Zarlink products visit our Web Site at