MT9162AE

MT9162 ZARLINK | Alldatasheet

Document overview

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Technical content

Features

• Single 5 volt supply
• Programmable µ−law/A-law Codec and filters
• Fully differential output driver
• SSI digital interface
• SSI speed control via external pins CSLO-CSL2
• Individual transmit and receive mute controls
• 0 dB gain in receive path
• 6 dB gain in transmit path
• Low power operation
• ITU-T G.714 compliant

Applications

• Cellular radio sets
• Local area communications stations
• Line cards

Description

The MT9162 5 V single rail Codec incorporates a built- in Filter/Codec, transmit ant i-alias filter, a reference voltage and bias source. The device supports both A- law and µ-law requirements. The analog interface is cap able of driving a 20 k ohm load. The MT9162 is fabricated in Zarlink's ISO 2-CMOS technology ensuring low power consumption and high reliability. May 2006

Ordering Information

MT9162AE 20 Pin PDIP Tubes MT9162AS 20 Pin SOIC Tubes MT9162AN 20 Pin SSOP Tubes MT9162AN1 20 Pin SSOP* Tubes *Pb Free Matte Tin -40°C to +85 °C ISO2-CMOS MT9162

5 Volt Single Rail Codec

Figure 1 - Functional Block Diagram AIN+ AIN- AOUT + AOUT - FILTER/CODEC GAIN ENCODER DECODER 6dB 0 dB Analog Interface PCM Serial Interface Timing Control VDD VSS VBias VRef Din Dout STB CLOCKin PWRST IC A/µ CSL0 CSL1 CSL2 RXMute TXMute

Zarlink Semiconductor Inc. Figure 2 - Pin Connections Pin Description Pin # Name Description 1V Bias Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 µ F capacitor to VSS. Connect 1 µF capacitor to Vref. µ F capacitor to VSS. Connect 1 µF capacitor to VBias 3P W R S T Power-up Reset. Resets internal state of device via Schmitt Trigger input (active low). 4I C Internal Connection. Tie externally to VSS for normal operation. 5A / µ A/µ Law Selection. CMOS level compatible input pin governs the companding law used by the device. A-law selected when pin tied to VDD or µ-law selected when pin tied to VSS. 6R X M u t e Receive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation. CMOS level compatible. 7T X M u t e Transmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation. CMOS level compatible. CSL0 CSL1 CSL2 Clock Speed Select. These pins are used to program the speed of the SSI mode as well as the conversion rate between the externally supplied MCL clock and the 512 kHz clock required by the filter/codec. Refer to Table 2 for details. CMOS level compatible. 11 D out Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1 device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot defined by STB. 12 D in Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the falling edge of BCL during the timeslot defined by STB. CMOS level compatible. 13 STB Data Strobe. This input determines the 8-bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatible. 14 CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions. Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin when the bit clock is 128 kHz or 256 kHz. CMOS level compatible. 15 V DD Positive Power Supply. Nominally 5 volts. AIN- AIN+VBias VRef IC RXMUTE CSL0 CSL1 CSL2 Din Dout VSS AOUT + AOUT - VDD 10 11 PWRST TXMUTE STB CLOCKin

20 PIN PDIP/SOIC/SSOP

A/µ

Zarlink Semiconductor Inc. Overview The 5 V single rail Codec features complete Analog/D igital and Digital/Analog c onversion of audio signals (Filter/Codec) and an analog interface to a standard analog transmitter and receiver (Analog Interface). The receiver amplifier is capable of driving a 20 k ohm load. Functional Description Filter/Codec The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion. The Filter/Codec block also implement s a transmit audio path gain in the analog domain. Figure 3 depicts the nominal half-channel for the MT9162. The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide dynamic range from a single 5 volt supply design. This full y differential architecture is continued into the analog interface section to provide full chip realization of these capabilities for the external functions. A reference voltage (V Ref), for the conversion requirements of the Codec section, and a bias voltage (V Bias), for biasing the internal analog sect ions, are both generated on-chip. V Bias is also brought to an external pin so that it may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from VBias to analog ground at all times. Likewise, although V Ref may only be used internally, a 0.1 µF capacitor from the V Ref pin to ground is required at all times. The analog ground reference point for these two capacitors must be physically the same point. To facilitate this the VRef and VBias pins are situated on adjacent pins. The transmit filter is designed to meet ITU-T G.714 specifications. An anti-aliasing filter is included. This is a second order lowpass implementation with a corner frequency at 25 kHz. The receive filter is designed to meet ITU-T G.714 specific ations. Filter response is peaked to compensate for the sinx/x attenuation caused by the 8 kHz sampling rate. Companding law selection for the Filter/Codec is provided by the A/ µ companding control pin. Table 1 illustrates these choices. 16 AOUT- Inverting Analog Output. (balanced). 17 AOUT+ Non-Inverting Analog Output. (balanced). 18 V SS Ground. Nominally 0 volts. 19 Ain- Inverting Analog Input. No external anti-aliasing is required. 20 Ain+ Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required. Pin Description (continued) Pin # Name Description

Zarlink Semiconductor Inc. Table 1 - Law Selection Analog Interfaces Standard interfaces are provided by the MT9162. These are:

• The analog inputs (transmitter), pins AIN+/AIN-. The maximum peak to peak input is 3.667Vpp µ−law and across AIN+/AIN- 3.8Vpp A-law.
• The analog outputs (re ceiver), pins AOUT+/AOUT-.This in ternally compensated fully differential output driver is capable of driving a load of 20k ohms. PCM Serial Interface A serial link is required to transport data between the MT9162 and an external digital transmission device. The MT9162 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly referred to as Simple Serial Interface (SSI). The required mode of operation is selected via the CSL2-0 control pins. See Table 2 for selections based in CSL2- 0 pin settings. Quiet Code The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the Figure 2 - Table 2: Bi t Clock Rate Selection TxMute pin is high. When either of these pins are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet code definition. Code ITU-T (G .711) µ -Law A-Law + Full Scale 1000 0000 1010 1010 + Zero 1111 1111 1101 0101 -Zero (quiet code) 0111 1111 0101 0101 - Full Scale 0000 0000 0010 1010 CSL2 CSL1 CSL0 External Clock Bit Rate (kHz) CLOCKin (kHz) 1 0 0 128 4096 1 0 1 256 4096 000 5 1 2 5 1 2 0 0 1 1536 1536 0 1 0 2048 2048 0 1 1 4096 4096

Zarlink Semiconductor Inc. SSI Mode The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6. In SSI mode the MT9162 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel data are always in the channel defined by the STB input. The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This is an active high signal with an 8 kHz repetition rate. SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is 512 kHz or greater then it is used directly by the in ternal MT9162 functions allowing synchronous operation. If the available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal MT9162 functions. internal clocks to allow operation w hen the external master and bit clocks are asynchronous. Control pins CSL2, CSL1 and CSL0 are used to program the bit rates. Figure 3 - Audio Gain Partitioning For synchronous operation, data is sampled from Din, on the falling edge of BCL during the time slot defined by the STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input. Dout is tri-stated at all times when STB is not true. If STB is valid, then quiet code will be transmitted on Dout during the valid strobe period. There is no frame delay through the PCM serial circuit for synchronous operation. Serial Port Filter/Codec and Analog Interface PCM Receive Filter Gain 0 dB Receiver Driver -2.05 dB Aout + Aout- 20kΩ Internal To Device External To Device AIN+ AIN- Transmit Gain 8.42 dB Transmit Gain -0.37 dB Transmit Filter Gain 0 to +7 dB (1 dB steps) PCM Analog Input Din Dout Transmit Filter Gain 0dB Decoder Encoder 2.05 dB -2.05 dB

Zarlink Semiconductor Inc. † Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Note 1: Power delivered to the load is in addition to the bias current requirements. Absolute Maximum Ratings† Parameter Symbol Min. Max. Units 1 Supply V oltage V DD - VSS - 0.3 7 V 2 V oltage on any I/O pin V I/VO VSS - 0.3 V DD + 0.3 V

3 Current on any I/O pin (transducers excluded) I I/IO ± 20 mA

4 Storage Temperature T S - 65 + 150 °C

5 Power Dissipation (package) P D 750 mW

Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Supply V oltage V DD 4 . 7 555 . 2 5 V 2 CMOS Input V oltage (high) V IHC 4.5 V DD V 3 CMOS Input V oltage (low) V ILC VSS 0.5 V

4 Operating Temperature T A - 40 + 85 °C

Characteristics Sym. Min. Typ. Max. Units Test Conditions

1 Static Supply Current (clock disabled) I DDC1 42 0 µA Outputs unloaded, Input

signals static, not loaded

2 Dynamic Supply Current:

Total all functions enabled I DDFT 7.0 10 mA See Note 1

Zarlink Semiconductor Inc. † DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Note 1 - Magnitude measurement, ignore signs. † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions 1 Input HIGH V oltag e CMOS inputs V IHC 3.5 V 2 Input LOW V oltage CMOS inputs V ILC 1.5 V 3 VBias V oltage Output V Bias VDD/2 V Max. Load = 10k Ω 4V Ref Output V oltage V Ref VDD/2- 1.9 VN o l o a d 5 Input Leakage Current I IZ 0.1 10 µAV IN=VDD to VSS

6 Positive Going Threshold

V oltage (PWRST only) Negative Going Threshold V oltage (PWRST only) VT+ VT- 3.7 1.3 V V 7 Output HIGH Current I OH 37 m A V OH = 0.9*VDD See Note 1 8 Output LOW Current I OL 51 0 m A V OL = 0.1*VDD See Note 1 9 Output Leakage Current I OZ 0.01 10 µAV OUT = VDD and VSS

10 Output Capacitance C o 15 pF

11 Input Capacitance C i 10 pF

Clockin Tolerance Characteristics† Characteristics Min. Typ. ‡ Max. Units Test Conditions

1 CLOCKin Frequency (Asynchronous

Mode) 4095.6 4096 4096.4 kHz (i.e., 100 ppm)

Zarlink Semiconductor Inc. † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. AC Characteristics† for A/D (Transmit) Path - 0dBm0 = ALo3.17 - 3.17dB = 1.773Vrms for µ-Law and 0dBm0 = ALo3.14 Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

1 Analog input equivalent to overload

ALi3.17 ALi3.14 7.334 7.6 Vp-p Vp-p µ-Law A-Law Both at Codec

2 Absolute half-channel gain

AIN ± to Dout G AX1 5.2 6.0 6.8 dB Transmit filter gain=0dB setting. @1020Hz 3 Gain tracking vs. input level ITU-T G .714 Method 2 GTX -0.3 -0.6 -1.6 0.3 0.6 1.6 dB dB dB 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 4 Signal to total Distortion vs. input level. ITU-T G .714 Method 2 D QX 35 dB dB dB 0 to -30 dBm0 -40 dBm0 -45 dBm0

5 Transmit Idle Channel Noise N CX

8.5 -71 -69 dBrnC0 dBm0p µ-Law A-Law

6 Gain relative to gain at

<50Hz 60Hz 200Hz 300 - 3000 Hz 3000 - 3400 Hz 4000 Hz >4600 Hz G RX -0.25 -0.9 -45 -23 -40 -25 -30 0.0 0.25 0.25 -12.5 -25 dB dB dB dB dB dB dB

7 Absolute Delay D

AX 360 µs at frequency of minimum delay

8 Group Delay relative to D AX DDX 750

µs µs µs µs 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz

9 Power Supply Rejection

f=1020 Hz f=0.3 to 3 kHz f=3 to 4 kHz f=4 to 50 kHz PSSR PSSR1 PSSR2 PSSR3 37 37 dB dB dB dB ±100mV peak signal on V DD µ-law PSSR1-3 not production tested

Zarlink Semiconductor Inc. † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. † Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. AC Characteristics† for D/A (Receive) Path - 0dBm0 = ALo3.17 - 3.17dB = 1.773Vrms for µ-Law and 0dBm0 = ALo3.14 Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

1 Analog output at the Codec full

ALo3.17 ALo3.14 7.225 7.481 Vp-p Vp-p µ-Law A-Law 2 Absolute half-channel gain. Din to AOUT± GAR1 -0.8 0 0.8 dB @1020Hz 3 Gain tracking vs. input level ITU-T G .714 Method 2 GTR -0.3 -0.6 -1.6 0.3 0.6 1.6 dB dB dB 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 4 Signal to total distortion vs. input level. ITU-T G .714 Method 2 G QR 35 dB dB dB 0 to -30 dBm0 -40 dBm0 -45 dBm0

5 Receive Idle Channel Noise N

-84 -80 dBrnC0 dBm0p µ-Law A-Law

6 Gain relative to gain at 1020Hz

4600 Hz G RR -0.25 -0.90 0.25 0.25 0.25 -12.5 -25 dB dB dB dB dB

AR 240 µs at frequency of min. delay

8 Group Delay relative to D AR DDR 750

µs µs µs µs 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz

9 CrosstalkD/A to A/D

-74 -80 dB dB G .714.16 ITU-T Electrical Characteristics† for Analog Outputs Characteristics Sym. Min. Typ. ‡ Max . Units Test Conditions

1 Load impedance at Output E ZL 20k ohms across AOUT ±

2 Allowable output capacitive

ECL 20 pF each pin:AOUT+, AOUT- 3 Analog output ha rmonic distortion E D 0.5 % 20k ohms load across AOUT± VO≤693mVRMS

Zarlink Semiconductor Inc. † Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. NOTE 1:Not production tested, guaranteed by design. Electrical Characteristics† for Analog Inputs Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

1 Maximum input voltage without

across AIN+/AIN- V IOLH 2.90 3.00 Vp-p A/ µ = 0 A/µ = 1

2 Input Impedance Z I 50 k Ω AIN+/AIN- to VSS

Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

1 BCL Clock Period t BCL 244 1953 ns BCL=4096 kHz to 512 kHz

2 BCL Pulse Width High t BCLH 122 ns BCL=4096 kHz

3 BCL Pulse Width Low t BCLL 122 ns BCL=4096 kHz

4 BCL Rise/Fall Time t R/tF 20 ns Note 1

5 Strobe Pulse Width t ENW 8 x tBCL ns Note 1

6 Strobe setup time before BCL falling t SSS 70 t BCL-80 ns

7 Strobe hold time after BCL falling t SSH 80 t BCL-80 ns

8 Dout High Impedance to Active Low

tDOZL 50 ns C L=150 pF, RL=1K

9 Dout High Impedance to Active High

tDOZH 50 ns C L=150 pF, RL=1K

10 Dout Active Low to High Impedance

tDOLZ 50 ns C L=150 pF, RL=1K

11 Dout Active High to High Impedance

tDOHZ 50 ns C L=150 pF, RL=1K

12 Dout Delay (high and low) from BCL

tDD 50 ns C L=150 pF, RL=1K

13 Din Setup time before BCL falling t DIS 20 ns

14 Din Hold Time from BCL falling t DIH 50 ns

Zarlink Semiconductor Inc. Figure 5 - SSI Synchronous Timing Diagram † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions

1 Bit Cell Period T DA TA 7812

BCL=128 kHz BCL=256 kHz

2 Frame Jitter T j 600 ns

3 Bit 1 Dout Delay from STB going

tdda1 Tj+600 ns C L=150 pF, RL=1K

4 Bit 2 Dout Delay from STB going

ns C L=150 pF, RL=1K

5 Bit n Dout Delay from STB going

(n-1) x TDA TA-Tj 600 + (n-1) x TDATA 600 + (n-1) x TDA TA+Tj ns C L=150 pF, RL=1K n=3 to 8

6 Bit 1 Data Boundary T DATA1 TDA TA-Tj TDA TA+Tj ns

7 Din Bit n Data Setup time from

tSU TDATA\\2 +500ns-Tj +(n-1) x TDATA ns n=1-8

8 Din Data Hold time from STB

tho TDATA\\2 +500ns+Tj +(n-1) x TDATA ns (BCL) Din Dout STB 70% 30% 70% 30% 70% 30% 70% 30% tBCLH tR tF tBCLL tDIS tDIH tDOZL tDD tBCL tDOZH tSSS tENW tSSH tDOLZ tDOHZ NOTE: Levels refer to% V DD (CMOS I/O) CLOCKin

Zarlink Semiconductor Inc. Figure 6 - SSI Asynchronous Timing Diagram Din Dout STB 70% 30% 70% 30% 70% 30% Tj tdda1 NOTE: Levels refer to% V DD (CMOS I/O) tdha1 TDATA1 tdda2 TDATA Bit 1 Bit 2 Bit 3 D1 D2 D3 tho tsu TDATA/2 TDATA TDATA

Zarlink Semiconductor Inc. Plastic Dual-In-Line Packages (PDIP) - E Suffix DIM 8-Pin 16-Pin 18-Pin 20-Pin Plastic Plastic Plastic Plastic Min Max Min Max Min Max Min Max B0 . 0 1 4 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) C0 . 0 0 8 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) D 0.348 (8.84) 0.430 (10.92) 0.745 (18.93) 0.840 (21.33) 0.845 (21.47) 0.925 (23.49) 0.925 (23.49) 1.060 (26.9) 32 1 E n-2 n-1 n L D e B C eA α Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) A

Zarlink Semiconductor Inc. NOTE: ( ) Millimeters S a1 5 ° 15° 15° 15° DIM 8-Pin 16-Pin 18-Pin 20-Pin Plastic Plastic Plastic Plastic Min Max Min Max Min Max Min Max

Zarlink Semiconductor Inc. DIM 16-Pin 18-Pin 20-Pi n 24-Pin 28-Pin Min Max Min Max Min Max Min Max Min Max A0 . 0 9 3 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) A1 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) B0 . 0 1 4 (0.351) 0.019 (0.488) 0.014 (0.351) 0.019 (0.488) 0.014 (0.351) 0.019 (0.488) 0.014 (0.351) 0.019 (0.488) 0.014 (0.351) 0.019 (0.488) C0 . 0 0 9 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) D0 . 3 9 8 (10.1) 0.413 (10.5) 0.447 (11.35) 0.469 (11.90) 0.496 (12.60) 0.518 (13.00) 0.598 (15.2) 0.614 (15.6) 0.697 (17.7) 0.712 (18.1) E0 . 2 9 1 (7.40) 0.305 (7.75) 0.291 (7.40) 0.305 (7.75) 0.291 (7.40) 0.305 (7.75) 0.291 (7.40) 0.305 (7.75) 0.291 (7.40) 0.305 (7.75) e 0.050 BSC (1.27 BSC)

0.050 BSC

(1.27 BSC) (1.27 BSC) (1.27 BSC) (1.27 BSC) F0 . 0 4 4 (1.125) 0.064 (1.625) 0.044 (1.125) 0.064 (1.625) 0.044 (1.125) 0.064 (1.625) 0.044 (1.125) 0.064 (1.625) 0.044 (1.125) 0.064 (1.625) Pin 1 B e F E A L H C G Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) O1 & O2 are SYMMETRY dimensions 5) A & B Maximum dimensions include allowable mold flash D L 4 mils (lead coplanarity)

Zarlink Semiconductor Inc. Lead SOIC Package - S Suffix G0 . 0 4 0 (1.016) 0.050 (1.270) 0.040 (1.016) 0.050 (1.270) 0.040 (1.016) 0.050 (1.270) 0.040 (1.016) 0.050 (1.270) 0.040 (1.016) 0.050 (1.270) H0 . 3 9 4 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) L0 . 0 1 6 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) DIM 16-Pin 18-Pin 20-Pi n 24-Pin 28-Pin Min Max Min Max Min Max Min Max Min Max

Zarlink Semiconductor Inc. Small Shrink Outline Package (SSOP) - N Suffix Pin 1 B e D F E A L H C G Dim 20-Pin 24-Pin 28-Pin 48-Pin M i nM a xM i nM a xM i nM a xM i nM a x A0 . 0 7 9 (2) -0 . 0 7 9 (2) 0.079 (2) 0.095 (2.41) 0.110 (2.79) A1 0.004 (0.1) 0.004 (0.1) 0.004 (0.1) 0.008 (0.2) 0.015 (0.4) B0 . 0 0 8 7 (0.22) 0.013 (0.33) 0.0087 (0.22) 0.013 (0.33) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.2) 0.0135 (0.34) C0 . 0 0 8 (0.21) 0.008 (0.21) 0.008 (0.21) 0.010 (0.25) D0 . 2 7 (6.9) 0.295 (7.5) 0.31 (7.9) 0.33 (8.5) 0.39 (9.9) 0.41 (10.5) 0.62 (15.75) 0.63 (16.00) E0 . 2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.291 (7.39) 0.299 (7.59) e 0.025 BSC (0.65 BSC)

0.025 BSC

(0.65 BSC) (0.65 BSC) (0.65 BSC) F 0.049 REF (1.25 REF)

0.049 REF

(1.25 REF) (1.25 REF)

0.056 REF

(1.42 REF) G0 . 0 6 5 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.089 (2.25) 0.099 (2.52) H0 . 2 9 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.395 (10.03) 0.42 (10.67) L0 . 0 2 2 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.02 (0.51) 0.04 (1.02) Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard M0-150 5) A & B Maximum dimensions include allowable mold flash

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