MT9085

MT9085 MITEL | Alldatasheet

Document overview

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Technical content

Features

• Configurable for parallel-to-serial or serial-to-parallel conversion of 1024 channels
• Interfaces to Mitel’s MT9080 Switch Matrix Module (SMX). Generates all framing signals required in 1K or 2K switching applications
• Serial data rates of 2.048 Mbit/s or 4.096 Mbit/s
• M i t e l S T - B U S compatible serial inputs/outputs

Applications

• Interfacing the MT9080 Switch Matrix Module to an ST-BUS system
• Rate conversion between 4 Mbit/s and 2 Mbit/s serial streams
• Interfacing a parallel system bus to devices utilizing serial I/O

Description

The MT9085 Parallel Access Circuit (PAC) provides an interface between an 8 bit, parallel time division multiplexed bus and a serial time division multiplexed bus. A single PAC device will accept data clocked out on the parallel bus of the Mitel MT9080 (SMX) and output it on 32/16 time division multiplexed serial bus streams. A second device can be configured to perform the conversion from the serial format into an SMX compatible parallel format. The time division, serial multiplexed streams may operate at 2.048 Mbit/s or at 4.096 Mbit/s. The PAC generates all framing signals required by the SMX for 1024 and 2048 channel configurations. Figure 1 - Functional Block Diagram S30 S31 LOAD C16 Parallel/Serial VSS VDD C16 Shift Registers Address Decoder Timing Generation Mode Control C4i F0i C16i C2o C4o F0o DFPo CFPo OE MCA MCB CKD 2/4S DFPo

Ordering Information

-40°C to 70°C ISSUE 3 January 1993 MT9085 PAC - Parallel Access Circuit CMOS

Figure 2 - Pin Connections P0VSS MCB VSS NC C2o C4o DFPo VDD VSS C16i F0i F0o DFPo CFPo IC IC MCA S10 S1 1 S12 S13 VDD VSS S14 S15 S16 S17 S18 S19 S20 S21 VSS VDD VSS S22 S23 S24 S25 S26 S27 VSS VDD S28 S29 S30 S31 CKD C4i OE 2/4S

Pin # Name Description 1V SS Ground. 2-9 S0-S7 Serial Input/Outputs (TTL compatible with internal pullups). Time division, multiplexed serial bus streams; inputs in serial to parallel mode (MCA=0), and outputs in parallel to serial mode (MCA=1). Data rate on the serial streams can be selected to be 2.048 Mbit/s (2/4S=0) or 4.096 Mbit/s (2/4S=1). Refer to Figures 3, 4 and 5 for functional timing information. 10 V SS Ground. 11-16 S8-S13 Serial Input/Outputs. See description for pins 2 - 9 above. 17 V DD Supply Input. +5V. 18 V SS Ground. 19-20 S14-S15 Serial Input/Outputs. See description for pins 2 - 9 above. 21-26 S16-S21 Serial Input/Outputs (TTL compatible with internal pullups). Time division, multiplexed serial bus streams which are configured as inputs in serial to parallel mode (MCA =0), and outputs in parallel to serial mode (MCA=1). Data is clocked at 2.048 Mbit/s (2 /4S = 0). These input/ outputs are inactive when the device is configured for 4.096 Mbit/s operation (2/4S=1). 27 V SS Ground. 28-33 S22-S27 Serial Input/Outputs. See description for pins 21-26 above. 34 V SS Ground. 35 V DD Supply Input +5V. 36-39 S28-S31 Serial Input/Outputs. See description for pins 21-26 above. 40 CKD Clock Delay (Input). Control input which configures internal device timing. CKD=0 Internal master counter is reset at the system frame boundary established by the frame pulse (F0i). CKD=1 Internal master counter is reset one C16 clock period after system frame boundary. All data input/output will be delayed by one C16 clock period. Timing for data input/output and for OE is affected by the level asserted on CKD. The relative phase between the frame boundary established by F0i and output signals F0o, C2o, C4o, DFPo, DFPo and CFPo is also affected by the state of the CKD input. See descriptions pertaining to each specific pin for more information. clock. The falling edge of C4i is used to clock in the frame pulse (F0i). 42 OE Output Enable (Input). When low, output data bus (serial or parallel) is actively driven. When set high, the output bus drivers are disabled. In serial to parallel mode, the outputs are disabled immediately after OE is taken High. See Figures 6 and 21 for timing information pertaining to parallel to serial mode. 43 2 /4S 2.048/4.096 Mbit/s Select (Input). Selects the data rate for the time division, multiplexed serial streams. When tied low, the data rate is 2.048 Mbit/s. When tied high, the data rate is 4.096 Mbit/s. 44 MCA Mode Control-A (Input). The device will perform a serial to parallel conversion when this input is tied low. When the input is tied high, the device operates in the parallel to serial mode. 45 IC Internal Connection. Must be tied to V SS for normal device operation. 46 IC Internal Connection. Should be left unconnected. 47 CFPo Connect Memory Frame Pulse (Output). Framing signal with a nominal 8 kHz frequency; goes low 71 (CKD=0) or 68 (CKD=1) C16 clock cycles before the frame boundary established by F0i. The signal is used by the connection memory in a typical 1k or 2k switch configuration. See Figure 15 for timing information.

Pin # Name Description 48 DFPo Data Memory Frame Pulse (Output). Framing signal with nominal 4 kHz frequency; changes state 64 (CKD=0) or 65 (CKD=1) C16 clock cycles after the frame boundary established by F0i. This signal is a complement of DFPo. See Figure 15 for timing information. The signal is used by SMXs (MT9080s) making up the Data Memory in a typical 1k or 2k switch configuration. 49 F0o Framing Type 0 Signal (Output). 8 kHz framing signal output by the PAC to indicate the frame boundary synchronized to C16. This framing signal is aligned with C4o and is output by the PAC for use by other devices in a typical switch configuration. Refer to Figures 4 and 5 for functional timing information.

50 F0i

Framing Type 0 Signal (TTL compatible input). This input signal establishes the frame boundary for the serial input/output streams. The first falling edge of C4i following the falling edge of F0i establishes the frame boundaries. Refer to Figure 13 for timing information. 51 C16i 16 MHz Clock Input. The 16.384 MHz clock signal input at this pin must be phase-locked to the 4.096 MHz clock input at C4i. See Figure 13 for timing information. 52 V SS Ground. 53 V DD Supply Input. +5V. 54 DFPo Data Memory Frame Pulse (Output). 4 kHz framing signal; changes state 64 (CKD=0) or 65 (CKD=1) C16 clock cycles after the frame boundary established by F0i. This signal is a complement of DFPo. See Figure 15. The signal is used by SMXs (MT9080s) making up the Data Memory in a typical 2k switch configuration.

55 C4o

4.096 MHz Clock Output. This is a 4.096 MHz clock signal derived from the 16 MHz master clock input at C16. The falling edge of C4o occurs in the middle of the regenerated frame pulse output at F0o. Refer to Figures 4 and 5 for functional timing information. 56 C2o 2.048 MHz Clock Output. This is a 2.048 MHz clock signal derived from the 16 MHz master clock input. The rising edge of this clock signal occurs in the middle of the regenerated frame pulse output at F0o . Refer to Figures 4 and 5 for functional timing information. 57 NC No Connection. 58 V SS Ground. 59 MCB Mode Control-B (Input). This control input performs two different functions, depending on the state of MCA pin. In parallel to serial mode (MCA=1), MCB defines which clock edge latches in the data. MCB=0 Data on the parallel bus is latched into the device with the every second falling edge of C16. See Figure 6. MCB=1 Data on the parallel bus is latched into the device with every alternate positive clock edge. In serial to parallel mode (MCA=0), the MCB pin controls the state of the parallel bus driver as follows: MCB=0 The output drivers are enabled for only half the timeslot. The data is clocked out on the first falling edge within the timeslot and disabled on the next falling edge. See Figure 7. MCB=1 The parallel data bus output drivers are enabled for the duration of the channel timeslot (two C16 Clock Periods). The data is clocked out on the first positive edge within a timeslot and disabled on the last edge. 60-67 P0-P7 Parallel Input/Output Data Bus. This 8 bit data bus is an output in serial to parallel mode (MCA=0), and an input in parallel to serial mode (MCA=1). Data is clocked in and out of the port by the C16 clock. The state of the CKD pin determines the relative phase of the critical clock edges with respect to the frame pulse. All inputs/outputs have internal pullups. Refer to Figures 6 and 7 for functional timing information. 68 V DD Supply. +5V. Pin Description (continued)

Figure 3 - Serial Input/Output Functional Timing Figure 4 - Channel and Frame Alignment (CKD = 0) Figure 5 - Channel and Frame Alignment (CKD = 1) S0-S31 2/4S = 0 S0-S15 2/4S = 1

512 C4 Cycles

2 Mbit/s

4 Mbit/S

Frame Boundary Established by F0i Ch. 31 Bit 1 Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 C16i C4o C2o F0o Serial I/O Frame Boundary Established by F0i Ch. 31 Bit 1 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 31 Bit 0

Figure 6 - Functional Data I/O Timing in Parallel to Serial Mode (MCA = 1) A AAA A AAA A AAA A AAA AAAA AAA A AAA A AAA A AAA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AA AA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA A AAA A AAA A AAA A AAAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAAA A AAA A AAA A AAA A AAA AAAA AAA AA A AA A AA A AA A AAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAA A AAA A AAA A AAA A AAAA A AAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAA A AAA A AAA A AAA A AAA A A AAA A AAA A AAA A AAA A AAA AA A AA A AA A AA A AA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A AA A AA A AA A AA A A AAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AA A AA A AA A AA A AA A A AAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AA A AA A AA A AA A AA A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAA A AAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA A A A A A A A A A A AAAA A AAA A AAA A AAA A AAA AAAA AA A A A A A A A A AA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA A AAA A AAA A AAA A AAAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA A AAA A AAA A AAA A AAAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAAA AAA A AAA A AAA A AAA A AAAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AA A AA A AA A AA A AAA AAA A A A A A A A A A A A A AAA C16i CKD=0 Serial Output S0-S31 Parallel Input MCB=0 OE Parallel Input MCB=1 OE CKD=1 Serial Output S0-S31 Parallel Input MCB=0 OE Parallel Input MCB=1 OE Ch. 31, Bit 0 Ch. 1, Bit 7 Ch. 1, Bit 7 C 1S1 C 1S2 C 1S3C 1S0C 0S31 C 1S1 C 1S2 C 1S3C 1S0C 0S31 C 2S 0 C 2S 0 C 1S1 C 1S2C 1S0 C 1S1 C 1S2C 1S0C 0S31 C 2S0 C 2S0 C 2S 1 C 2 Frame Boundary established by F0i

64 Cycles

Notes: C XS Y - on the parallel inputs indicates data closed in with the edge shown will be clocked out on Serial Stream Y, Channel X. Arrows in the row marked OE indicate the clock edge which latches in the state of the OE pin. CXSY written below the arrow indicates the serial output channel affected by the OE signal. For example, the level on OE clocked in with edge marked C1S1 will enable or disable the serial output drivers for stream 1 during channel 1. C 1S3 C 1S3C 0S31 Ch. 0, Bit 7 C 2S1C 1S1 Ch. 31, Bit 0 C 1S4C 1S2 C 1S3 Ch. 0, Bit 7 C 1S1 C 1S4C 1S2 C 1S3 C 1S1 C 1S4C 1S 2 C 1S3 C 2S1 C 2S 1 C 1S1 C 1S2 C 1S3 C 1S4 C 2S 1

Figure 7 - Functional Data I/O Timing in Serial to Parallel Mode (MCA = 0) AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA A AAA A AAA A AAA A AAA A AAA A AAAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A A A A A A A A A A AA AAA AAA AAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A A A A A A A A A A AA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAAA A AAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A A A A A A A A A A AA AAA AAA AAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A AAA A AAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA A A A A A A A A A A AA C16 Serial Input S0-S31 Parallel Output MCB=0 CKD=0 Parallel Output MCB=0 CKD=1 Parallel Output MCB=1 CKD=0 Parallel Output MCB=1 CKD=1 C 31S0 C 31S1 C 31S 2 C 31S3 C 31S0 C 31S1 C 31S2 C 31S3 C 31S0 C 31S1 C 31S 2 C 31S3 C 31S0 C 31S1 C 31S 2 C 31S3 C 30S31 C 30S31 C 30S31 Ch.31 Bit 0 Ch. 0, Bit 7 Ch.0 Bit 6 Frame Boundary established by F0i Note: C xSY - indicates data being output is sourced from Serial Stream Y, Channel X

Serial to Parallel Conversion The MT9085 can be configured to perform serial to parallel conversion by tying the MCA pin low. A single PAC will accept 1024 channels on the 32 or 16 serial streams and output the data onto the parallel bus as illustrated in Figure 8. The data on the serial input streams can be clocked in at 2.048 Mbit/s or at 4.096 Mbit/s by setting the appropriate level on the 2 /4S pin. See Figures 16 and 17 for timing details. Data is clocked out on the parallel bus with the C16 clock (see Figure 18 for timing details). The parallel output bus will be actively driven for two C16 clock periods when MCB is tied high. Data is output with every second rising clock edge. Setting MCB low will enable the output drivers for only one C16 clock period in any specific parallel channel timeslot. The actual phase relationship between the system frame boundary and the parallel output timeslots is affected by the level asserted on the CKD input (see Figure 7). The flexibility in output timing permits the PAC to be easily interfaced to the SMX in 1024 and 2048 channel configurations. Refer to the applications section of this data sheet for more information. The delay through the PAC is approximately one ST-BUS channel when the device is configured for 2.048 Mbit/s serial rate. In the 4.096 Mbit/s mode, the delay is equal to approximately eight C4 clock cycles. Timing and Framing Signals The PAC requires two clock signals. A 16.384 MHz master clock (C16) is used to clock data in and out of the device on the parallel bus. A 4.096 MHz clock (C4i ), phase locked to C16i, clocks in the frame pulse. The positive C16i edge immediately after the C4i falling edge which clocks in F0i defines the internal frame boundary. The two separate clock inputs permit synchronization of the MT9085 to system timing in which the frame pulse is derived from a 4.096 MHz clock. The PAC generates all framing signals necessary to construct a 1024 channel or a 2048 channel switch matrix using the SMX. The DFPo signal is used as a framing signal for the SMXs operated as the Data Memory. The CFPo is used to synchronize Connect Memory timing in a typical 1K or 2K switch application (refer to the application section in this data sheet for more information). The timing of both DFPo and CFPo signals is affected by the level asserted on the CKD input as shown in Figure 15. The PAC outputs ST-BUS timing signals, F0o , C2o and C4o derived from C16i. The phase relationship between the frame boundary established by F0i and F0o is illustrated in Figures 4 and 5.

1024 Channel Digital Time-Space Switch

A 1024 channel serial time-space digital switch design is illustrated in Figure 9. The main switching function is accomplished using two MT9080s (SMXs). One SMX is operated in the Data Memory mode and the second serves as the Connection Memory. Refer to the SMX data sheet for more information on this configuration. The serial to parallel conversion function is provided by a PAC configured for 2.048 Mbit/s operation (2 /4S = 0). The MCB input in this PAC is tied high to ensure data output by the PAC meets SMX input setup and hold requirement. PAC #2 performs the parallel to serial function; MCA is set high. The MCB input in this device is set low to allow data to be clocked in with the falling edge of C16. The main timing source generates a 16.384MHz clock phase locked to a 4.096MHz clock. The framing signal input to PAC#1 at F0i should meet the requirements specified in Figure 13 of this data sheet. In some applications where a master 16.384 MHz oscillator is used for system timing, the C4i and F0i clocks could be derived directly from it. In applications where a 4.096 MHz clock signal is available, the 16.384 MHz clock can be generated using a phase-lock loop. Framing signals for both the SMXs are generated by PAC #1. DFPo is connected to FP input of the Data Memory. CFPo is connected to the FP input of the Connection Memory. PAC #2 is configured to perform parallel to serial conversion. The DFPo and CFPo signals ensure that all timing requirements necessary to interface the SMXs with the PACs are met while input and output serial frames are aligned. The maximum delay through the switch is approximately one frame plus two serial channels when SMX#1 is operated in Data Memory Mode-1. When the SMX is operated in Data Memory Mode-2, the maximum delay is two frames. In this case, the channels are double buffered; frame integrity is maintained for all switching configurations.

In the example configuration shown in Figure 9 the OE pin of PAC #2 is connected to D10 on the Connection Memory. Setting bit 10 high in the Connection Memory location corresponding to a serial channel timeslot will result in the output driver for the specific stream being disabled during that serial channel timeslot. D11 is connected to the ME input of SMX1 and D12 is connected to a mode select pin (Mz). Consequently, the levels on these outputs can be set high or low by writing to the appropriate memory location corresponding to the selected output channel. The mapping of the control functions on to Connection Memory data bits is illustrated in Figure 10. The data on the PAC serial streams is byte interleaved as described in the Functional Description section in this data sheet. The SMX channel number corresponding to the channel on the serial streams can be determined directly by specifying the serial channel and stream number in binary as shown in Figure 11. For example, serial channel 4, stream 2 corresponds to SMX channel number Hex 0082. In order to program the matrix for switching, the input channel address is written to the Connection Memory address corresonding to the serial output channel. The bits controlling features such as OE , ME, and Mz should be set or reset accordingly at the same time. For example. if channel 4 on stream 2 is to be switched to channel 10 on stream 1, the following binary word is written to Connection Memory address corresponding to the output channel (Hex 0141): XXX0 10000000 0010 Stream Address Channel Address Output Enable Message Enable DM-1/DM-2 Unused Figure 9 - 1024 Channel Switch Matrix Using the PAC and SMX Timing Source C4i C16i S31

• •• /4S OE CKD MCA MCB P0-P7 DFPo CFPo PAC#1 S/P F0i
• •• S31 C16 C16 D0-D7i CK FP Mz R/W ODE A0-A9 ME D0-D7o Mx My CS DS SMX #1 DM - 1/2 F0 C4 C16 F0i C4i C16i P0-P7 OE CKD MCA MCB 2/4S
• •• S31
• •• S31 PAC#2 P/S SMX #2 CM - 1 D12 D0-D9 D11 D10 ODE Mx My Mz FP CK C16 MPU Interface NOTE: Connect all inputs not shown to VSS CONNECTION MEMORY DATA MEMORY DTA DS R/W CS A0-A15 CD D0-D15 From Timing Source

Figure 10 - Mapping of Data Memory and PAC Control Functions on Connection Memory Data Bits Figure 11 - Decoding SMX Channel Number from Serial Stream & Channel Address

1024 Switch Configuration

1 5 1 4 1 3 1 2 1 1 1 0 98 7654 3210 Not Used Serial Channel Number Stream Address OE - Output Enable ME - Message Enable Mode Control - DM-1 or DM-2 43 2104 3210 Unused Channel Address Stream Address Ex. Serial Stream 4, Channel 3 Corresponds to SMX Channel Number 100 (Hex 0064)

2048 Channel Digital Space-Time Switch

A 2048 channel serial time-space digital switch design is illustrated in Figure 12. The main switching function is accomplished using three MT9080s (SMXs). Two SMXs function as the data memory, while the third is operated in Connect Memory mode. Refer to the SMX data sheet for more information on this configuration. The Serial to parallel conversion for 2048 channels is handled by two PACs. PAC #1a and PAC #1b. Both are configured for 2.048 Mbit/s operation (2 /4S=0). The MCB input is tied low in both devices. The parallel data bus on each of the devices will be actively driven for one C16 clock period. The CKD input is set low in one of the devices and set high in the other. This will cause the output timing of the two PACs to be off set by one C16 clock period. Consequently, the parallel output of one device will be disabled while the other is active. The parallel to serial conversion is also accomplished with two PACs. Data from the common SMX parallel bus is clocked into each PAC in alternate clock periods. The timing source generates a 16.384 MHz clock phase locked to a 4.096 MHz clock. The framing signal input to PAC #1a at F0i should meet the requirements specified in this data sheet. In some applications where a master 16.384 MHz oscillator is used for system timing, the C4i and F0i clocks could be derived directly from it. The DFPo and DFPo generated by PAC #1a are used to switch the mode of operation of the Data Memory SMXs between Counter and External modes and also serve as the frame pulse for the two SMXs. Because DFPo and DFPo are complementary signals, one of the two SMXs is operated in the Counter mode while the second one is operated in the External mode. The states of the other control inputs, R/W and ODE, are changed accordingly. The SMX configured as the Connection Memory, is fed a frame pulse from PAC #1b. The phase alignment of CFPo with respect to DFPo ensures that timing requirements for proper operation of the SMXs are met. Refer to the SMX data sheet for more information on the timing requirements. The maximum delay through the switch is two frames. Channels are double buffered and frame integrity is maintained for all switching configurations. For more information, see Mitel’s Application Note MSAN-135, “Design of Large Digital Switching Matrices using the SMX/PAC“ (in this data book) and Application Sheet MSAS-62 “16.384 MHz Clock Generation for SMX/PAC“ (available from Mitel).

Figure 12 - 2048 Channel Switch Matrix Using the PAC and SMX Timing Source MF C16 C4i C16i S31

• ••• 2/4S OE CKD MCA MCB P0-P7 DFPo PAC#1a S/P F0i
• ••• S31 DFPo C16 D0-D7i CK FP Mz R/W ODE A0- ME D0-D7o Mx My CS DS SMX #1 CNT/EXT A10 D0-D7i FP Mz R/W ODE A0- ME D0-D7o Mx My CS DS SMX #2 CNT/EXT A10 C16 CK F0 C4 C16 C4i C16i S31 /4S OE CKD MCA MCB P0-P7 CFPo PAC#1b S/P F0i S31 F0i C4i C16i P0-P7 OE CKD MCA MCB 2/4S
• ••• S31 PAC#2b P/S F0i C4i C16i P0-P7 OE CKD MCA MCB 2/4S
• •• S31 PAC#2a P/S F0 C4 C16 From Timing Source
• •• S31
• ••• S31 F0 C4 C16 SMX #3 CM - 2 D12 D0-D10 D11 ODE Mx My Mz FP CK C16 MPU Interface CONNECTION MEMORY DTA DS R/W CS A0-A15 CD D0-D15 NOTE: Connect all inputs not shown to VSS

• Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings* - Voltages are with respect to Ground (VSS ) unless otherwise stated. Parameter Symbol Min Max Units 1V DD -VSS -0.3 7 V 2 Voltage on Digital Inputs V I VSS -0.3 V DD +0.3 V 3 Voltage on Digital Outputs V O VSS -0.3 V DD +0.3 V

4 Current at Digital Outputs I O 40 mA

5 Storage Temperature T S -40 125 °C

6 Package Power Dissipation P D 2W

Recommended Operating Conditions - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Operating Temperature T OP -40 70 °C

2 Positive Supply V DD 4.5 5.5 V

3 Input Voltage V I 0V DD V

Characteristics Sym Min Typ ‡ Max Units Test Conditions I N P U T S Supply Current I DD 50 mA Outputs unloaded

2 Input High Voltage - all pins

except C4i, F0i, S0-S31 VIH 0.7VDD V

3 Input Low Voltage - all pins

except C4i, F0i, S0-S31 VIL 00 . 3 V DD V

4 Input High Voltage - C4i , F0i,

VIH 2.0 V

5 Input Low Voltage - C4i , F0i,

VIL 0.8 V

6 Input Leakage Current I IL ±10 µA

O U T P U T S Output Low Current S0-S31 I OL 8m A V OL =0.4V

8 Output Low Current all outputs

IOL 8m A V OL =0.3VDD 9 Output High Current S0-S31 I OH 8m A V OH =2.4V

10 Output High Current all outputs

IOH 8m A V OH =0.7VDD

11 High Impedance Leakage I OZ 10 µA

12 Input Pin Capacitance C i 10 pF

13 Output Pin Capacitance C o 10 pF V DD =5.0V ±10 %

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 13 - ST-BUS Frame Pulse and Clock Timing † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 14 - F0o, C4o and C2o Output Clock Timing Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 C16 Clock Period t C16P 60 61 62 ns

2 C4 Clock Period t C4P 219 244 269 ns

3 C16 Pulse Width Low t C16L 25 ns

4 C16 Pulse Width High t C16H 25 ns

5 C4 Setup Time t C4S -10 25 ns

6 Frame Pulse Setup Time t FPS 52 0 0 n s

7 Frame Pulse Hold Time t FPH 5n s

Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Frame Pulse Delay t FPD 03 1 n s C L=85pF

2 C4 Clock Delay t C4D 02 8 n s C L=85pF

3 C2 Clock Delay t C2D 0n s C L=85pF

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 15 - DFPo and CFPo Output Timing Figure 15) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Data - Memory Frame Pulse

tDFPo 03 7 n s C L=85 pF

2 Connection - Memory Frame

tCFPo 03 0 n s C L=85 pF C16i CKD=0 DFPo DFPo CFPo CKD=1 DFPo DFPo CFPo tDFPo tDFPo tDFPo tDFPo tCFPD tCFPD tDFPo tDFPo tDFPo tDFPo

68 C16

71 C16 Cycles

64 C16

† Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 16 - Serial Input and Output Timing in 2 Mbit/s Mode (2/4S=0) (See Figure 16) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Serial Input Setup Time t SS 0n s

2 Serial Input Hold Time t SH 24 ns

3 Serial Output Delay

t SD ns ns ns C L=150pF C L=150pF C L=150pF C4i C16i S0i-S7i (CKD=0) S0i-S7i (CKD=1) S0o-S7o (CKD=0) S0o-S7o (CKD=1) Serial Bit Cell tSS tSH tSS tSH tSDtSD tSD Note: 1) The phase relationship of C4i and C16i depends on the user’s timing source (see Fig. 13 for device related contstraints). 2) Timing measurements for inputs are referenced to/from a low voltage of 0.8V and a high voltage of 2.0V. Measurements for outputs are referenced to/from a low voltage of 0.4V to a high voltage of 2.4V

† Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 17 - Serial Input and Output Timing in 4 Mbit/s Mode (2/4S=1) (See Figure 17) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions t SD ns ns ns C L=150pF C L=150pF C L=150pF C4i C16i S0i-S7i (CKD=0) S0i-S7i (CKD=1) S0o-S7o (CKD=0) S0o-S7o (CKD=1) tSS tSH tSS tSH tSDtSD tSD Note: 1) The phase relationship of C4i and C16i depends on the user’s timing source (see Fig. 13 for device related contstraints). Measurements for outputs are referenced to/from a low voltage of 0.4V to a high voltage of 2.4V tSD tSS tSH tSS tSH Serial Bit Cell 2) Timing measurements for inputs are referenced to/from a low voltage of 0.8V and a high voltage of 2.0V.

† Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 18 - Parallel Output Timing † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 19 - Parallel Input Timing to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Parallel Output Delay t PD 28 ns C L=85pF

2 Parallel Output Delay

tPZA 28 ns C L=85pF

3 Parallel Output Delay

tPAZ 28 ns C L=85pF Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Parallel Input Setup Time t PS 0n s

2 Parallel Input Hold Time t PH 5n s

MCB=1 P0 to P7 MCB=0 tPD tPZA tPAZ tPZA tPD90% 10% NOTE: See Figure 7 for functional timing information C16i P0 to P7 MCB=1 P0 to P7 MCB=0 NOTE: See Figure 6 for functional timing information tPS tPH tPS tPH tPS tPH tPS tPH

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 20 - OE Timing in Serial to Parallel Mode † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 21 - OE Timing in Parallel to Serial Mode Figure 20) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Parallel Output Delay

tPAZ 23 ns C L=85pF tPZA 25 ns C L=85pF (See Figure 21) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1O E Setup Time t OES 2n s 2O E Hold Time t OEH 10 ns OE P0 to P8 Output tPAZ tPZA 90% 10% C16i OE CKD=0 OE CKD=1 tOEH tOES tOEH tOES tOEH tOES tOEH tOES Frame Boundary Established by F0i

NOTES: