MT90826AL1

MT90826 ZARLINK | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 46

Technical content

Features

• 4 , 0 9 6 × 4,096 channel non-blocking switching at 8.192 or 16.384 Mbps
• Per-channel variable or constant throughput delay
• Accepts 32 ST-BUS streams of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps
• Split Rate mode provides a rate conversion option to convert data from one rate to another rate
• Automatic frame offset delay measurement for ST-BUS input streams
• Per-stream input delay programming
• Per-stream output advancement programming
• Per-channel high impedance output control
• Bit Error Monitoring on selected ST-BUS input and output channels.
• Per-channel message mode
• Connection memory block programming
• IEEE-1149.1 (JTAG) Test Port
• 3.3 V local I/O with 5 V tolerant inputs and TTL compatible outputs

Applications

• Medium switching platforms
• CTI application
• Voice/data multiplexer
• Digital cross connects
• WAN access system
• Wireless base stations August 2005

Ordering Information

MT90826AL 160 Pin MQFP Trays MT90826AG 160 Ball PBGA Trays MT90826AV 144 Ball LBGA Trays MT90826AL1 160 Pin MQFP* Trays *Pb Free Matte Tin -40°C to +85 °C MT90826 Quad Digital Switch Data Sheet Figure 1 - Functional Block Diagram Test Port STo0 STo1 STo31 STi0/FEi0 STi1/FEi1 STi31/FEi31 Parallel to Serial Converter Output MUX Microprocessor InterfaceTiming Unit Internal Registers F0i DS CS R/W A13-A0 DTA D15-D0 ODEVSS Connection Memory CLK VDD TDI TDO RESETTCK TRST Serial to Parallel Converter TMS Multiple Buffer Data Memory PLLVSSPLLVDD

Zarlink Semiconductor Inc.

Description

The MT90826 Quad Digital Switch has a non-blocking switch capacity of 4,096 x 4,096 channels at a serial bit rate The device has many features that are programmable on a per stream or per channel basis, including message mode, input offset delay and high impedance output control. The per stream input and output delay control is particularly useful for managing large multi-chip switches with a distributed backplane. Operating in Split Rate mode allows rate conversion for switching between two groups of bit rate streams.

Zarlink Semiconductor Inc.

Zarlink Semiconductor Inc.

Zarlink Semiconductor Inc. Changes Summary The following table captures the changes from the April 2005 issue. Page Item Change

26 Figure 6 “Examples for Input Offset

Delay Timing” Clarified the mid-point sampling of the 16Mbps input data. 30 Section 9.0 Initialization of the MT90826 Added the 600 µs waiting time needed for the APLL module to be stabilized before starting the next microprocessor port access cycle. Streams for ST-BUS. Clarified the 16, 8, 4 and 2 Mbps Input Data Sampling timing.

37 Figure 8 “ST-BUS Timing for Stream

rate of 16.384 Mbps” Clarified the input data sampling position at 16 Mbps data rate.

38 Figure 9 “ST-BUS Timing for Stream

rate of 8.192 Mbps when CLK =

16.384 MHz”

Added the input data sampling position at 8 Mbps data rate.

38 Figure 10 “ST-BUS Timing for Stream

rate of 4.096 Mbps when CLK = Added the input data sampling position at 4 Mbps data rate.

39 Figure 12 “ST-BUS Timing for Stream

rate of 2.048 Mbps when CLK = Added the input data sampling position at 2 Mbps data rate.

Zarlink Semiconductor Inc. Figure 2 - 160-Pin MQFP Pin Connections STo16 STo17 STo18 STo19 STo20 STo21 STo22 STo23 ODE STo24 STo25 STo26 STi0/FEi0 STi1/FEi1 STi2/FEi2 STi3/FEi3 STi4/FEi4 STi5/FEi5 STi6/FEi6 STi7/FEi7 STi8/FEi8 STi9/FEi9 STi10/FEi10 STi12/FEi12 TCK TDO A10 A11 A12 A13 STo27 STo28 STo29 STo30 STo31 STi11/FEi11 STi15/FEi15 STi14/FEi14 STi13/FEi13 TDI D10 D11 D12 D13 DTA TRST IC1 TMS

160 Pin MQFP

103109111113 959799101117 91115 93 89107 105119 135 141 143 145 127 129 131 133 149 123 147 125 121 139 137 151 171513119 25 27232119753 29 311 STi16/FEi16 STi17/FEi17 STi18/FEi18 STi19/FEi19 STi20/FEi20 VSS STi21/FEi21 STi22/FEi22 STi23/FEi23 STi24/FEi24 STi25/FEi25 STI26/FEi26 STi27/FEi27 STi28/FEi28 STi29/FEi29 STi31/FEi31 VSS VDD CLK VSS STo13 STo12 STo7 STo6 STo5 STo4 STo3 VDD VSS IC2 STo8 STo15 STo14 STo9 87 83 85 81 STo10 33 35 37 39 CS R/W DS 153 157 155 159 STo11 D14 D15 F0i PLLGND NC IC3 VDD VSS VDD VSS VSS NC NC PLLVDD VDD VDD VSS VSS VSS VSS VSS VDD VSS VDD VSS VSS VDD VSS VDD VDD VSS VDD VSS STi30/FEi30 STo2 VSS STo0 STo1 NC NC VSS VDD NC VSS NC NC NC NC VSS NC NC NC 28 mm x 28 mm Pin Pitch 0.65 mm

Zarlink Semiconductor Inc. Figure 3 - 160 Ball PBGA Pin Connections B C D E F G H J K L M N 123456789 1 0 1 1 1 2 1 3 1 - A1 corner is identified by metallized markings. A STo22STo24STo27 STi29 NCSTi31 STo30 STo31 D2 D5 D6 D10 D13 D11 D14 D12 NC D15 NC R/W NC A1DS A2 A4 A5 A6 TMS A12 A13 TDO TCK IC1 RESET IC2 IC3 CLKF0i ODENC NC STi0STi1 STi2 STi6STi7 STo4 STo2 STo5 STo6STo3 STo7STi12STi15STo16 NC A9 PLLGND STi13 A10 PLLVDD STo0 STi14 VDDVDDVDDVDDVDDGND GND NCNCVDDVDDVDDGND NC GND VDD VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND GND GND STi26 STi24 STo20 STi22 STi20 STi18 STi16 STo15 STo13 STo10 STo8 STi10 STi9 STi27 STi25 STo21 STi23 STi21 STi19 STi17 STo14 STo12 STo11 STo9 STi11 STi8 STo26 STo25 STo23 STo19 STo18 STo17 GNDGNDGNDGND GND GND GND GNDGNDGND GND STi28 NCSTi30 STi3 STo1 STi4STi5 STo28 STo29 D1 D3 D9D8 DTA CS A0 A3 A8 A7 A11 TDI TRST 23mm x 23mm TOP VIEW Ball Pitch 1.5mm

Zarlink Semiconductor Inc. Figure 4 - 144 Ball LBGA Pin Connections PINOUT DIAGRAM: (as viewed through top of package) A1 corner identified by metallized marking, mould indent, ink dot or right-angled corner 123456789 1 0 1 1 1 2 A STo23 STo20 STi21 STi20 STi17 STi16 STo14 STo13 STo11 STo9 STi11 STi9 B STo22 STo21 STi23 STi22 STi19 STi18 STo15 STo12 STo10 STo8 STI10 STi8 C STi26 STi25 STo24 STo19 STo18 STo17 STo16 STi14 STi13 STi12 STo7 STo5 D STi27 STi24 STo25 GND VDD VDD VDD STi15 GND STo2 STo6 STo4 E STi29 STi28 STo27 STo26 GND GND GND GND VDD STo3 STi7 STi6 F STi30 STi31 STo28 VDD GND GND GND GND VDD STo1 STi4 STi5 G STo30 STo31 STo29 VDD GND GND GND GND PLLVDD STo0 STi3 STi2 H D1 D2 D0 VDD GND GND GND GND PLLGND ODE STi0 STi1 J D3 D7 D4 GND DS VDD VDD VDD NC NC FOi CLK KD 5 D 1 5 D 1 1 D 1 3 C S A2 A5 A8 A9 RESET IC1 IC3 LD 6 D 8 D 9 R / W A13 A1 A4 A10 A12 TCK TDO IC2 MD 1 0 D 1 2 D 1 4 D T A A0 A3 A6 A7 A11 TMS TDI TRST

Zarlink Semiconductor Inc. Pin Description Pin # MQFP Pin # PBGA Pin # LBGA Name Description 12,22,33,54, 66,77,90,101, 112,125,136, 147,157 D5,D6,D7,D8,D9, E4,E10,F4, F10,G4,G10, H4,J4,J10,K5, K6,K7 D5,D6,D7,E9, F4,F9,G4,H4, J6,J7,J8 VDD +3.3 Volt Power Supply. 11,21,32,45, 53,60,65,71, 76,84,89,95, 100,106,111, 117,124,130, 135,141,146, 156 D4,D10,E5,E6, E7,E8,E9,F5, F9,G5,G9,H5, H9,H10,J5,J6, J7,J8,J9,K4 D4,D9,E5,E6, E7,E8,F5,F6, F7,F8,G5,G6, G7,G8,H5,H6, H7,H8,J4 Vss Ground. 34 N11 M10 TMS Test Mode Select (3.3 V Input with Internal pull-up). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. 35 M11 M11 TDI Test Serial Data In (3.3 V Input with Internal pull-up). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. 36 N12 L11 TDO Test Serial Data Out (3.3 V Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. 37 N13 L10 TCK Test Clock (5 V Tolerant Input). Provides the clock to the JTAG test logic.

38 M12 M12 TRST

Test Reset (3.3 V Input with internal pull-up). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed low on power-up, or held low, to ensure that the device is in the normal functional mode. 42 L11 K11 IC1 Internal Connection 1 (3.3 V Input with internal pull-down). Connect to V SS for normal operation. 43 M13 K10 RESET Device Reset (5 V Tolerant Input). This input (active LOW) puts the device in its reset state which clears the device internal counters and registers.

Zarlink Semiconductor Inc. 44 L12 L12 IC2 Internal Connection 2 (3.3 V Input with internal pull-down). Connect to VSS for normal operation. 46 L13 K12 IC3 Internal Connection 3 (3.3 V Input with internal pull-down). Connect to VSS for normal operation.

47 K12 J11 F0i Master Frame Pulse (5 V Tolerant

Input). This input accepts a 122 ns or 60 ns wide negative frame pulse. The CPLL bit in the control register determines the usage of the frame pulse width. See Table 6 for details. 50 K10 H9 PLLGND Phase Lock Loop Ground. 51 K9 G9 PLLVDD Phase Lock Loop Power Supply. 3.3 V

52 K13 J12 CLK

Master Clock (5 V Tolerant Input). Serial clock for shifting data in/out on the serial streams. This pin accepts a clock frequency of 8.192 MHz or 16.384 MHz. The CPLL bit in the control register determines the usage of the clock frequency. See Table 6 for details.

55 J13 H10 ODE Output Drive Enable (5 V Tolerant

Input). This is the output-enable control pin for the STo0 to STo31 serial outputs. See Table 2 for details. 67-70 78,79 82,83 91-94 102-105 113-116 126-129 137-140 H13 H12 G13 G12 F13,F12,E13,E12 B13,A13 A12,B12 C11,C10,C9,C8 A7,B7,A6,B6 A5,B5,A4,B4 A2,B2,A1,B1 E2,F2,E1,F1 H11 H12 G12 G11 F11,F12,E12,E11 B12,A12 B11,A11 C10,C9,C8,D8 A6,A5,B6,B5, A4,A3,B4,B3 D2,C2,C1,D1 E2,E1,F1,F2 STi0/FEi0, STi1/FEi1 STi2/FEi2 STi3/FEi3 STi4-7/FEi4-7 STi8-9/FEi8-9 STi10-11/FEi10-11 STi12-15/FEi12-15 STi16-19/FEi16-19 STi20-23/FEi20-23 STi24-27/FEi24-27 STi28-31/FEi28-31 Serial Input Streams 0 to 31 and Frame Evaluation Inputs 0 to 31 (5 V Tolerant Inputs). Serial data input streams. These streams may have data rates of 2.048, 4.096, 8.192 or

16.384 Mbps, depending upon the

value programmed at bits DR0 - DR2 in the control register. In the frame evaluation mode, they are used as the frame evaluation inputs. 61-64 72-75 85-88 96-99 107-110 118,119 122,123 131-134 142-145 G11,F11,E11,D11 D13,C13,D12,C12 A11,B11,A10,B10 B9,A9,B8,A8 C7,C6,C5,C4 A3,B3 D3,C3 D2,C2,C1,D1 G1,G2,H1,H2 G10,F10,D10,E10 D12,C12,D11,C11 B10,A10,B9,A9 B8,A8,A7,B7 C7,C6,C5,C4 A2,B2 B1,A1 C3,D3,E4,E3 F3,G3,G1,G2 STo0 - 3 STo4 - 7 STo8 - 11 STo12 - 15 STo16 - 19 STo20, STo21 STo22, STo23 STo24 - 27 STo28 - 31 ST-BUS Output 0 to 31 (Three-state Outputs). Serial data output streams. These streams may have data rates of 2.048, 4.096, 8.192, or 16.384 Mbps, depending upon the value programmed at bits DR0 - DR2 in the control register. Pin Description (continued) Pin # MQFP Pin # PBGA Pin # LBGA Name Description

Zarlink Semiconductor Inc.

1.0 Device Overview

The MT90826 Quad Digital Switch is capable of switching up to 4,096 × 4,096 channels. The MT90826 is designed to switch 64 Kbps PCM or N x 64 Kbps data. The device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis. The serial input streams of the MT90826 can have a bit rate of 2.048, 4.096, 8.192 or 16.384 Mbps and are arranged in 125 µs wide frames, which contain 32, 64,128 or 256 channels, respectively. The data rates on input STo0-15 may be set to 16.384 Mbps. Combinations of two bit rates, N and 2N are provided. See Table 1. By using Zarlink’s message mode capability, the micropr ocessor can access input and output timeslots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other ST- BUS devices. To correct for backplane delays, the MT90826 has a frame offset calibration function which allows users to measure the frame delay on any of the input streams, This information can then be used to program the input offset dealy for each individual stream. Refer to Table 7, 8, and 9 and Figure 6. In addition, the MT90826 allow users to advance 148 - 153 154,155 158 3 - 7 8,9 G3,J1,H3,J2,J3,K1, K2,K3 L2,M1,M2,M3,N1, N2,N3 H3,H1,H2,J1,J3,K1 L1,J2 L3,M1,K3,M2,K4 M3,K2 D0 - 5, D6, D7 D9 - 13 D14, D15 Data Bus 0 to 15 (5 V Tolerant I/O). These pins form the 16-bit data bus of the microprocessor port.

10 M4 M4 DTA

Data Transfer Acknowledgment (Three-state Output). This output pulses low from tristate to indicate that a databus transfer is complete. A pull- up resistor is required to hold a HIGH level when the pin is tristated.

15 N5 J5 DS

Data Strobe (5 V Tolerant Input). This active low input works in conjunction with CS to enable the read and write operations. 14 N4 L4 R/W Read/Write (5 V Tolerant Input). This input controls the direction of the data bus lines (D0-D15) during a microprocessor access.

13 M5 K5 CS

Chip Select (5 V Tolerant Input). Active low input used by a microprocessor to activate the microprocessor port. 16 - 20 23 - 31 M6,N6,N7,M7,N8 N9,N10,M8,M9,L7 L8,M10,L9,L10 M5,L6,K6,M6,L7, K7,M7,M8,K8,K9, L8,M9,L9,L5 A0 - A4 A5 - A13 Address 0 to 13 (5 V Tolerant Input). These lines provide the A0 - A13 address lines when accessing the internal registers or memories. 1,2,39,40,41,48, 49,80,81,120, 121,159,160 E3,F3,H11,J11, J12,K8,K11, L3,L4,L5,L6. J9,J10 NC No Connect. These pins have to be left unconnected. Pin Description (continued) Pin # MQFP Pin # PBGA Pin # LBGA Name Description

Zarlink Semiconductor Inc. the output data position up to 45ns to compensate for the output delay caused by excessive output loading conditions. See Figure 7 “Examples for Frame Output Offset Timing”. The microport interface is compatible with Motorola non-multiplexed buses. Connection memory locations may be directly written to or read from; data memo ry locations may be directly read from. A DTA signal is provided to hold the bus until the asynchronous microport operation is queued into the device. Serial Interface Mode Input Stream Input Data Rate Output Stream Output Data Rate

8 Mbps STi0-31 8 Mbps STo0-31 8 Mbps

16 Mbps STi0-15 16 Mbps STo0-15 16 Mbps

4 Mbps and 8 Mbps STi0-15 4 Mbps STo0-15 4 Mbps

STi15-31 8 Mbps STo16-31 8 Mbps

16 Mbps and 8 Mbps STi0-11 16 Mbps STo0-11 16 Mbps

STi12-19 8 Mbps STo12-19 8 Mbps

4 Mbps STi0-31 4 Mbps STo0-31 4 Mbps

2 Mbps and 4 Mbps STi0-15 2 Mbps STo0-15 2 Mbps

STi16-31 4 Mbps STo16-31 4 Mbps

2 Mbps STi0-31 2 Mbps STo0-31 2 Mbps

Table 1 - Stream Usage under Various Operation Modes ODE pin OSB bit in Control register OE bit in Connection Memory ST-BUS Output Driver

00 X H i g h - Z

Table 2 - Output High Impedance Control A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Location 0 0 0 0 0000000000 C o n t r o l R e g i s t e r , C R 0 0 0 0 0000000001 F r a m e A l i g n m e n t R e g i s t e r , F A R 0 0 0 0 0000000010 I n p u t O f f s e t S e l e c t i o n R e g i s t e r 0 , D O S 0 0 0 0 0 0000000011 I n p u t O f f s e t S e l e c t i o n R e g i s t e r 1 , D O S 1 0 0 0 0 0000000100 I n p u t O f f s e t S e l e c t i o n R e g i s t e r 2 , D O S 2 0 0 0 0 0000000101 I n p u t O f f s e t S e l e c t i o n R e g i s t e r 3 , D O S 3 0 0 0 0 0000000110 I n p u t O f f s e t S e l e c t i o n R e g i s t e r 4 , D O S 4 Table 3 - Address Map for Registers (A13 = 0)

Zarlink Semiconductor Inc.

2.0 Functional Description

A functional Block Diagram of the MT90826 is shown in Figure 1.

2.1 Data and Connection Memory

For all data rates, the received serial data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the data memory. Depending upon the selected operation programmed in the control register, the usable data memory may be as large as 4,096 byte s. The sequential addressing of the data memory is performed by an internal counter, which is reset by the input 8 kHz frame pulse (F0i) to mark the frame boundaries of the incoming serial data streams. Data to be output on the serial streams may come from either the data memory or connection memory. Locations in the connection memory are associated with particular ST -BUS output channels. When a channel is due to be transmitted on an ST-BUS output, the data for this c hannel can be switched either from an ST-BUS input in connection mode, or from the lower half of the connection memory in message mode. Data destined for a particular channel on a serial output stream is read from the data memory or connection memory during the previous channel timeslot. This allows enough time for memory access and parallel-to-serial conversion.

2.2 Connection and Message Modes

In the connection mode, the addresses of the input source data for all output channels are stored in the connection memory. The connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto an ST-BUS output stream. By having several output channels connected to the same input source channel, data can be broadcast from one input channel to several output channels. In message mode, the microprocessor writes data to the connection memory locations corresponding to the output stream and channel number. The lower half (8 least si gnificant bits) of the c onnection memory content is 0 0 0 0 0000000111 I n p u t O f f s e t S e l e c t i o n R e g i s t e r 5 , D O S 5 0 0 0 0 0000001000 I n p u t O f f s e t S e l e c t i o n R e g i s t e r 6 , D O S 6 0 0 0 0 0000001001 I n p u t O f f s e t S e l e c t i o n R e g i s t e r 7 , D O S 7 0 0 0 0 0000001010 F r a m e O u t p u t O f f s e t R e g i s t e r , F O R 0 0 0 0 0 0000001011 F r a m e O u t p u t O f f s e t R e g i s t e r , F O R 1 0 0 0 0 0000001100 F r a m e O u t p u t O f f s e t R e g i s t e r , F O R 2 0 0 0 0 0000001101 F r a m e O u t p u t O f f s e t R e g i s t e r , F O R 3 0 0 0 0 0000001110 U n u s e d 0 0 0 0 0000001111 U n u s e d 0 0 0 0 0000010000 U n u s e d 0 0 0 0 0000010001 B i t E r r o r I n p u t S e l e c t i o n R e g i s t e r , B I S R 0 0 0 0 0000010010 B i t E r r o r C o u n t R e g i s t e r , B E C R A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Location Table 3 - Address Map for Registers (A13 = 0) (continued)

Zarlink Semiconductor Inc. transferred directly to the parallel-to-serial converter. This data will be output on the ST-BUS streams in every frame until the data is changed by the microprocessor. The three most significant bits of the connection memo ry controls the following for an output channel: message or connection mode, constant or variable delay mode, enable s/tristate the ST-BUS output drivers and bit error test pattern enable. If an output channel is set to a high-impedance state by setting the OE bit to zero in the connection memory, the ST-BUS output will be in a high impedance state for the duration of that channel. In addition to the per- channel control, all channels on the ST-BUS outputs can be placed in a high impedance state by pulling the ODE input pin low and programming the output stand by (OSB) bit in the control register to low. This action overrides the individual per-channel programming by the connection memory bits. See Table 2 for detail. The connection memory data can be accessed via the micr oprocessor interface through the D0 to D15 pins. The addressing of the device internal r egisters, data and connection memories is performed through the address input pins and the Memory Select (MS) bit of the control register.

2.3 Clock Timing Requirements

The master clock (CLK) frequency must be either at 8.192 MHz or 16. 384 MHz for serial data rate of 2.048, 4.096, 8.192 and 16.384 Mbps; see Table 6 for the selections of the master clock frequency.

3.0 Switching Configurations

The MT90826 maximum non-blocking switchin g configurations is determined by the data rates selected for the serial inputs and outputs. The switching configuration is selected by three DR bits in the control register. See Table 5 and Table 6.

8 Mbps mode (DR2=0, DR1=0, DR0=0)

When the 8 Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 128 64 Kbps channels. This mode allows a maximum non-bl ocking capacity of 4,096 x 4,096 channels. Table 1 summarizes the switching configurations and the relation ship between different serial data rates and the master clock frequencies.

16 Mbps mode (DR2=0, DR1=0, DR0 =1)

When the 16 Mbps mode is selected, the device is configur ed with 16-input/16-output data streams each having 256 64 Kbps channels. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels.

4 Mbps and 8 Mbps mode (DR2=0, DR1=1, DR0=0)

When the 4 Mbps and 8 Mbps mode is selected, the device is configured with 32-input /32-output data streams. STi0-15/STo0-15 have a data rate of 4 Mbps and STi16-31/STo16-31 have a data rate of 8 Mbps. This mode allows a maximum non-blocking capacity of 3,072 x 3,072 channels. The MT90826 is capable of rate conversion, allowing 4 Mbps input to be converted to 8 Mbps output and vice versa.

16 Mbps and 8 Mbps mode (DR2=0, DR1=1, DR0=1)

When the 16 Mbps and 8 Mbps mode is selected, the device is configured with 20-in put/20-output data streams. STi0-11/STo0-11 have a data rate of 16 Mbps and STi 12-19/STo12-19 have a data rate of 8 Mbps. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels. The MT90826 is capable of rate conversion, allowing 16 Mbps input to be converted to 8 Mbps output and vice versa.

4 Mbps mode (DR2=1, DR1=0, DR0=0)

When the 4 Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 64 64 Kbps channels. This mode allows a maximum non-blocking capacity of 2,048 x 2,048 channels.

Zarlink Semiconductor Inc.

2 Mbps and 4 Mbps mode (DR2=1, DR1=0, DR0=1)

When the 2 Mbps and 4 Mbps mode is selected, the device is configured with 32-input/32-output data streams. STi0-15/STo0-15 have a data rate of 2 Mbps and STi16-31/STo16-31 have a data rate of 4 Mbps. This mode allows a maximum non-blocking capacity of 1,536 x 1,536 channels. The MT90826 is capable of rate conversion, allowing 2 Mbps input to be converted to 4 Mbps output and vice versa.

2 Mbps mode

(DR2=1, DR1=1, DR0 =0) When the 2 Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 32 64 Kbps channels. This mode allows a maximum non-blocking capacity of 1,024 x 1,024 channels.

3.1 Serial Input Fr ame Alignment Evaluation

The MT90826 provides the frame evaluation inputs, FEi0 to FEi31, to determine different data input delays with respect to the frame pulse F0i. By using the frame evaluation input select bits (FE0 to FE4) of the frame alignment register (FAR), users can select one of the thirty-two frame evaluation inputs for the frame alignment measurement. The internal master clock, which has a fixed relationship with the CLK and F0i depending upon the mode of operation, is used as the reference timing signal to det ermine the input frame delays. See Figure 5 for the signal alignments between the internal and the external master clocks. A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the evaluation starts when the SFE bit in the control register is changed from low to high. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 9 of the FAR register. The SFE bit must be set to zero before a new measurement cycle started. The falling edge of the frame measurem ent signal (FEi) is evaluated agains t the falling edge of the frame pulse (F0i). See Table 7 for the description of the frame alignment register.

3.2 Input Frame Offset Selection

Input frame offset selection allows the channel alignment of individual input streams, which operate at 4.096 Mbps, 8.192 Mbps or 16.384 Mbps, to be shifted against the input frame pulse (F0i ). The input offset selection is not available for streams operated at 2. 048 Mbps. This feature is useful in compensating for variable path delays caused by serial backplanes of vari able lengths, which may be implemented in large centralized and distributed switching systems. Each input stream has its own delay offset value programmed by the input delay offset registers. Each delay offset register can control 4 input streams. There are eight delay offset regist ers (DOS0 to DOS7) to control 32 input streams. Possible adjustment can range up to +4.5 internal master clock periods forwar d with resolution of 0.5 internal master clock period. See Table 8 and Table 9 for frame input delay offset programming.

3.3 Output Advance Offset Selection

The MT90826 allows users to advance indi vidual output streams up to 45 ns with a resolution of 15 ns when the device is in 8 Mbps, 16 Mbps, 4 and 8 Mbps or 16 and 8 M bps mode. The output delay adjustment is useful in compensating for variable output delays caused by vari ous output loading conditi ons. The frame output offset registers (FOR0 & FOR3) control the output offset delays for each output streams via the programming of the OFn bits. See Table 10 and Table 11 for the frame output offset programming.

Zarlink Semiconductor Inc.

3.4 Memory Block Programming

The MT90826 provides users with the capability of initia lizing the entire connection memory block in two frames. Bits 13 to 15 of every connection memory location will be programmed with the pattern stored in bits 13 to 15 of the control register. The block programming mode is enabled by setting the memo ry block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the control register is set to high, the block programming data will be loaded into the bits 13 to 15 of every c onnection memory location. The other connection memory bits (bit 0 to 12) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero.

3.5 Bit Error Rate Monitoring

The MT90826 allows users to perform bit error rate monitoring by sending a pseudo random pattern to a selected ST-BUS output channel and receiving the pattern from a selected ST-BUS input channel. The pseudo random pattern is internally generated by the device with the polynomial of 2 15 -1. Users can select the pseudo random pattern to be pr esented on a ST-BUS channel by programming the TM0 and TM1 bits in the connection memory. When TM0 and TM1 bits are high, the pseudo random pattern is output to the selected ST-BUS output channel. The pseudo random pattern is then received by a ST-BUS input channel which is selected using the BSA and BCA bits in the bit error rate input selection register (BISR). An internal bit error counter keeps track of the error counts which is then stored in the bit error count register (BECR). The bit error test is enabled and disabl ed by the SBER bit in the control register. Setting the bit from zero to one initiates the bit error test and enables the internal bit error counter. When t he bit is programmed from one to zero, A13 Stream Address (ST0-31) Channel Address (Ch0-255) A12 A11 A10 A9 A8 Stream Location A7 A6 A5 A4 A3 A2 A1 A0 Channel Location Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 Stream 8 Stream 22 Stream 23 Stream 24 Stream 25 Stream 26 Stream 27 Stream 28 Stream 29 Stream 30 Stream 31 Ch 0 Ch 1 Ch 30 Ch 31 (Note 2) Ch 32 Ch 33 Ch 62 Ch 63 (Note 3) Ch 64 Ch 65 Ch 126 Ch 127 (Note 4) Ch 128 Ch 129 Ch 254 Ch 255 (Note 5) 1. Bit A13 must be high for access to data and connection memory positions. Bit A13 must be low for access to registers. 2. Channels 0 to 31 are used when serial stream is at 2Mbps. 3. Channels 0 to 63 are used when serial stream is at 4Mbps 4. Channels 0 to 127 are used when serial stream is at 8Mbps 5. Channels 0 to 255 are used when serial stream is at 16Mbps Table 4 - Address Map for Memory Locations (A13 = 1)

Zarlink Semiconductor Inc. the device stops the bit error rate test and the internal bit error counter and transfers the error counts to the bit error count register. In the control register, a zero to one transition of the CBER bit resets the bit error count register and the internal bit error counter. The MT90826 does not recognize an input of all 1s as an er ror. If all 1s are being fed into the input stream and channel, the BERT on chip BECR does not increment. This test is performed by sending defined data through the message mode to ensure there is proper connectivity, and then running the BER test normally.

4.0 Delay Through the MT90826

The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform timeslot in terchange functions with different throughput delay capabilities on the per-channel basis. For voice application, select variabl e throughput delay to ensure minimum delay between input and output data. In wideband data appli cations, select constant throughput delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the type of throughput delay selected by the TM bits in the connection memory.

4.1 Variable Delay Mode (TM1=0, TM0=0)

The delay in this mode is dependent only on the co mbination of source and destination channels and is independent of input and output stream s. The delay through the switch can vary from 3 channels to 1 frame + 3 channels. The Variable delay is only available for odd num ber output streams but not for the even number output streams. Avoid programming the TM0 and TM1 bits to ze ro in the connection memory when the destination output streams are STo0, 2, 4, ..., 28 and 30.

4.2 Constant Delay Mode (TM1=1, TM0=0)

In this mode, frame integrity is maintained in all switch ing configurations by making use of a multiple data memory buffer. The delay through the switch is always two fr ames. The constant delay mode is available for all output streams.

5.0 Microprocessor Interface

The MT90826 provides a parallel microprocessor interface for non-multiplexed bus stru ctures. This interface is compatible with Motorola non-multiplexed buses. The required microprocessor signals are the 16-bit data bus (D0- D15), 14-bit address bus (A0-A13) and 4 control lines (CS , DS, R/W and DTA). See Figure 16 for Motorola non- multiplexed microport timing. The MT90826 microport provides access to the internal re gisters, connection and data memories. All locations provide read/write access except for the data memory and BECR registers which are read only. For data memory read operations, two consecutive microprocessor cycles are required. The read address (A0-A13) should remain the same for the two consecutive read cycles. The data memory content from the first read cycle should be ignored.

Zarlink Semiconductor Inc. Bit Name Description 15 - 13 BPD2-0 Block Programming Data. These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature is activated. After the MBP bit is set to 1 and the BPE bit is set to 1, the contents of the bits BPD2- 0 are loaded into bit 15 to bit 13 of the connection memory. Bit 12 to bit 0 of the connection memory are set to 0. 12 Unused Must be zero for normal operation. 11 CPLL PLL Input Frequency Select. When zero or one, the CLK input is 16.384 MHz and the F0i input is 60 ns wide. When one, the CLK input is 8.192 MHz and the F0i input is 122 ns wide. See Table 6 for the usage of the clock frequency. 10 CBER Clear Bit Error Rate Register. A zero to one transition in this bit resets the internal bit error counter and the bit error count register to zero. 9 SBER Start Bit Error Rate Test. A zero to one transition in this bit starts the bit error rate test. The bit error test result is kept in the bit error count register. A one to zero transition stops the bit error rate test and the internal bit error counter. 8S F E Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the frame alignement (FAR) register changes from zero to one, the evaluation procedure stops. To start another frame evaluation cycle, set this bit to zero. 7 Unused Must be zero for normal operation. 6 BPE Begin Block programming Enable. A zero to one transition of this bit enables the memory block programming function. The BPE and BPD2-0 bits have to be defined in the same write operation. Once the BPE bit is set high, the device requires two frames to complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort the programming operation. When BPE = 1, the other bits in the control register must not be changed for two frames to ensure proper operation. 5M B P Memory Block Program. When 1, the connection memory block programming feature is ready to program Bit13 to Bit15 of the connection memory. When 0, feature is disabled. Table 5 - Control Register Bits Read/Write Address: 0000H, Reset Value: 0000 H. 765432108910111213 DR0DR1BPE 1415 SFE 0 OSB MBP MSSBERBPD2 BPD1 BPD0 CBER 0 DR2CPLL

Zarlink Semiconductor Inc. 4M S Memory Select. When 0, connection memory is selected for read or write operations. When 1, the data memory is selected for read operations and connection memory is selected for write operations. (No microprocessor write operation is allowed for the data memory.) For data memory read operations, two consecutive microprocessor cycles are required. The read address should remain the same for the two consecutive read cycles. The data memory content from the first read cycle should be ignored. The correct data memory content will be presented to the data bus on the second read cycle. 3O S B Output Stand By. This bit controls the device output drivers. OSB bit ODE pin OE bit STo0 - 31 0 1 1 Enable 1 0 1 Enable 1 1 1 Enable 0 0 X High impedance state X X 0 Per-channel high impedance 2 - 0 DR2-0 Data Rate Select. Input/Output data rate selection. See next table (Table 6) for detailed programming. DR2 DR1 DR0 Serial Interface Mode CLK (CPLL=0) CLK (CPLL=1) 00 0 8 M b p s 16.384 MHz 16.384 MHz 00 1 1 6 M b p s 0 1 0 4 and 8 Mbps 0 1 1 16 and 8 Mbps 1 0 0 4 Mbps 16.384 MHz 8.192 MHz 1 0 1 2 and 4 Mbps 1 1 0 2 Mbps 16.384 MHz 8.192 MHz Table 6 - Serial Data Rate Selections and External Clock Rates Bit Name Description Table 5 - Control Register Bits (continued) Read/Write Address: 0000H, Reset Value: 0000 H. 765432108910111213 DR0DR1BPE 1415 SFE 0 OSB MBP MSSBERBPD2 BPD1 BPD0 CBER 0 DR2CPLL

Zarlink Semiconductor Inc. Bit Name Description 15 - 11 FE4-0 Frame Evaluation Input Select. The binary value expressed in these bits refers to the frame evaluation inputs, FEi0 to FEi31. 10 CFE Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed and FD9 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when SFE bit in the control register is changed from 1 to 0. 9F D 9 Frame Delay Bit 9. The falling edge of FEi input is sampled during the internal master clock high phase (FD9 = 1) or during the low phase (FD9 = 0). This bit allows the measurement resolution to 1/2 internal master clock cycle. See Figure 5 for clock signal alignment. Internal Master Clock Operation Mode C8i 2 Mbps C16i 4 Mbps, 2&4 Mbps C32i 8 Mbps, 16 Mbps, 4&8 Mbps, 16&8 Mbps 8 - 0 FD8-0 Frame Delay Bits. The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the SFE bit of the control register changes from 1 to 0. (FD8 = MSB, FD0 = LSB) Table 7 - Frame Alignment (FAR) Register Bits Read/Write Address: 0001H, Reset Value: 0000 H. 765432108910111213 FD0FD1FD2FD3FD4FD5FD6FD7FD8FD9CFEFE0FE1FE2FE3FE4 1415

Zarlink Semiconductor Inc. Figure 5 - Example for Frame Alignment Measurement F0i FEi Input (FD9 = 0, sample at internal C32i low phase) Offset Value (FD[8:0] = 06H, frame offset of six C32i clock cycles) 10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Internal CLK Frame Boundary at 32 MHz master clock For 8 Mbps, 16 Mbps, 4&8 Mbps and 16&8 Mbps modes F0i FEi Input (FD9 = 0, sample at internal C16i low phase) Offset Value (FD[8:0] = 03H, frame offset of three C16i clock cycles) 102 3 4 5 6 7 Internal CLK at 16 MHz master clock For 4 Mbps and 2&4 Mbps modes F0i FEi Input (FD9 = 1, sample at internal C8i high phase) Offset Value (FD[8:0] = 02H, frame offset of two C8i clock cycles) 102 3 4 Internal CLK at 8 MHz master clock For 2 Mbps mode (16.384 MHz) (16.384 MHz) (16.384 MHz)

Zarlink Semiconductor Inc. Name (Note 1) Description IFn3-0 Input Offset Bits 3,2,1 & 0. These four bits define how long the serial interface receiver takes to recognize and store bit 0 from the STi pin: i.e., to start a new frame. The input frame offset can be selected to +2.25 external clock periods (or 4.50 internal clock cycles) from the point where the external frame pulse input signal is applied to the F0i inputs of the device. See Table 9. When the STi pin has a stream rate of 2.048 Mbps, the input offset cannot be adjusted and the input offset bits have to be set to zero. Table 8 - Frame Delay Offset Register (DOS) Bits Read/Write Address: 02 H for DOS0 register, 03 H for DOS1 register, 04H for DOS2 register, 05 H for DOS3 register, 06H for DOS4 register, 07 H for DOS5 register, 08H for DOS6 register, 09 H for DOS7 register, Reset value: 0000 H for all DOS registers. 765432108910111213 IF00IF01IF02 1415 IF10IF11IF12IF20IF21IF22IF30IF31IF32IF33 DOS0 register DOS1 register IF40IF41IF42IF50IF51IF52IF60IF61IF62IF70IF71IF72IF73 DOS2 register IF80IF81IF82IF90IF91IF92IF100IF101IF102IF110IF111IF112 DOS3 register IF120IF121IF122IF130IF131IF132IF140IF141IF142IF150IF151IF152 DOS4 register IF160IF161IF162IF170IF171IF172IF180IF181IF182IF190IF191IF192 DOS5 register IF200IF201IF202IF210IF211IF212IF220IF221IF222IF230IF231IF232 DOS6 register IF240IF241IF242IF250IF251IF252IF260IF261IF262IF270IF271IF272 DOS7 register IF280IF281IF282IF290IF291IF292IF300IF301IF302IF310IF311IF312 IF03IF13IF23 IF43IF53IF63 IF83IF93IF103IF113 IF123IF133IF153 IF143 IF163IF173IF183IF193 IF203IF213IF223IF233 IF243IF253IF263IF273 IF283IF293IF303IF313

Zarlink Semiconductor Inc. Note 1: n denotes a STi stream number from 0 to 31. Name (Note 1) Description Table 8 - Frame Delay Offset Register (DOS) Bits (continued) Read/Write Address: 02 H for DOS0 register, 03 H for DOS1 register, 04H for DOS2 register, 05 H for DOS3 register, 06H for DOS4 register, 07 H for DOS5 register, 08H for DOS6 register, 09 H for DOS7 register, Reset value: 0000 H for all DOS registers. 765432108910111213 IF00IF01IF02 1415 IF10IF11IF12IF20IF21IF22IF30IF31IF32IF33 DOS0 register DOS1 register IF40IF41IF42IF50IF51IF52IF60IF61IF62IF70IF71IF72IF73 DOS2 register IF80IF81IF82IF90IF91IF92IF100IF101IF102IF110IF111IF112 DOS3 register IF120IF121IF122IF130IF131IF132IF140IF141IF142IF150IF151IF152 DOS4 register IF160IF161IF162IF170IF171IF172IF180IF181IF182IF190IF191IF192 DOS5 register IF200IF201IF202IF210IF211IF212IF220IF221IF222IF230IF231IF232 DOS6 register IF240IF241IF242IF250IF251IF252IF260IF261IF262IF270IF271IF272 DOS7 register IF280IF281IF282IF290IF291IF292IF300IF301IF302IF310IF311IF312 IF03IF13IF23 IF43IF53IF63 IF83IF93IF103IF113 IF123IF133IF153 IF143 IF163IF173IF183IF193 IF203IF213IF223IF233 IF243IF253IF263IF273 IF283IF293IF303IF313

Zarlink Semiconductor Inc. Input Stream Offset Measurement Result from Frame Delay Bits Corresponding Input Offset Bits FD9 FD2 FD1 FD0 IFn3 IFn2 IFn1 IFn0 No internal master clock shift (Default) 1 0 0 0 0000 + 0.5 internal master clock shift 0 0 0 0 0 0 0 1 + 1.0 internal master clock shift 1 0 0 1 0 0 1 0 + 1.5 internal master clock shift 0 0 0 1 0 0 1 1 + 2.0 internal master clock shift 1 0 1 0 0 1 0 0 + 2.5 internal master clock shift 0 0 1 0 0 1 0 1 + 3.0 internal master clock shift 1 0 1 1 0 1 1 0 + 3.5 internal master clock shift 0 0 1 1 0 1 1 1 + 4.0 internal master clock shift 1 1 0 0 1 0 0 0 + 4.5 internal master clock shift 0 1 0 0 1 0 0 1 Table 9 - Frame delay Bits (FD9, FD2-0) and Input Offset Bits (IFn3-0)

Zarlink Semiconductor Inc. Figure 6 - Examples for Input Offset Delay Timing F0i CLK 8Mbps STi Stream 8Mbps STi Stream IFn=0000 IFn=0100 Bit 7 Bit 7 denotes the 1/2 point of the 16M bps bit cell (16.384 MHz) Internal at 32 MHz master clock F0i CLK 16Mbps STi Stream 16Mbps STi Stream IFn=0000 IFn=0010 Bit 7 Bit 7 (16.384 MHz) Internal at 32 MHz master clock denotes the 3/4 point of the 8M bps bit cell

Zarlink Semiconductor Inc. Name (Note 1) Description OFn1, OFn0 (n = 0 to 31) Output Offset Bits 1 - 0. These two bits define how soon the serial interface transmitter output the bit 0 from the STo pin. The output stream offset can be selected to -45 ns from the point where the external frame pulse input signal is applied to the F0i inputs of the device. See Table 11 and Figure 6. Table 10 - Frame Output Offset (FOR) Register Bits Corresponding Output Offset Bits Output Stream Offset for

8 Mbps, 16 Mbps, 4&8 Mbps and 16&8 Mbps modes

(Not available for 2 Mbps, 4 Mbps and 2&4 Mbps modes)OFn1 OFn0 00 0 n s 01 - 1 5 n s 1 0 -30 ns 11 - 4 5 n s Table 11 - Output Offset Bits (FD9, FD2-0) Read/Write Address: 000A H for FOR0 register, 000BH for FOR1 register, 000CH for FOR2 register, 000DH for FOR3 register, Reset value: 0000 H for all FOR registers. 765432108910111213 OF00OF01OF10OF11 1415 OF20OF21OF30OF31OF40OF41OF50OF51OF60OF61OF70OF71 FOR0 register FOR1 register OF80OF81OF90OF91OF100OF101OF110OF111OF120OF121OF130OF131OF140OF141OF150OF151 OF160OF161OF170O171OF180OF181OF190OF191OF200OF201OF210OF211OF220OF221OF230OF231 FOR2 register FOR3 register OF240OF241OF250OF251OF260OF261OF270OF271OF280OF281OF290OF291OF300OF301OF310OF311

Zarlink Semiconductor Inc. Figure 7 - Examples for Frame Output Offset Timing The correct data memory content will be presented to the data bus (D0-D15) on the second read cycle. Bit Name Description 12 - 8 BSA4 - BSA0 BER Input Stream Address Bits. The number expressed in binary notation on these bits refers to the input data stream which receives the pseudo random pattern. 7 - 0 BCA7 - BCA0 BER Input Channel Address Bits. The number expressed in binary notation on these bits refers to the input channel which receives the pseudo random pattern. Table 12 - Bit Error Input Selection (BISR) Register Bits Bit Name Description 15 - 0 BER15 - BER0 Bit Error Rate Count Bits. The number expressed in binary notation on these bits refers to the bit error counts. The register content can be cleared by programming the CBER bit in the control register from zero to one. Table 13 - Bit Error Count (BECR) Register Bits F0i CLK STo Stream STo Stream offset=00, (0ns) offset=01, (-15ns) Bit 7 Bit 7 denotes the starting point of the bit cell (16.384MHz) Read/Write Address: 0011 H for BISR register, Reset value: 0000 H 765432108910111213 BCA0BCA1BCA2BCA3 1415 BCA4BCA5BCA6BCA7BSA0BSA1BSA2BSA3BSA4000 Read Address: 0012 H for BECR register, 7654321089101112131415 BER0BER1BER2BER3BER4BER5BER6BER7BER8BER9BER10BER11BER12BER13BER14BER15

Zarlink Semiconductor Inc.

6.0 Memory Mapping

The address bus on the microprocessor interface select s the internal registers and memories of the MT90826. If the A13 address input is low, then the registers are addressed by A12 to A0 according to Table 3. If the A13 is high, the remaining addr ess input lines are used to select location in the data or connection memory depending upon MS bit in the control register. For data memory reads, the serial inputs are selected. For connection memory writes, the serial outputs are sele cted. The destination stream address bits and channel address bits are defined by A12 to A8 and A7 to A0 respectively. See Table 4 for the memory address mapping. The control register controls all the major functions of the device. It selects the in ternal memory locations that specify the input and output channels selected for switch ing and should be programmed immediately after system power-up to establish the desired switching configuration as explained in the Switching Configurations sections. The data in the control register consists of the bl ock programming (BPD0-2), the DPLL control (CPLL), the clear BER test (CBER), the start BER test (SBER), the star t frame evaluation (SFE), the block programming enable (BPE), the memory block prog ramming bit (MBP), the memory select bits (MS), the output stand by bit (OSB) and the data rate selection (DR0-2) bits. See Table 5 for the description of the control register bits.

7.0 Connection Memory Control

The connection memory controls the switching configuration of the device. Locations of the connection memory are associated with particular STo output streams. The TM0 and TM1 bits of each connection memory locati on allows the selection of Variable throughput delay, Constant throughput delay, Message or Bit error test mode for all STo channels. When the variable or constant throughput delay mode is selected, (TM1=0/1, TM0=0), the contents of the stream address bit (SAB) and the channel address bit (CAB) of th e connection memory defines the source information (stream and channel) of the timeslot that will be switched to the STo streams. When the message mode is selected, (TM1=0, TM0=1) , onl y the lower half byte (8 leas t significant bits) of the connection memory is transferred to the associated STo output channel. When the bit error test mo de is selected, (TM1=1, TM 0=1), the pseudo random patte rn will be output on the associated STo output channel. See Table 14 for the description of the connection memory bits.

8.0 DTA Data Transfer Acknowledgment Pin

The DTA pin is driven LOW by internal logic, to indicate to the CPU that a data bus transfer is complete. When the read or write cycle ends, this pin changes to the high-impedance state.

Zarlink Semiconductor Inc.

9.0 Initialization of the MT90826

During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90826 is in the normal functional mode. A 5 K pull-dow n resistor can be connected to the TRST pin so that the device will not enter the JTAG test mode during power up. An external RC network with a time constant of five ti mes the power supply rise time should be connected to the RESET pin to ensure that the device is properly reset after power up. After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after power up to keep all serial outputs in a high impedance stat e until the microprocessor ha s initialized the switching matrix. This procedure prevents two serial outputs from driving the same stream simultaneously. Wait for 600 µs for the APLL module to be stabilized before starting the microprocessor initialization routine. During the microprocessor initializati on routine, the microprocessor should program the desired active paths through the switch. Users can also cons ider using the memory block programm ing feature to quickly initialize the OE, TM0 and TM1 bits in the connection memory. When this process is comp lete, the microprocessor controlling the matrices can either bring the ODE pin high or enable the OSB bit in control regi ster to relinquish the high impedance state control.

10.0 JTAG Support

The MT90826 JTAG interface conforms to the Boundary-Scan standard I EEE1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The ope ration of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller.

10.1 Test Access Port (TAP)

The Test Access Port (TAP) provides access to the many test functions of the MT90826. It consists of three input pins and one output pin. The following pins are from the TAP.

• Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic.
• Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising e dge of the TCK pulse. This pin is internally pulled to Vdd when it is not driven from an external source.
• Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to th e TMS input. Both registers are described in a subsequent section. The received input data is samp led at the rising edge of TCK pulses. This pin is internally pulled to Vdd when it is not driven from an external source.
• Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towa rds the TDO. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state.
• Test Reset (TRST ) Resets the JTAG scan structure. This pin is internally pulled to VDD.

Zarlink Semiconductor Inc.

10.2 Instruction Register

In accordance with the IEEE 1149.1 standard, the MT90 826 uses public instructions. The JTAG Interface contains a three-bit instruction r egister. Instructions are serially loaded into th e instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is curr ent, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. Test Data Register As specified in IEEE 1149.1, the MT90826 JTAG Interface contains three test data registers:

• The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the MT90826 core logic.
• The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO.
• The Device Identification Register The device identification register is a 32-bit register with the register contain of: The LSB bit in the device identification register is the first bit clock out. The MT90826 scan register contains 165 bits. MSB LSB 0000 0000 1000 0010 0110 0001 0100 1011

Zarlink Semiconductor Inc. Device Pin Boundary Scan Bit 0 to Bit 165 Tri-state Control Output Scan Cell Input Scan Cell F0i CLK ODE STi0 STi1 STi2 STi3 STo0 STo1 STo2 STo3 STi4 STi5 STi6 STi7 STo4 STo5 STo6 STo7 STi8 STi9 STi10 STi11 STo8 STo9 STo10 STo11 STi12 STi13 STi14 STi15 STo12 STo13 STo14 STo15 STi16 STi17 STi18 STi19 STo16 STo17 STo18 STo19 STi20 STi21 STi22 STi23 STo20 STo21 STo22 STo23 STi24 STi25 STi26 STi27 STo24 STo25 STo26 STo27

Zarlink Semiconductor Inc. Note 1: DTA is an open drain output and it requires a pull-up resistor. Safe for DTA = 0. DTA cell = 1 will produce active LOW. STi28 STi29 STi30 STi31 STo28 ST029 ST030 STo31 D10 D11 D12 D13 D14 D15 102 105 108 111 114 117 120 123 126 129 132 135 138 141 144 100 103 106 109 112 115 118 121 124 127 130 133 136 139 142 145 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 DTA CS R/W DS 147 147 148 149 150 A10 A11 A12 A13 RESETb 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 Device Pin Boundary Scan Bit 0 to Bit 165 Tri-state Control Output Scan Cell Input Scan Cell

Zarlink Semiconductor Inc. Bit Name Description 15-14 TM1-0 Mode Select Bits. TM1 TM0 Mode Selection 0 0 Variable Throughput Delay mode (Note 1) 1 0 Constant Throughput Delay mode (Note 2) 0 1 Message mode; the contents of the connection memory are output on the corresponding output channel and stream. Only the lower byte (bit 7 - bit 0) will be output to the ST-BUS output pins. 1 1 Bit Error Test mode; the pseudo random test pattern will be output on the output channel and stream associated with this location. 13 OE Output Enable. This bit enables the drivers of STo pins on a per-channel basis. When 1, the STo output driver functions normally. When 0, the STo output driver is in a high-impedance state. 12-8 SAB4-0 Source Stream Address Bits. The binary value is the number of the data stream for the source of the connection. 7-0 CAB7-0 Source Channel Address Bits. The binary value is the number of the channel for the source of the connection. When the message mode is enabled, these entire 8 bits are output on the output channel and stream associated with this location. Note 1: The Variable delay is only available for odd number output streams but not for the even number output streams. Avoid programming the TM0 and TM1 bits to zero in the connection memory when the destination output streams are STo0, 2, 4, ... , 28 and 30. Note 2: The constant delay mode is available for all output streams. Table 14 - Connection Memory Bits Data Rate SAB4 to SAB0 Bits Used to Determine the Source Stream of the connection CAB Bits Used to Determine the Source Channel of the Connection

8 Mbps SAB4 to SAB0 (STi0 to STi31) CAB6 to CAB0 (128 channel/frame)

16 Mbps SAB3 to SAB0 (STi0 to STi15) CAB7 to CAB0 (256 channel/frame)

4 Mbps & 8 Mbps SAB4 to SAB0 (STi0 to STi31) CAB6 to CAB0 (64 or 128 channel/frame)

16 Mbps & 8 Mbps SAB4 to SAB0 (STi0 to STi19) CAB7 to CAB0 (128 or 256 channel/frame)

4 Mbps SAB4 to SAB0 (STi0 to STi31) CAB5 to CAB0 (64 channel/frame)

2 Mbps & 4 Mbps SAB4 to SAB0 (STi0 to STi31) CAB5 to CAB0 (32 or 64 channel/frame)

2 Mbps SAB4 to SAB0 (STi0 to STi31) CAB4 to CAB0 (32 channel/frame)

Table 15 - SAB and CAB Bits Programming for Various Interface Mode 765432108910111213 CABCABCABCAB CABCABCABSABSABSAB TM0 OETM1 21076543210 CAB SABSAB

Zarlink Semiconductor Inc. * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V) Absolute Maximum Ratings* Parameter Symbol Min. Max. Units 1 Supply Voltage V DD -0.3 5.0 V 2 Voltage on any 3.3 V tolerant pin I/O (other than supply pins) VI VSS - 0.3 V DD + 0.3 V

3 Voltage on any 5 V tolerant pin I/O (other than sup-

ply pins) VI VSS - 0.3 5.0 V

4 Continuous Current at digital outputs I o 20 mA

5 Package power dissipation P D 1W

6 Storage temperature T S - 65 +125 °C

Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics Sym. Min. Typ. Max. Units Test Conditions

1 Operating Temperature T OP -40 +85 °C

2 Positive Supply V DD 3.0 3.6 V 3 Input High Voltage V IH 0.7VDD VDD V 4 Input High Voltage on 5 V Tolerant Inputs V IH 5.5 V 5 Input Low Voltage V IL VSS 0.3VDD V Characteristics Sym. Min. Ty p. Max. Units Test Conditions I N P U T S Supply Current I DD 64 100 mA Output unloaded 2 Input High Voltage V IH 0.7VDD V 3 Input Low Voltage V IL 0.3VDD V

4 Input Leakage (input pins)

Input Leakage (with pull-up or pull-down) I IL IBL µA µA0 ≤<V≤VDD See Note 1

5 Input Pin Capacitance C I 10 pF

U T P U T S Output High Voltage V OH 0.8VDD VI OH = 10mA 7 Output Low Voltage V OL 0.4 V I OL = 10mA

8 High Impedance Leakage I OZ 5 µA 0 < V < V DD See Note 1

9 Output Pin Capacitance C O 10 pF

Zarlink Semiconductor Inc. Characteristics Sym. Level Units Conditions 1 CMOS Threshold Voltage V TT 0.5VDD V 2 CMOS Rise/Fall Threshold Voltage High V HM 0.7VDD V 3 CMOS Rise/Fall Threshold Voltage Low V LM 0.3VDD V Characteristic Sym. Min. Typ. Max. Units CLK

1 Frame pulse width t FPW 55 65 ns

16.384 MHz2 Frame Pulse Setup time before CLK falling t FPS 5n s

3 Frame Pulse Hold Time from CLK falling t FPH 10 ns

4C L K Period t CP 55 70 ns 5C L K Pulse Width High t CH 20 40 ns 6C L K Pulse Width Low t CL 20 40 ns 7 Frame pulse width t FPW8 115 145 ns 8.192 MHz

8 Frame Pulse Setup time before CLK falling t FPS8 5n s

9 Frame Pulse Hold Time from CLK falling t FPH8 10 ns

10 CLK Period t CP8 110 150 ns

11 CLK Pulse Width High t CH8 50 75 ns

12 CLK Pulse Width Low t CL8 50 75 ns

13 Clock Rise/Fall Time t r, tf 0+ 1 0 n s

Zarlink Semiconductor Inc. Note: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL Figure 8 - ST-BUS Timing for Stream rate of 16.384 Mbps Characteristic Sym. Min. Typ. Max. Units Test Conditions

1 Input Data Sample Point (Data rate of

16 Mbps)

tIDS_16 30 ns

2 Input Data Sample Point (Data rate of

8M b p s ) tIDS_8 91 ns

3 Input Data Sample Point (Data rate of

4M b p s ) tIDS_4 183 ns

4 Input Data Sample Point (Data rate of

2M b p s ) tIDS_2 366 ns

5 STi Set-up Time (Data rate of 16 Mbps) t SIS_16 0n s

6 STi Hold Time (Date rate of 16 Mbps) t SIH_16 8n s

7 STi Set-up Time (Date rate of 2, 4 or 8 Mbps) t SIS 0n s

8 STi Hold Time (Date rate of 2, 4 or 8 Mbps) t SIH 8n s

9 STo Delay - Active to Active t SOD 8

ns C L=30pF CL=200pF

10 Output Driver Enable (ODE) Delay t ODE 35 ns R L=1K, CL=200pF,

11 STo delay - Active to High-Z

• High-Z to Active tDZ, tZD 35 ns R L=1K, CL=200pF, See Note 1 VTT VTT F0i CLK tFPW STo STi tFPH tSOD tSIH_16 tCH tCL tFPS tCP tSIS_16 VTT VTT VHM VLM tr tf Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch255 Bit0 Ch255 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit1 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch255 Bit0 Ch255 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit1 (16.384 MHz) (16 Mbps) (16 Mbps) tIDS_16

Zarlink Semiconductor Inc. Figure 15 - Output Driver Enable (ODE) VTTHiZHiZSTo ODE tODEtODE Valid Data VTT

Zarlink Semiconductor Inc. Note: 1. High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. 2. Register write timing refers to the rising edge of DS at the end of the write cycle. 3. Memory write timing refers to the falling edge of DS at the beginning of the write cycle. Characteristics Sym. Min. Typ. Max. Units Test Conditions 1C S setup from DS falling t CSS 0n s 2R / W setup from DS falling t RWS 10 ns

3 Address setup from DS falling t ADS 2n s

4C S hold after DS rising t CSH 0n s 5R / W hold after DS rising t RWH 2n s

6 Address hold after DS rising t ADH 10 ns

7 Data setup from DTA Low on Read t DDR 27 ns C L=150pF

8 Data hold on read t DHR 12 20 ns C L=150pF, RL=1K

9 Data setup on write (register write 2)t DSW 0n s

10 Valid Data Delay on write (memory write 3)

For 16 Mbps, 16&8 Mbps, 8 Mbps, 4&8 Mbps modes For 4 Mbps, 4&2 Mbps modes For 2 Mbps mode t SWD 50 185 ns ns ns

11 Data hold on write t

12a Acknowledgment Delay: Register RD or WR t AKD 55 ns C L=150pF 12b Acknowledgment Delay: Memory RD or WR For 16 Mbps, 16&8 Mbps, 8 Mbps, 4&8 Mbps modes For 4 Mbps, 4&2 Mbps modes For 2 Mbps mode t AKD 100 140 240 ns ns ns C L=150pF

13 Acknowledgment Hold Time t AKH 24 ns C L=150pF, RL=1K,

Zarlink Semiconductor Inc. Figure 16 - Motorola Non-Multiplexed Bus Timing DS A0-A7 CS D0-D15 D0-D15 READ WRITE tCSS tCSH tADH tDHR tRWS R/W tADS tRWH tDHW tAKD tSWD tDDR tAKH DTA VTT VTT VTT VTT VTT VTT VTT tDSW Valid Address Valid Read Data Valid Write Data

c Zarlink Semiconductor 2002 All rights reserved. APPRD. ISSUE DATE ACN Package Code : GA Previous package codes: 213936 20Jan03

c Zarlink Semiconductor 2002 All rights reserved. APPRD. ISSUE DATE ACN Package Code Previous package codes 213740 15Nov02 213834 11Dec02

www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I 2C Patent rights to use these components in and I 2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE For more information about all Zarlink products visit our Web Site at