MT90820AL

MT90820 ZARLINK | Alldatasheet

Document overview

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Technical content

Features

• 2 , 0 4 8 × 2,048 channel non-blocking switching at

8.192 Mb/s

• Per-channel variable or constant throughput delay
• Automatic identification of ST-BUS/GCI interfaces
• Accept ST-BUS streams of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel high impedance output control
• Per-channel message mode
• Control interface compatible to Motorola non- mulitplexed CPUs
• Connection memory block programming
• IEEE-1149.1 (JTAG) Test Port

Applications

• Medium and large switching platforms
• CTI application
• Voice/data multiplexer
• Digital cross connects
• ST-BUS/GCI interface functions
• Support IEEE 802.9a standard August 2005

Ordering Information

MT90820AP 84 Pin PLCC Tubes MT90820AL 100 Pin MQFP Trays MT90820APR 84 Pin PLCC Tape & Reel MT90820AL1 100 Pin MQFP* Trays MT90820AP1 84 Pin PLCC* Tubes MT90820APR1 84 Pin PLCC* Tape & Reel *Pb Free Matte Tin -40°C to +85 °C CMOS ST-BUSTM Family MT90820 Large Digital Switch Data Sheet Figure 1 - Functional Block Diagram Test Port STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15 STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 Parallel to Serial Converter Output MUX Microprocessor InterfaceTiming Unit Internal Registers F0i FE/ AS/ IM DS/ RD CS R/W /WR A7-A0ALEHCLK DTA D15-D8/ AD7-AD0 CSTo ODEVSS ConnectionMemory CLK VDD WFPS TDI TDO IC RESETTCK TRST Serial to Parallel Converter TMS Multiple Buffer Data Memory Loopback

Zarlink Semiconductor Inc.

Description

The MT90820 Large Digital Switch has a non-blocking switch capacity of 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s, 1,024 x 1,024 channels at 4.096 Mb/s and 512 x 512 channels at 2.048 Mb/s. The device has many features that are programmable on pe r stream or per channel bas is, including message mode, input offset delay and high impedance output control. Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, input stream can be individually calibrated for input frame offset using a dedicated pin.

Zarlink Semiconductor Inc. Figure 2 - Pin Connections NC NC NC NC NC 31 55 10 8 6 4 2 84 82 80 78 76 34 36 38 40 42 44 46 48 50 52 D14 D12 D11 D10 AD2 AD1 AD0 VSS VSS VDD AD7 AD6 AD5 AD4 AD3 DTA D13 D15 CSTo AS/ALE TCK TDO CS DS/RD IM TDI TRST IC RESET WFPS TMS R/W/RW STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi11 STi15 FE/HCLK STi10 STi12 STi13 STi14 F0i VDD CLK VSS ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 VSS VDD VSS STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15 VSS

84 PIN PLCC

100 PIN MQFP

50525456586062646668707274767880 22 24 26 28 30 2018161412108642 ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 VSS VDD VSS STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15 VSS CSTo NC NC NC NC D14 D12 D11 D10 AD2 AD1 AD0 VSS VSS VDD AD7 AD6 AD5 AD4 AD3 DTA D13 D15 CS TCK TDO WFPS R/W/RW DS/RD TDI TRST IC TMS AS/ALE VDD RESET IM NC NC NC NC NC STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi11 STi15 FE/HCLK STi10 STi12 STi13 STi14 F0i CLK VSS NC NC

Zarlink Semiconductor Inc. Pin Description Pin # Name Description84 PLCC 100 MQFP 1, 11, 30, 54 64, 75 31, 41, 56, 66, 76, 99 V SS Ground. 2, 32, 5, 40, VDD +5 Volt Power Supply. 3 - 10 68-75 STo8 - 15 ST-BUS Output 8 to 15 (Three-state Outputs): Serial data Output stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 - 1 in the IMS register. 12 - 27 81-96 STi0 - 15 ST-BUS Input 0 to 15 (Inputs): Serial data input stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 - 1 in the IMS register. 28 97 F0i Frame Pulse (Input): When the WFPS pin is low, this input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI specifications. When the WFPS pin is high, this pin accepts a negative frame pulse which conforms to WFPS formats. 29 98 FE/HCLK Frame Evaluation / HCLK Clock (Input): When the WFPS pin is low, this pin is the frame measurement input. When the WFPS pin is high, the HCLK (4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode. 31 100 CLK Clock (Input): Serial clock for shifting data in/out on the serial streams (STi/o 0 - 15). Depending upon the value programmed at bits DR0 - 1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock. 33 6 TMS Test Mode Select (Input): JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. 34 7 TDI Test Serial Data In (Input): JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. 35 8 TDO Test Serial Data Out (Output): JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enable. 36 9 TCK Test Clock (Input): Provides the clock to the JTAG test logic. This pin is pulled high by an internal pull-up when not driven. 37 10 TRST Test Reset (Input): Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed low on power-up, or held low, to ensure that the MT90820 is in the normal functional mode. 38 11 IC Internal Connection (Input): Connect to VSS for normal operation. This pin must be low for the MT90820 to function normally and to comply with IEEE 1149 (JTAG) boundary scan requirements. This pin is pulled low internally when not driven.

Zarlink Semiconductor Inc. 39 12 RESET Device Reset (Schmitt Trigger Input): This input (active LOW) puts the MT90820 in its reset state that clears the device internal counters, registers and brings STo0 - 15 and microport data outputs to a high impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held low for a minimum of 100 nsec to reset the device. 40 13 WFPS Wide Frame Pulse Select (Input): When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in ST-BUS/GCI mode. 41 - 48 14-21 A0 - A7 Address 0 - 7 (Input): When non-multiplexed CPU bus operation is selected, these lines provide the A0 - A7 address lines to the internal memories. 49 22 DS/RD Data Strobe / Read (Input): For multiplexed bus operation, this input is DS. This active high DS input works in conjunction with CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active low input works in conjunction with CS to enable the read and write operations. For multiplexed bus operation, this input is RD. This active low input sets the data bus lines (AD0-AD7, D8-D15) as outputs. 50 23 R/W / WR Read/Write / Write (Input): In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls the direction of the data bus lines (AD0 - AD7, D8-D15) during a microprocessor access. For multiplexed bus operation, this input is WR. This active low input is used with RD to control the data bus (AD0 - 7) lines as inputs. 51 24 CS Chip Select (Input): Active low input used by a microprocessor to activate the microprocessor port of MT90820. 52 25 AS/ALE Address Strobe or Latch Enable (Input): This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed bus operation, connect this pin to ground. This pin is pulled low by an internal pull-down when not driven. 53 26 IM CPU Interface Mode (input): When IM is high, the microprocessor port is in the multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed mode. This pin is pulled low by an internal pull-down when not driven. 55 - 62 32-39 AD0 - 7 Address/Data Bus 0 to 7 (Bidirectional): These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins are also the input address bits of the microprocessor port. 65 - 72 42-49 D8 - 15 Data Bus 8-15 (Bidirectional): These pins are the eight most significant data bits of the microprocessor port. 73 50 DTA Data Transfer Acknowledgement (Active Low Output): Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is tri-stated. 74 55 CSTo Control Output (Output). This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1024 or 2048 bits per frame respectively. The level of each bit is determined by the CSTo bit in the connection memory. See External Drive Control Section. Pin Description Pin # Name Description84 PLCC 100 MQFP

Zarlink Semiconductor Inc. Device Overview The MT90820 Large Digital Switch is capable of switching up to 2,048 × 2,048 channels. The MT90820 is designed to switch 64 kbit/s PCM or N x 64 kbit/s data. The dev ice maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis. The serial input streams of the MT9082 0 can have a bit rate of 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125 µs wide frames, which contain 32, 64 or 128 channel s, respectively. The data rates on input and output streams are identical. By using Zarlink’s message mode capability, the microprocessor can access input and output time-slots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other ST- BUS devices. The MT90820 automatically identifies the pola rity of the frame synchronization input signal and configures its serial streams to be compatible to either ST-BUS or GCI formats. Two different microprocessor bus interfaces can be sele cted through the Input Mode pi n (IM): Non-multiplexed or Multiplexed. These interfaces provide compatibility with multiplexed and Motorola non-multiplexed buses. The frame offset calibration function allows users to me asure the frame offset delay using a frame evaluation pin (FE). The input offset delay can be prog rammed for individual streams using in ternal frame input offset registers, see Table 11. The internal loopback allows the ST-BUS output data to be looped around to the ST-BUS inputs for diagnostic purposes. Functional Description A functional Block Diagram of the MT90820 is shown in Figure 1. Data and Connection Memory For all data rates, the received serial data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the data memory. Depending upon the selected operation programmed in the interface mode select (IMS) register, the useable data memory may be as large as 2,048 bytes. The sequential addressing of the data memory is performed by an internal counter, which is reset by the input 8 kHz frame pulse (F0i) to mark the frame boundaries of the incoming serial data streams. 76 57 ODE Output Drive Enable (Input): This is the output enable control for the STo0 to STo15 serial outputs. When ODE input is low and the OSB bit of the IMS register is low, STo0- 15 are in a high impedance state. If this input is high, the STo0-15 output drivers are enabled. However, each channel may still be put into a high impedance state by using the per channel control bit in the connection memory. 77 - 84 58-65 STo0 - 7 Data Stream Output 0 to 7 (Three-state Outputs): Serial data Output stream. These streams have selectable data rates of 2.048, 4.096 or 8.192 Mb/s. -1 - 4 , 27 - 30, 51 - 54 77 - 80 NC No connection. Pin Description Pin # Name Description84 PLCC 100 MQFP

Zarlink Semiconductor Inc. Data to be output on the serial streams may come from either the data memory or connection memory. Locations in the connection memory are associated with particular ST -BUS output channels. When a channel is due to be transmitted on an ST-BUS output, the data for this c hannel can be switched either from an ST-BUS input in connection mode, or from the lower half of the connection memory in message mode. Data destined for a particular channel on a serial output stream is read from the data memory or connection memory during the previous channel time-slot. This allows enough time for memory access and parallel-to-serial conversion. Connection and Message Modes In the connection mode, the addresses of the input source data for all output channels are stored in the connection memory. The connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 13 and Table 14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto an ST-BUS output stream. By having several output channels connected to the same input source channel, data can be broadcasted from one input channel to several output channels. In message mode, the microprocessor writes data to the connection memory locations corresponding to the output stream and channel number. The lower half (8 least si gnificant bits) of the c onnection memory content is transferred directly to the parallel-to-serial converter. This data will be output on the ST-BUS streams in every frame until the data is changed by the microprocessor. The five most significant bits of the connection memory controls the fo llowing for an output channel: message or connection mode, constant or variabl e delay, enables/tristate the ST-BUS output drivers and enables/disable the loopback function. In addition, one of these bits allows the user to control the CSTo output. If an output channel is set to a high-impedance state through the connection memory, the ST-BUS output will be in a high impedance state for the duration of that channel. In addition to the per-channel control, all channels on the ST-BUS outputs can be placed in a high impedanc e state by either pulling the ODE input pin low or programming the output stand by (OSB) bit in the interface mode selection register to low. This action overrides the individual per-channel programming by the connection memory bits. The connection memory data can be accessed via the micr oprocessor interface through the D0 to D15 pins. The addressing of the device internal r egisters, data and connection memories is performed through the address input pins and the Memory Select (MS) bit of the control register. For details on device addressing, see Software Control and Control Register bits description (Table 4, Tables 6 and 7). Serial Data Interface Timing The master clock frequency must always be twice the data rate. The master clock (CLK) must be either at 4.096, data rates will always be identical. The MT90820 provides two different interface timing modes controlled by the WFPS pin. If the WFPS pin is low, the MT90820 is in ST-BUS/GCI mode. If the WFPS pin is hi gh, the MT90820 is in the wi de frame pulse (WFP) frame alignment mode. In ST-BUS/GCI mode, the input 8 kHz frame pulse c an be in either ST-BUS or GCI format. The MT90820 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of the master clock mar ks a bit boundary and the data is clocked in on the rising edge of CLK, three quarters of the way into the bit cell. In GCI format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell, see Figure 12.

Zarlink Semiconductor Inc. Wide Frame Pulse (WFP) Frame Alignment Timing When the device is in WFP frame alignment mode, the CL K input must be at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 kHz frame pulse is in ST-BUS form at. The timing relationship between CLK, HCLK and the frame pulse is defined in Figure 12. When WFPS pin is high, the frame alignment evaluation feature is disabled, but the frame input offset registers may still be programmed to compensate for the varying frame delays on the serial input streams. Switching Configurations The MT90820 maximum non-blocking switchin g configurations is determined by the data rates selected for the serial inputs and outputs. The switching configuration is selected by two DR bi ts in the IMS register. See Table 8 and Table 9.

2.048 Mb/s Serial Links (DR0=0, DR1=0)

When the 2.048 Mb/s data rate is selected, the device is configured with 16-inpu t/16-output data streams each having 32 64 Kbit/s channels each. This mode requires a CLK of 4.094 MHz and allows a maximum non-blocking capacity of 512 x 512 channels.

4.096 Mb/s Serial Links (DR0=1, DR1=0)

When the 4.096 Mb/s data rate is selected, the device is configured with 16-inpu t/16-output data streams each having 64 64 Kbit/s channels each. This mode requires a CLK of 8.192 MHz and allows a maximum non-blocking capacity of 1,024 x 1,024 channels.

8.192 Mb/s Serial Links (DR0=0, DR1=1)

When the 8.192 Mb/s data rate is selected, the device is configured with 16-inpu t/16-output data streams each having 128 64 Kbit/s channels each. This mode r equires a CLK of 16.384 MHz and allows a maximum non- blocking capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching configurations and the relationship between different serial data rates and the master clock frequencies. Table 1 - Switching Configuration Serial Interface Data Rate Master Clock Required (MHz) Matrix Channel Capacity 2 Mb/s 4.096 512 x 512 4 Mb/s 8.192 1,024 x 1,024 8 Mb/s 16.384 2,048 x 2,048

Zarlink Semiconductor Inc. Input Frame Offset Selection Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e., F0i). This feature is useful in compensating for variable path delays caused by serial backplanes of variable lengths, which may be implemented in large centralized and distributed switching systems. Each input stream can have its own delay offset value by programming the frame inpu t offset (FOR) registers. Possible adjustment can range up to +4 master clock (CLK) periods forward with resolution of 1/2 clock period. The output frame offset cannot be offset or adjusted. See Figure 4, Table 11 and Table 12 for delay offset programming. Serial Input Frame Alignment Evaluation The MT90820 provides the frame evaluati on (FE) input to determine different dat a input delays with respect to the frame pulse F0i. A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the evaluation starts when the SFE bit in the IMS register is changed from low to high. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR register. The SFE bit must be set to zero before a new measurement cycle started. In ST-BUS mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the ST-BUS frame pulse. In GCI mode, the rising edge of FE is evaluated against the ri sing edge of the GCI frame pulse. See Table 10 & Figure 3 for the description of the frame alignment register. This feature is not available when the WFP Frame Alignment mode is enabled (i.e., when the WFPS pin is connected to VDD). Memory Block Programming The MT90820 provides users with the capability of initia lizing the entire connection memory block in two frames. Bits 11 to 15 of every connection memory location will be programmed with the pattern st ored in bits 5 to 9 of the IMS register. The block programming mode is enabled by setting the memo ry block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data will be loaded into the bits 11 to 15 of every connection memory location. The other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero. Loopback Control The loopback control (LPBK) bit of each connection memory location allows the ST-BUS output data to be looped backed internally to the ST-BUS input for diagnostic purposes. If the LPBK bit is high, the associated ST-BUS output c hannel data is internally looped back to the ST-BUS input channel (i.e., data from STo n channel m will appear in STi n channel m). Note: when LPBK is activated in channel m STo n+1 (for n even) or STo n-1 (for n odd), the data from channel m of STi n will be switched to channel m STo n. The associated frame delay offset register must be set to zero for proper operation of the per-channel loopback function. If the LPBK bit is low, the per-channel loopback feature is disabled and the device will function normally. Delay Through the MT90820 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot in terchange functions with different throughput delay capabilities on the per-channel basis. For voice application, select variabl e throughput delay to ensure minimum

Zarlink Semiconductor Inc. delay between input and output data. In wideband data appli cations, select constant throughput delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the type of throughput delay selected in the V /C bit of the connection memory. Variable Delay Mode (V /C bit = 0) The delay in this mode is dependent only on the co mbination of source and destination channels and is independent of input and output streams. The minimum delay achievable in the MT90820 is three time-slots. When the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). The same frame delay occu rs if the input channel n is switched to output channel n+1 or n+2. When input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. Table 2 shows the possible delays for the MT90820 in the variable delay mode. Constant Delay Mode (V /C bit = 1) In this mode, frame integrity is maintained in all switch ing configurations by making use of a multiple data memory buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the MT90820, the minimum throughput delay achievable in the constant delay mode will be one frame. For example, in 2 Mb/s mode, when input time-slot 31 is switched to output time-slot 0. The maximum delay of 94 time- slots of delay occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 3. Table 2 - Variable Throughput Delay Value Table 3 - Constant Throughput Delay Value Microprocessor Interface The MT90820 provides a parallel microprocessor interface for non-multiplexed or multiplexed bus structures. This interface is compatible with Motorola non-multiplexed and multiplexed buses. If the IM pin is low, the MT90820 microprocessor interf ace assumes Motorola non-multiplexed bus mode. If the IM pin is high, the device micro-processor interface accept s two different timing modes (mode1 and mode2) which allows direct connection to multiplexed microprocessors. Input Rate Delay for Variable Throughput Delay Mode (m - output channel number) (n - input channel number)) m < n m = n, n+1, n+2 m > n+2

2.048 Mb/s 32 - (n-m) time-slots m-n + 32 time-slots m-n time-slots

4.096 Mb/s 64 - (n-m) time-slots m-n + 64 time-slots m-n time-slots

8.192 Mb/s 128 - (n-m) time-slots m-n + 128 time-slots m-n time-slots

Delay for Constant Throughput Delay Mode (m - output channel number) (n - input channel number))

2.048 Mb/s 32 + (32 - n) + (m - 1) time-slots

4.096 Mb/s 64 + (64 - n) + (m- 1) time-slots

8.192 Mb/s 128 + (128 - n) + (m- 1) time-slots

Zarlink Semiconductor Inc. The microprocessor interface automatically identifies the type of micro-processor bus connected to the MT90820. This circuit uses the level of the DS/RD input pin at the rising edge of AS/ALE to identify the appropriate bus timing connected to the MT90820. If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode 2 multiplexed bus timing is selected. For multiplexed operation, the required signals are the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch enable (AS/ALE), Data strobe/Read (DS/RD ), Read/Write /Write (R/W /W R), Chip select (CS) and Data transfer acknowledge (DTA ). See Figure 13 and Figure 14 for multiplexed parallel microport timing. For the Motorola non-multiplexed bus, the required signal s are the 16-bit data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines (CS , DS, R/W and DTA ). See Figure 15 for Motorola non-multiplexed microport timing. The MT90820 microport provides access to the internal re gisters, connection and data memories. All locations provide read/write access except for the data memory and the frame alignment register which are read only. Memory Mapping The address bus on the microprocessor interface select s the internal registers and memories of the MT90820. If the A7 address input is low, then the control (CR), interface mode select ion (IMS), frame alignment (FAR) and frame input offset (FOR) registers are addressed by A6 to A0 according to Table 4. If the A7 is high, then the remaining address input lines are used to select memory subsections of up to 128 locations corresponding to the maximum number of channel s per input or output stre am. The address input lines and the stream address bits (STA) of the control register allow access to the entire data and connection memories. The control and IMS registers together control all the major functions of the device. The IM S register should be programmed immediately after system power-up to establish the desired switching configuration as explained in the Serial Data Interface Timing and Switching Configurations sections. The control register is used to control switching operations in the MT90820. It selects the internal memory locations that specify the input and output channels selected for switching. The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS) and the stream address bits (STA). The memory bloc k programming bit allows us ers to program the entire connection memory block, (see Memory Block Programming section). The memory select bit controls the selection of the connection memory or the data Memory. The stream address bits define an internal memory subsections corresponding to input or output ST-BUS streams. The data in the IMS register consists of block programming bits (BPD0- BPD4), block programming enable bit (BPE), output stand by bit (OSB), star t frame evaluation bit (SFE) and data rate selection bits (DR0, DR1). The block programming and the block programming enable bits allows users to program the entire connection memory, (see Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all ST-BUS output drivers are enabled. Connection Memory Control The contents of the CSTo bit of each connection memo ry location are output on the CSTo pin once every frame. The CSTo pin is a 4.096, 8.192 or 16.384 Mb/s output, which carries 512, 1,024 or 2,048 bits, respectively. If the CSTo bit is set high, the corresponding bit on the CSTo output is transmitted high. If the CSTo bit is low, the corresponding bit on the CSTo output is transmitted low. The contents of the CSTo bits of the connection memory are transmitted sequentially on to the CSTo pin and ar e synchronous with the data rates on the other ST-BUS streams. The CSTo bit is output one channel before the corres ponding channel on the ST-BUS. For example, in 2 Mb/s mode, the contents of the CSTo bit in position 0 (STo0, CH0) of the connection memory is output on the first clock

Zarlink Semiconductor Inc. cycle of channel 31 through CSTo pin. The contents of the CSTo bit in position 32 (STo1, CH0) of the connection memory is output on the second clock cycle of channel 31 via CSTo pin. If the ODE pin or the OSB bit is high, the OE bit of each connection memory location enables (if high) or disables (if low) the output drivers for an individual ST-BUS output stream and channel. See Table 5 for detail. The message channel (MC) bit of the connection memory enables (if high) an associated ST-BUS output channel in message mode. If the MC bit is low, the contents of the stream address bit (SAB) and the channel address bit (CAB) of the connection memory define s the source information (stream and channel) of the time -slot that will be switched to the output. When message mode is enabled, only the lower half (8 least significant bits) of the connection memory is transferred to the ST-BUS outputs. Bit V /C (Variable/Constant Delay) of each connection memory location allows the per-channel selection between variable and constant throughput delay modes. If the LPBK bit is high, the associated ST-BUS output c hannel data is internally looped back to the ST-BUS input channel (i.e., data from STo n channel m will appear in STi n channel m). Note: when LPBK is activated in channel m STo n+1 (for n even) or STo n-1 (for n odd), the data from channel m of STi n will be switched to channel m STo n. The associated frame delay offset register must be set to zero for proper operation of the per-channel loopback function. If the LPBK bit is low, the per-channel loopback feature is disabled and the device will function normally. Initialization of the MT90820 After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after power up to keep all ST-BUS outputs in a high impe dance state until the micropr ocessor has initialized the switching matrix. During the microprocessor initializati on routine, the microprocessor should program the desired active paths through the switch, and put all other channels into a high impedance state. This procedure prevents two ST-BUS outputs from driving the same stream simultaneously. When this process is complete, the microprocessor controlling the matrices can bring the ODE pin or OSB bit high to relinquish the high impedance state control to the OE bit in the connection memory. (Note 1) A6 A5 A4 A3 A2 A1 A0 Location 0 0000000 C o n t r o l R e g i s t e r , C R 0 0 0 0 0 0 0 1 Interface Mode Selection Register, IMS 0 0000010 F r a m e A l i g n m e n t R e g i s t e r , F A R 0 0 0 0 0 0 1 1 Frame Input Offset Register 0, FOR0 0 0 0 0 0 1 0 0 Frame Input Offset Register 1, FOR1 0 0 0 0 0 1 0 1 Frame Input Offset Register 2, FOR2 0 0 0 0 0 1 1 0 Frame Input Offset Register 3, FOR3 Ch 0 Ch 1 Ch 30 Ch 31 (Note 2)

Zarlink Semiconductor Inc. Table 4 - Internal Register and Address Memory Mapping Table 5 - Output High Impedance Control Ch 32 Ch 33 Ch 62 Ch 63 (Note 3) Ch 64 Ch 65 Ch 126 Ch 127 (Note 4) Notes: 1. Bit A7 must be high for access to data and connection me mory positions. Bit A7 must be low for access to registers. 2. Channels 0 to 31 are used when serial interface is at 2 Mb/s mode. 3. Channels 0 to 63 are used when serial interface is at 4 Mb/s mode. 4. Channels 0 to 127 are used when serial interface is at 8 Mb/s mode. OE bit in Connection Memory ODE pin OSB bit in IMS register ST-BUS Output Driver Status

0 Don’t Care Don’t Care Per Channel

15 - 6 Unused Must be zero for normal operation. 5M B P Memory Block Program. When 1, the connection memory block programming feature is ready for the programming of Connection Memory high bits, bit 11 to bit 15. When 0, this feature is disabled. 4M S Memory Select. When 0, connection memory is selected for read or write operations. When 1, the data memory is selected for read operations and connection memory is selected for write operations. (No microprocessor write operation is allowed for the data memory.) (Note 1) A6 A5 A4 A3 A2 A1 A0 Location Read/Write Address: 00 H, Reset Value: 0000 H. 765432108910111213 STA0STA1STA2STA3 1415 MSMBP0000000000

Zarlink Semiconductor Inc. Table 6 - Control (CR) Register Bits Table 7 - Valid Address Lines for Different Bit Rates 3 - 0 STA3-0 Stream Address Bits. The binary value expressed by these bits refers to the input or output data stream, which corresponds to the subsection of memory made accessible for subsequent operations. (STA3 = MSB, STA0 = LSB) Input/Output Data Rate Valid Address Lines

2.048 Mb/s A4, A3, A2, A1, A0

4.096 Mb/s A5, A4, A3, A2, A1, A0

8.192 Mb/s A6, A5, A4 A3, A2, A1, A0

15-10 Unused Must be zero for normal operation. 9-5 BPD4-0 Block Programming Data. These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD4- 0 are loaded into bit 15 to bit 11 of the connection memory. Bit 10 to bit 0 of the connection memory are set to 0. 4B P E Begin Block programming Enable. A zero to one transition of this bit enables the memory block programming function. The BPE and BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set high, the device requires two frames to complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort the programming operation. When BPE = 1, the other bits in the IMS register must not be changed for two frames to ensure proper operation. Bit Name Description Read/Write Address: 00 H, Reset Value: 0000 H. 765432108910111213 STA0STA1STA2STA3 1415 MSMBP0000000000 Read/Write Address: 01H, Reset Value: 0000 H. 765432108910111213 DR0DR1BPDBPDBPD0 1415 BPD0 BPD BPE OSB SFE32 100000 4

Zarlink Semiconductor Inc. Table 8 - Interface Mode Selection (IMS) Register Bits Table 9 - Serial Data Rate Selection (16 input x 16 output) 3O S B Output Stand By. When ODE = 0 and OSB = 0, the output drivers of STo0 to STo15 are in high impedance mode. When ODE = 0 and OSB = 1, the output driver of STo0 to STo15 function normally. When ODE = 1, STo0 to STo15 output drivers function normally. 2S F E Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from zero to one, the evaluation procedure stops. To start another frame evaluation cycle, set this bit to zero for at least one frame. 1 - 0 DR1-0 Data Rate Select. Input/Output data rate selection. See Table 9 for detailed programming. DR1 DR0 Data Rate Selected Master Clock Required 0 0 2.048 Mb/s 4.096 MHz 0 1 4.096 Mb/s 8.192 MHz 1 0 8.192 Mb/s 16.384 MHz 1 1 Reserved Reserved Bit Name Description 15 - 13 Unused Must be zero for normal operation. 12 CFE Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0. 11 FD11 Frame Delay Bit 11. The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to 1/2 CLK cycle. Bit Name Description Read/Write Address: 01H, Reset Value: 0000 H. 765432108910111213 DR0DR1BPDBPDBPD0 1415 BPD0 BPD BPE OSB SFE32 100000 4 Read Address: 02H, Reset Value: 0000 H. 765432108910111213 FD0FD1FD2FD3FD4FD5FD6FD7FD8FD9FD10FD11CFE000 1415

Zarlink Semiconductor Inc. Table 10 - Frame Alignment (FAR) Register Bits Figure 3 - Example for Frame Alignment Measurement 10 - 0 FD10-0 Frame Delay Bits. The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 = MSB, FD0 = LSB) Bit Name Description Read Address: 02H, Reset Value: 0000 H. 765432108910111213 FD0FD1FD2FD3FD4FD5FD6FD7FD8FD9FD10FD11CFE000 1415 ST-BUS Frame FE Input GCI Frame FE Input (FD11 = 0, sample at CLK low phase) (FD11 = 1, sample at CLK high phase) (FD[10:0] = 09H) Offset Value (FD[10:0] = 06H) 10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Offset Value 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK

Zarlink Semiconductor Inc. Table 11 - Frame Input Offset (FOR) Register Bits Name (Note 1) Description OFn2, OFn1, OFn0 Offset Bits 2,1 & 0. These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the STi input pin: i.e., to start a new frame. The input frame offset can be selected to +4 clock periods from the point where the external frame pulse input signal is applied to the F0i input of the device. See Figure 4. DLEn Data Latch Edge. ST-BUS mode: DLEn =0, if clock rising edge is at the 3/4 point of the bit cell. DLEn =1, if when clock falling edge is at the 3/4 of the bit cell. GCI mode: DLEn =0, if clock falling edge is at the 3/4 point of the bit cell. DLEn =1, if when clock rising edge is at the 3/4 of the bit cell. Note 1: n denotes an input stream number from 0 to 15. Input Stream Offset Measurement Result from Frame Delay Bits Corresponding Offset Bits FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn No clock period shift (Default) 1 0 0 0 0 0 0 0 Read/Write Address: 03 H for FOR0 register, 04H for FOR1 register, 05H for FOR2 register, 06H for FOR3 register, Reset value: 0000 H for all FOR registers. 765432108910111213 DLE0OF00OF01OF02 1415 DLE1OF10OF11OF12DLE2OF20OF21OF22DLE3OF30OF31OF32 FOR0 register FOR1 register 765432108910111213 DLE4OF40OF41OF42 1415 DLE5OF50OF51OF52DLE6OF60OF61OF62DLE7OF70OF71OF72 FOR2 register 765432108910111213 DLE8OF80OF81OF82 1415 DLE9OF90OF91OF92DLE10OF100OF101OF102DLE11OF110OF111OF112 FOR3 register 765432108910111213 DLE12OF120OF121OF122 1415 DLE13OF130OF131OF132DLE14OF140OF141OF142DLE15OF150OF151OF152

Zarlink Semiconductor Inc. Table 12 - Offset Bits (OFn2, OFn1, OFn0, DLEn) & Frame Delay Bits (FD11, FD2-0) Figure 4 - Examples for Input Offset Delay Timing + 0.5 clock period shift 0 0 0 0 0 0 0 1 +1.0 clock period shift 1 0 0 1 0 0 1 0 +1.5 clock period shift 0 0 0 1 0 0 1 1 +2.0 clock period shift 1 0 1 0 0 1 0 0 +2.5 clock period shift 0 0 1 0 0 1 0 1 +3.0 clock period shift 1 0 1 1 0 1 1 0 +3.5 clock period shift 0 0 1 1 0 1 1 1 +4.0 clock period shift 1 1 0 0 1 0 0 0 +4.5 clock period shift 0 1 0 0 1 0 0 1 Input Stream Offset Measurement Result from Frame Delay Bits Corresponding Offset Bits FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn ST-BUS F0i CLK STi Stream STi Stream STi Stream STi Stream GCI F0i CLK Input Stream Input Stream Input Stream Input Stream offset=0, DLE=0 offset=1, DLE=0 offset=0, DLE=1 offset=1, DLE=1 offset=0, DLE=0 offset=1, DLE=0 offset=0, DLE=1 offset=1, DLE=1 denotes the 3/4 point of the bit cell Bit 7 Bit 7 Bit 7 Bit 7 Bit 0 Bit 0 Bit 0 Bit 0 denotes the 3/4 point of the bit cell

Zarlink Semiconductor Inc. Table 13 - Connection Memory Bits Table 14 - CAB Bits Programming for Different Data Rates JTAG Support The MT90820 JTAG interface conforms to the Boundary-Scan standard I EEE1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The ope ration of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. Bit Name Description 15 LPBK Per Channel Loopback. When 1, the STi n channel m data comes from the STo n channel m. For proper per channel loopback operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode. Refer to the section Loopback Control or Connection Memory Control for more details. 14 V /C Variable /Constant Throughput Delay. This bit is used to select between the variable (low) and the constant delay (high) modes on a per-channel basis. 13 MC Message Channel. When 1, the contents of the connection memory are output on the corresponding output channel and stream. Only the lower byte (bit 7 - bit 0) will be output to the ST-BUS output pins. When 0, the contents of the connection memory are the data memory address of the switched input channel and stream. 12 CSTo Control ST-BUS output. This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output first. 11 OE Output Enable. This bit enables the ST-BUS output drivers on a per-channel basis. When 1, the output driver functions normally. When 0, the output driver is in a high- impedance state. 10 - 8, (Note 1) SAB3-0 Source Stream Address Bits. The binary value is the number of the data stream for the source of the connection. 6 - 0 (Note 1) CAB6-0 Source Channel Address Bits. The binary value is the number of the channel for the source of the connection. Note 1: If bit 13 (MC) of the corresponding connection memory lo cation is 1 (device in message mo de), then these entire 8 bits (SAB0, CAB6 - CAB0) are output on the output channel an d stream associated with this location. Data Rate CAB Bits Used to Determine the Source Channel of the Connection

2.048 Mb/s CAB4 to CAB0 (32 channel/input stream)

4.096 Mb/s CAB5 to CAB0 (64 channel/input stream)

8.192 Mb/s CAB6 to CAB0 (128 channel/input stream)

CAB0CAB1CAB2CAB6SAB0 CAB3CAB4CAB5SAB1SAB2SAB3OECSTo V/C MCLPBK

Zarlink Semiconductor Inc. Test Access Port (TAP) The Test Access Port (TAP) provides access to the many test functions of the MT90820. It consists of three input pins and one output pin. The following pins are from the TAP.

• Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic.
• Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising e dge of the TCK pulse. This pin is internally pulled to Vdd when it is not driven from an external source.
• Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to th e TMS input. Both registers are described in a subsequent section. The received input data is samp led at the rising edge of TCK pulses. This pin is internally pulled to Vdd when it is not driven from an external source.
• Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towa rds the TDO. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state.
• Test Reset (TRST ) Reset the JTAG scan structure. This pin is internally pulled to VDD. Instruction Register In accordance with the IEEE 1149.1 standard, the MT90820 uses public instructions. The MT90820 JTAG Interface contains a two-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifte d-IR state. Subsequently, the instruct ions are decoded to achieve two basic functions: to select the test data regi ster that may operate while the instru ction is current, and to define the serial test data register path, which is used to shift data between TDI and DO during data register scanning. Test Data Register As specified in IEEE 1149.1, the MT90820 JTAG Interface contains two test data registers:
• The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the MT90820 core logic.
• The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO. The MT90820 boundary scan register contains 118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out. All tristate enable bits are active high.

Zarlink Semiconductor Inc. Device Pin Boundary Scan Bit 0 to Bit 117 Tristate Control Output Scan Cell Input Scan Cell STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE 16 CSTo 17 18 DTA D15 D14 D13 D12 D11 D10 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 IM 68 AS/ALE 69 CS R/W / WR 71 DS/RD 72 WFPS 81 RESET Table 15 - Boundary Scan Register Bits

Zarlink Semiconductor Inc. Switch Matrix Architectures The MT90820 is an ideal device for medium to large size switch matrices. Applications where voice and grouped data channels are transported within t he same frame, the voice samples have to be time interchanged with a minimum delay while maintaining the integrity of groupe d data. To ensure the integrity of grouped data during switching and to provide a minimum delay for voice conne ctions, the MT90820 provides the per-channel selection between variable and constant throughput delay. This can be selected by the V /C bit of the Connection Memory. Figure 5 illustrates how four MT90820 devices can be used to form non-blocking switches up to 4096 channels with data rate of 8.192 Mb/s. CLK 83 FE/HCLK 84 F0i 85 STi15 STi14 STi13 STi12 STi11 STi10 STi9 STi8 STi7 STi6 STi5 STi4 STi3 STi2 STi1 STi0 100 101 STo15 STo14 STo13 STo12 STo11 STo10 STo9 STo8 102 104 106 108 110 112 114 116 103 105 107 109 111 113 115 117 Device Pin Boundary Scan Bit 0 to Bit 117 Tristate Control Output Scan Cell Input Scan Cell Table 15 - Boundary Scan Register Bits

Zarlink Semiconductor Inc. Serial Input Frame Alignment Evaluation The MT90820 is capable of performing frame alignment evaluation. The frame pulse under evaluation is connected to the FE (frame measurement) pin. An external multiplexe r is required to selected one of the frame pulses related to the different input streams. Figur e 6 gives an example of performing me asurement for 16 frame pulses can be performed. Figure 5 - Switch Matrix with Seri al Stream at Various Bit Rates Figure 6 - Serial Input Frame Alignmen t Evaluation for Various Frame Pulses Wide Frame Pulse (WFP) Frame Alignment Mode When the device is the wide frame pulse mode, the device can operate in the HMVIP and MVIP-90 environment if the input data streams are sampled at 3/4 bit time. When input data stream are sampled at half-bit time as specified in the HMVIP and MVIP-90 standard, the device can only operate with data rate of 2 Mb/s. Refer to the ST-BUS output delay parameter, tSOD, as specified in the AC Electrical Characteristic table.

16 Streams

2.048 Mb/s 1,024 - Channel Switch

4.096 Mb/s 2,048 - Channel Switch

4,096 - Channel Switch8.192 Mb/s Bit Rate (IN/OUT) Size of Switch Matrix STi0 STo[0:15] STi1 STi2 STi15 Frame Alignment Evaluation circuit Central Timing Source FE input CLK FP FP STi15 FP STi0 FP STi1 FP STi2 External Mux MT90820 Note: 1. Use the external mux to select one of the serial frame pulses. 2. To start a measurement cycle, set the Start Frame Evaluation (SFE) bit in the IM S register low for at least 1 frame. 3. Frame evaluation starts when the SFE bit is changed from low to high. 4. Two frames later, the Complete Frame Ev aluation (CFE) bit of the Frame Alignment Register (FAR) changes from low to high to signal the CPU that a valid offset measurement is ready to be read from bit [11:0] of the FAR register. 5. The SFE bit must be set to zero be fore a new measurement cycle started.

Zarlink Semiconductor Inc. Figure 8 - 8,192 x 8,192 Channel Switch Matrix Figure 9 - Trunk Card Block Diagram * Exceeding these values may cause permanent damage. F unctional operation under these conditions is not implied. Absolute Maximum Ratings* Parameter Symbol Min. Max. Units 1 Supply V oltage V DD 6.0 V 2 V oltage on any pin I/O (other than supply pins) V I VSS - 0.3 V DD +0.3 V

3 Continuous Current at digital outputs I o 20 mA

4 Package power dissipation (PLCC & PQFP) P D 2W

5 Storage temperature T S - 65 +125 °C

32 Streams

4,096 x 4,096 Switch Matrix (Figure 5) 4,096 x 4,096 Switch Matrix (Figure 5) 4,096 x 4,096 Switch Matrix (Figure 5) 4,096 x 4,096 Switch Matrix (Figure 5) OUT (8.192Mb/s pre channel) 256-channel in DSTo DSTi DSTo DSTi DSTo DSTi (8.192Mb/s pre channel)

Zarlink Semiconductor Inc. Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V) Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics Sym. Min. Typ. Max. Units Test Conditions

1 Operating Temperature T OP -40 +85 °C

2 Positive Supply V DD 4.75 5.25 V 3 Input High V oltage V IH 2.4 V DD V 400 mV noise margin 4 Input Low V oltage V IL VSS 0.4 V 400 mV noise margin Characteristics Sym. Min. Typ. Max. Units Test Conditions I N P U T S Supply Current @ 2 Mb/s IDD 50 mA Output unloaded@ 4 Mb/s 90 mA @ 8 Mb/s 170 mA 2 Input High V oltage V IH 2.0 V 3 Input Low V oltage V IL 0.8 V

4 Input Leakage (input pins)

Input Leakage (bi-directional pins) IIL IBL µA µA0 ≤<V≤VDD See Note 1

5 Input Pin Capacitance C I 10 pF

U T P U T S Output High V oltage V OH 2.4 V I OH = 10mA 7 Output Low V oltage V OL 0.4 V I OL = 10mA

8 High Impedance Leakage I OZ 5 µA 0 < V < V DD See Note 1

9 Output Pin Capacitance C O 10 pF

Characteristics Sym. Level Units Conditions 1 TTL Threshold V TT 1.5 V 2 TTL Rise/Fall Threshold V oltage High V HM 2.0 V 3 TTL Rise/Fall Threshold V oltage Low V LM 0.8 V

Zarlink Semiconductor Inc. Characteristic Sym. Min. Typ. Max. Units Notes

1 Frame pulse width (ST-BUS, GCI)

Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s tFPW 295 145 ns ns ns WFPS Pin = 0

2 Frame Pulse Setup time before CLK

falling (ST-BUS or GCI) tFPS 10 ns WFPS Pin = 0

3 Frame Pulse Hold Time from CLK

falling (ST-BUS or GCI) tFPH 16 ns WFPS Pin = 0 4C L K P e r i o d Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s tCP 190 110 300 150 ns ns ns WFPS Pin = 0

5 CLK Pulse Width High

Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s tCH 150 ns ns ns WFPS Pin = 0

6 CLK Pulse Width Low

Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s tCL 150 ns ns ns WFPS Pin = 0

7 Clock Rise/Fall Time tr, tf 10 ns

8 Wide frame pulse width

Bit rate = 8.192 Mb/s tHFPW 195 295 ns WFPS Pin = 1

9 Frame Pulse Setup Time before

tHFPS 10 150 ns WFPS Pin = 1

10 Frame Pulse Hold Time from HCLK

tHFPH 20 150 ns WFPS Pin = 1 11 HCLK (4.096MHz) Period Bit rate = 8.192 Mb/s tHCP 190 300 ns WFPS Pin = 1 12 HCLK (4.096MHz) Pulse Width High Bit rate = 8.192 Mb/s tHCH 85 150 ns WFPS Pin = 1 13 HCLK (4.096MHz) Pulse Width Low Bit rate = 8.192 Mb/s tHCL 85 150 ns WFPS Pin = 1

14 HCLK Rise/Fall Time tHr, tHf 10 ns

15 Delay between falling edge of HCLK

tDIF -10 10 ns WFPS Pin = 0 or 1

Zarlink Semiconductor Inc. Note 1: High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. Characteristic Sym. Min. Typ. Max. Units Test Conditions

1 Sti Set-up Time tSIS 0n s

2 Sti Hold Time tSIH 20 ns

3 Sto Delay - Active to Active

@ 2.048 Mb/s mode @ 4.096 Mb/s mode @ 8.192 Mb/s mode @ 8.192 Mb/s mode tSOD ns ns ns ns C L=200pF CL=200pF CL=200pF CL=30pF

4 STo delay - Active to High-Z

2.048 Mb/s mode

4.096 Mb/s mode

8.192 Mb/s mode

t DZ ns ns ns RL=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1

5 Sto delay - High-Z to Active

t ZD ns ns ns R L=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1

6 Output Driver En able (ODE) Delay

t ODE ns ns ns R L=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1 RL=1K, CL=200pF, See Note 1

7 CSTo Output Delay

t XCD ns ns ns CL=200pF CL=200pF CL=200pF

Zarlink Semiconductor Inc. Figure 10 - ST-BUS Timing for 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0. Figure 11 - GCI Timing at 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0 VTT VTT F0i CLK tFPW STo STi tFPH tSOD tSIH tCH tCL Bit 0, Last Ch (Note1)

2.048 Mb/s mode, last channel = ch 31,

4.196 Mb/s mode, last channel = ch 63,

8.192 Mb/s mode, last channel = ch 127. tFPS tCP tSIS VTT VTT Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 Bit 0, Last Ch (Note1) Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0 Note 1: VHM VLM tr tf 2Mb/s mode, last channel = ch 31, 4Mb/s mode, last channel = ch 63, 8Mb/s mode, last channel = ch 127 VTT VTT F0i CLK tFPW STo STi tFPH tSOD tSIH tCH tCL Bit 7, Last Ch (Note1) tFPS tCP tSIS VTT VTT Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 Bit 7, Last Ch (Note1) Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 Note 1: tr tf VHM VLM

Zarlink Semiconductor Inc. Figure 14 - Output Driver Enable (ODE) Note 1: High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. Characteristics Sym. Min. Typ. Max. Units Test Conditions 1A L E p u l s e w i d t h t ALW 20 ns

2 Address setup from ALE falling t ADS 10 ns

3 Address hold from ALE falling t ADH 10 ns

4R D active after ALE falling t ALRD 10 ns 5D a t a s e t u p f r o m D T A Low on Read t DDR 10 ns C L=150pF 6C S hold after RD/WR tCSRW 0n s 7R D pulse width (fast read) t RW 80 ns 8C S setup from RD tCSR 0n s

9 Data hold after RD tDHR 10 75 ns C L=150pF, RL=1K,

Note 1.

10 WR pulse width (fast write) t WW 90 ns

11 WR delay after ALE falling t ALWR 10 ns

12 CS setup from WR tCSW 0n s

13 Data setup from WR (fast write) t DSW 90 ns

14 Valid Data Delay on write (slow write) t SWD 122 ns

15 Data hold after WR inactive t DHW 10 ns

16 Acknowledgment Delay:

Reading/Writing Memory, @ 2Mb/s @ 4Mb/s @ 8Mb/s t AKD ns ns ns ns C L=150pF CL=150pF CL=150pF CL=150pF

17 Acknowledgment Hold Time t AKH 45 80 ns C L=150pF, RL=1K,

Note 1. VTTHiZHiZSTo ODE tODEtODE Valid Data VTT

Zarlink Semiconductor Inc. Figure 15 - Multiplexed Bus Timing (Mode 1) Note 1. High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. Characteristics Sym. Min. Typ. Max. Units Test Conditions 1A S p u l s e w i d t h t ASW 80 ns

2 Address setup from AS falling t ADS 10 ns

3 Address hold from AS falling t ADH 10 ns

4 Data setup from DTA Low on Read t DDR 10 ns C L=150pF

5C S hold after DS falling t CSH 0n s 6C S setup from DS rising t CSS 0n s

7 Data hold after write t DHW 10 ns

8 Data setup from DS -Write (fast write) t DWS 25 ns

9 Valid Data Delay on write (slow write) t SWD 122 ns

10 R/W setup from DS rising t RWS 60 ns

11 R/W hold after DS falling t RWH 10 ns

12 Data hold after read t DHR 10 50 75 ns C L=150pF, RL=1K,

13 DS delay after AS falling t DSH 10 ns

14 Acknowledgment Delay:

Reading/Writing Memory, @ 2Mb/s @ 4Mb/s @ 8Mb/s t AKD ns ns ns ns C L=150pF CL=150pF CL=150pF CL=150pF

15 Acknowledgment Hold Time t AKH 45 80 ns C L=150pF, RL=1K,

Zarlink Semiconductor Inc. Figure 16 - Multiplexed Bus Timing (Mode2) Note 1: High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. Characteristics Sym. Min. Typ. Max. Units Test Conditions 1C S setup from DS falling t CSS 0n s 2R / W setup from DS falling t RWS 10 ns

3 Address setup from DS falling t ADS 2n s

4C S hold after DS rising t CSH 0n s 5R / W hold after DS rising t RWH 5n s

6 Address hold after DS rising t ADH 5n s

7 Data setup from DTA Low on Read t DDR 0n s C L=150pF

8 Data hold on read t DHR 10 50 75 ns C L=150pF, RL=1K

9 Data setup on write (fast write) t DSW 20 ns

10 Valid Data Delay on write (slow write) t SWD 122 ns

11 Data hold on write t DHW 8n s

12 Acknowledgment Delay:

Reading/Writing Memory, @ 2Mb/s @ 4Mb/s @ 8Mb/s t AKD ns ns ns ns C L=150pF CL=150pF CL=150pF CL=150pF

13 Acknowledgment Hold Time t AKH 45 80 ns C L=150pF, RL=1K,

Zarlink Semiconductor Inc. Figure 17 - Motorola Non-Multiplexed Bus Timing DS A0-A7 AD0-AD7 CS D8-D15 AD0-AD7 D8-D15 READ WRITE tCSS tCSH tADH tDHR tRWS R/W tADS tRWH tDHW tAKD tSWD tDDR tAKH DTA VTT VTT VTT VTT VTT VTT VTT tDSW VALID ADDRESS VALID READ DATA VALID WRITE DATA

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