MT9080

MT9080 MITEL | Alldatasheet

Document overview

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Technical content

Features

• Timeslot interchange circuit for digital switch

applications

• 16 bit wide data bus I/O
• 2048 x 16 bit wide byte capacity
• Dual addressing capability; internal counter and external address bus
• Variable clock and frame rates
• Microprocessor interface
• C M O S
• Building block for digital switching matrices used in PBXs, CO equipment, data switching, etc.
• Programmable delay lines

Description

The MT9080 is a flexible memory module suitable for use as a basic building block in the construction of large digital switching matrices. It can be configured as either a Data Memory or a Connection Memory. Interface to the device is via 16 bit wide data and address busses. The MT9080 can operate with variable clock rates up to 16.7 MHz. Figure 1 - Functional Block Diagram D0i/D15i A0-A15 ME 16 16 Address MUX

11 Bit

FP CK ODE DS CS R/W Mx My Mz DTA D15o

Ordering Information

-40°C to 70°C ISSUE 3 January 1993 MT9080 SMX - Switch Matrix Module CMOS

Figure 2 - Pin Connections Pin Description Pin # Name Description 1V SS Ground. 2-5 D0i-D3i Input/Microport Data Bus. This is part of a 16 bit data bus. The data bus is bidirectional in Connect Memory mode where it is typically interfaced to a microprocessor. In all other modes the data bus is an input. Data to be switched through the device is clocked in at this port. SS Ground. 7-10 D4i-D7i Input/Microport Data Bus. See description for pins 2-5 above. 11 V SS Ground. 12-15 D8i-D11i Input/Microport Data Bus. See description for pins 2-5 above. 16 V SS Ground. 17-20 D12i-D15i Input/Microport Data Bus. See description for pins 2-5 above. 21 V SS Ground. 22 CK Clock. Master clock input which is used to clock data into and out of the device. It also clocks the internal 11 bit counter. 23 V DD +5V supply input . 24 V SS Ground. 25,26 IC Internal Connection. Should be tied to VSS for normal operation. 27 FP Frame Pulse. An active low signal that serves as a synchronous clear for the internal 11 bit counter in all modes except Shift Register mode. The counter is cleared on a rising edge of CK. In the Shift Register mode, FP serves to align channel boundaries. VSS NC ODE ME Mx My Mz NC IC IC VSS VDD NC VSS D7o D6o D5o D4o VSS D3o D2o D1o D0o VSS CD A14 A13 A12 A11 A10 D8i D9i D10i D11i D13i D14i D15i VSS VSS IC CK VDD IC FP CS DS R/W DTA NC VSS D7i D6i D5i D4i VSS D3i D2i D1i VSS VDD D15o D14o D13o D12o VSS D1 1o D10o D9o D8o D0i

84 PIN PLCC

28 CS Chip Select. Active Low input. Selects the device for microport access in connect memory, data memory, external and shift register modes. Tying CS high will disable output data drivers (D0-D15o) in all modes except connect memory and shift register modes. 29 DS Data Strobe. Active low input. Indicates to the SMX that valid data is present on the microport data bus during a write operation or that the SMX must output data on a read operation. In Connect Memory modes, a low level applied to this input during a write operation indicates to the SMX that valid data is present on the microport data bus. During a read operation the low going signal indicates to the SMX that it must output data on the microport data bus. In Data Memory and External modes, when DS is high, the output data bus D0o-D15o will be disabled. The input data bus D0i-D15i is not affected. The DS input has no effect on the input and output busses in Counter or Shift Register modes. 30 R/W Read/Write Enable. Data is written into the device when R/W is low and read from it when it is high. This control input is disabled in data memory and shift register modes. It should be tied to V SS or VDD in these modes. In counter and external modes, the state of R/W pin is clocked in with the rising edge of CK. The actual read or write operation will be implemented on the next rising clock edge. 31 DTA Data Transfer Acknowledge. Open drain output which is pulled low to acknowledge completion of microport data transfer. On a read of the SMX, DTA low indicates that the SMX has put valid data on the data bus. On a write, DTA low indicates that the SMX has completed latching the data in. 32 NC No Connection. 33 V SS Ground. 34 NC No Connection. 35 ODE Output Data Enable. Control input which enables the output data bus. Pulling this input low will place the data bus in a high impedance state. The level on this pin is latched by a rising edge of CK. The output drivers will be enabled or disabled with the rising edge in the next timeslot (see Fig. 24 for applicable timing in different modes). 36 ME Message Enable. When tied high the data latched in on the address bus is clocked out on D0o-D15o. When ME is tied low, the contents of the addressed memory location will be output on the bus. The level on this pin is latched in with the rising edge of the clock. The actual mode change is implemented on the rising edge in the next timeslot. Refer to Figures 25 and 26 for more timing information. 37 Mx Mode X. One of three inputs which permit the selection of different operating modes for the device. Refer to Table 1 for description of various modes. 38 My Mode Y. See description for pin 37. 39 Mz Mode Z. See description for pin 37. 40 NC No Connection. 41, 42 IC Internal Connection. Leave open for normal operation. 43 V SS Ground. 44 V DD Supply Voltage. +5V . 45 NC No Connection. Pin Description Pin # Name Description

46-61 A0-A15 Address Bus. These inputs have three different functions. Inputs A0-A10 are used to address internal memory locations during read or write operations in all modes except Shift Register mode. In Shift Register mode, the levels latched in on A0-A10 program the delay through the device. When the ME pin is tied high, the data latched in on A0-A15 is clocked out on to the data bus (D0o-D15o). 62 CD Change Detect. Open drain output which is pulled low when a change in the memory contents from one frame to the next is detected by a Cyclic Redundancy Check (CRC). Changes in memory contents resulting from microprocessor access do not cause CD to go low. The output is reset to its normal high impedance state when the DS input is strobed, while the device has been selected (CS is low). 63 V DD Supply Voltage. +5V . 64 V SS Ground. 65-68 D0o-D3o Output Data Bus. These three state outputs are part of a 16 bit data bus which is used to clock out data from the device. Data is clocked out with the rising edge of the clock. See Figures 24 to 26 for timing information. The bus is actively driven when ODE is tied high. It is disabled when ODE is tied low. Tying CS high will also disable the output data bus in all modes except Connect Memory and Shift Register Modes. 69 V SS Ground. 70-73 D4o-D7o Output Data Bus. See description for pins 65-68. 74 V SS Ground. 75-78 D8o-D11o Output Data Bus. See description for pins 65-68. 79 V SS Ground. 80-83 D12o-D15 o Output Data Bus. See description for pins 65-68. 84 V DD Supply Voltage. +5V . Pin Description Pin # Name Description

microprocessor interface is also provided. available (see ME pin description). functionality in each mode is presented below. Table 1. SMX Modes of Operation first positive clock edge in the next timeslot (see Fig. further illustrated in Fig. 5.

This mode provides minimum delay through the SMX for any switching configuration. Data Memory Mode-2 Data Memory Mode-2 is designed for use in constructing a 1024 by 1024 channel double buffered switch. This mode is similar in most respects to Data Memory Mode-1. The double buffering is achieved by dividing the internal 2048 memory into two equal blocks. In a single frame, data is written into the first block and read from the second. In the next frame, the data will be written into the second and read from the first (see Figure 6). Frame sequence integrity of the data will be maintained for all switching configurations if the output frame is delayed by one channel with respect to the input frame. In this case, data clocked into the device during any of the channels in the current frame will be clocked out in the next frame. However, if the input and output frames are aligned, then data switched from any input channel to output channels 0 or 1 will be clocked out one frame after the next - consequently frame sequence integrity is not maintained for channels 0 or 1. Frame sequence integrity will be maintained for data switched to any of the other output channels. (See SMX/PAC Application Note, MSAN-135, for more information.) It is possible to switch between Data Memory Mode-1 and Mode-2 on a per timeslot basis. Data Memory Mode-3 This mode is similar to Data Memory Mode-1. However, there is no restriction on the minimum acceptable clock frequency or frame rate. In this mode, the size of the switching matrix depends on the clock and frame rates provided as per the following relationship: where S is the number of channels in the switching matrix F FP is the frame pulse frequency in Hz, and F CK is the clock frequency in Hz. The following table shows how the size of a switching matrix can be varied by selecting a suitable combination of clock and frame rates. It is not possible to switch between Data Memory Mode-3 and other modes on per-timeslot basis. Connect Memory Mode -1 In Connect Memory Mode-1, the input data bus is bidirectional. Internal memory locations can be randomly accessed via the microprocessor bus. The pinout of the device in this mode is illustrated in Figure 7. CK (kHz) FP (kHz) Number of channels in the switching matrix 16.384 16.384 16.384 12.288 12.288 8.192 8.192 2,048 1,024 512 1,536 768 1,024 512 S = FCK

2 X FFP

Figure 6 - Data Memory Mode-2 Functional Timing CK Data Input Data Output FRAME 0 FRAME 1 FRAME 2FRAME 1 FRAME 2 10230 1 102301 01 0 1 Written to Block 0 Written to Block 1 Read from Block 1 Read from Block 0 FRAME 0 Written to Block 1 Read from Block 0 1023 1023 Note: No input and output channel alignment is implied in the example shown above. It is assumed that the frame pulse for the connection memory used to generate adresses for the read operation has a specific phase relationship with respect to the Data Memory frame pulse.

Fig. 7 - Connect Memory Modes Pinout Data is clocked out on D0o-D15o from memory locations addressed sequentially by the internal counter. This counter is incremented every second clock period and is reset with FP . The frequency of the clock signal used should be twice the data rate. A timing diagram showing the relationship between the data output and the clock signal is presented in Fig. 8. With a clock rate of 16.384 MHz, the maximum number of addresses that can be generated in an 8 kHz frame period is 1024. Fig. 8 - Connect Memory Mode-1 Functional Timing Microprocessor access timing is shown in Figures 28 and 29. During a microprocessor read cycle, DS low indicates to the SMX that the processor is ready to receive data. The SMX responds by pulling DTA low when there is valid data present on the bus. The processor latches the data in and sets DS high. The SMX completes the bus cycle by disabling the DTA. DS should be kept low until after DTA is issued by the SMX. CS, R/W and the address lines should also be asserted for the duration of the access. A MPU write cycle is similar to the read cycle. Data will be latched into the device approximately three clock (CK) cycles after DS goes low. When the device has latched the data in, it will pull DTA low. DS can subsequently be set high. CK D0-D15 16 ODE ME Z Y X MODECD DTA CS DS R/W A0-A15 D0 o-D15o FP 0/1 1 0 Microprocessor Interface FP CK Data Out 1023 0 Connect Memory Mode-2 Connect Memory Mode-2 is designed specifically for 2048 channel switching applications. Data is clocked out on D0 o-D15o with every rising clock edge from memory locations addressed sequentially by the internal counter (see Figure 9). This counter is incremented with each clock period and is reset with FP or when a count of 2047 is reached. Fig. 9 - Connect Memory Mode-2 Functional Timing The clock frequency should be 16.384 MHz for a connection memory designed to support a 2048 channel switch. Microprocessor access is similar to Connect Memory Mode-1. Counter Mode This mode is designed for 2048 channel switching applications. In the counter mode all read and write addresses are generated sequentially by the internal 11 bit counter. The 11 bit counter is incremented with each clock pulse. It will wrap around when it reaches a count of binary 2047 or when it is reset by FP . The active input/output pins in this mode are illustrated in Fig. 10. Fig. 10 - Counter Mode Pinout A A A A A A A AA A A AA A A AA A A AA A A AA A A A A A A FP CK DATA OUTPUT 2047 0 1 2 D0 i-D15i CK FP D0 o-D15o CS ODE DTA CD R/W M E XYZ All other inputs should be tied Low 10 0

Figure 14 - Shift Register Mode Data Input/Output Timing CH X CH Y CH Z CH X CH Y CH Z td td = (Address x 2) + 2 Clock Cycles CK FP Data In Data Out

1024 Channel Switch Matrix

A 1024 channel, non-blocking, timeslot interchange switch can be constructed using two SMX devices (refer to Figure 15). One SMX is operated in the Data Memory mode, while the second device is operated in Connect Memory Mode-1. Data to be switched is clocked into the data memory via the 16 bit input data bus and stored sequentially in memory locations addressed by the internal 11 bit counter. The data is read out of the Data Memory (SMX#1) according to the external address supplied by the Connection Memory (SMX#2). The Connection memory clocks out contents of the memory according to the addresses supplied by the internal counter. The clock applied at the CK input of both the devices has a frequency of 16.384 MHz. There are two clock periods in each channel timeslot (see Figure 16). A framing signal (FP ) with a frequency of 8 kHz is used to delinate frames with 1024 channels each. The FP input to the Data Memory is delayed by seven clock periods from the Connection Memory frame pulse. This phase delay synchronizes the internal counters of the two SMXs such that the Connection Memory clocks out addresses one channel ahead of the affected timelsot. Using the connections illustrated in Figure 15, the Data Memory address and control functions can be mapped onto specific bits of the Connect Memory to form a 16 bit control word, as shown in Figure 17. The 16 bit control word is written into the Connection Memory by the processor. Subsequently, when the memory location is addressed by the internal counter, this word will be clocked out of the memory on to the data bus (D0 o-D15o). The output on the Connect Memory data bus (D0o-D9o) is used to specify the Data Memory location to be read out during any particular timeslot. The Connection Memory is programmed in a manner that permits specific addresses to be output in certain timeslots. The Data Memory will clock out data from internal memory locations according to the address asserted on its address bus. As mentioned earlier, this address is latched into Data Memory with a positive edge of the clock. The contents of the appropriate addressed memory location will be clocked out of the device at the beginning of the next channel timeslot. Connection Memory bit 10 controls the level on the ODE input. The ODE pin is used to enable the output drivers of the Data Memory. The capability to selectively enable or disable the output drivers during specific channel timeslots is required when constructing larger switches using the 1024 channel switch as a building block. The Message Enable (ME) input of the Data Memory is controlled by D11. Setting this particular bit high will result in the data latched into the address bus being clocked out on to the Data Memory output bus. Note that only 10 of the 16 address inputs are actually connected to the data bus of the Connection Memory. Consequently, only 10 of the 16 data output bits on the Data Memory can be dynamically controlled through the Connection Memory. In other applications, all 16 of the address bits may be connected to the data output bus of the Connection Memory. The mode of operation of the Data Memory can be changed from Data Memory Mode-1 to Data Memory Mode-2 by setting or resetting D12 in the connection

memory. The delay through the matrix can be optimized for specific applications by selectively enabling one of the two modes. Data Memory-1 (DM-1) is designed for voice switching applications where it is generally desirable to minimize delay through the switch. As mentioned earlier in the DM-1 description, the delay through the switch depends upon the difference between the input channel timeslot and the output channel timeslot. Consecutive output channels switched from non-contiguous input channels will not always originate from the same input frame. For example, if channels 3, 6 and 8 are to be switched to channels 5, 6 and 7; output channel 5 will contain data input in the current frame, while channels 6 and 7 will contain data clocked in one frame earlier. Data Memory-2 (DM-2) is designed for data switching applications where concatenation of a number of channels is often necessary. Data clocked out of the device will originate from the previous frame, regardless of the input/output time difference. There is one exception, when channel 1023 is switched to channel 0, the contents of Channel 0 will not originate from the previous frame but rather from the frame before it. The capability to selectively change between DM-1 and DM-2 allows a single switch to handle both voice and data effectively. External bus drivers can be controlled with D13 of the Connection Memory data bus. This bit will be output along with the remaining bits one channel Figure 15 - 1024 Channel Switch Matrix Parallel Input Data Parallel Output Data 1616 D0 i-D15i D0 o-D15o SMX #1 DM-1/2 DATA MEMORY A10-A15 R/W CS DS FP CK A0-A9 ODE ME Z Y X MODE External Tristate Control Timing Generator FP#1 CK FP#2 D0 o-D9o D10 o D11 o D12 o D13 o X Y Z MODE A11-A15 A10 CS CK FP CD D0-D15 R/W DTA DS A0-A9 SMX #2 CM-1 CONNECTION MEMORY Address Decode D0-D15 R/W HALT DS IRQ 16-BIT MPU Note: All other inputs not shown in this diagram should be connected to GND.

Switching any input channel to an output channel timeslot is possible by merely writing the address of the input channel in the Connection Memory location corresponding to the output channel timeslot. For example, to switch channel 1 to output channel 5 and enable output drivers during channel 5, the Connection Memory location corresponding to channel 5 should be loaded with Hex 2001. This word will be clocked out of the Connection Memory during timeslot 4 and will cause the Data Memory to clock out contents of the memory corresponding to channel 1 during the channel 5 timeslot. The 16 bit word clocked out by the Connection Memory will also enable Data Memory output drivers, and, external drivers.

2048 Channel Switch Matrix

A 2048 channel, double buffered timeslot interchange switch can be constructed with three SMXs as shown in Figure 18. SMX#1 and SMX#2 are used to store data and switch it in time, while the third SMX functions as a Connection Memory. SMX#1 and 2 are operated in the Counter Mode and External Mode alternatively in consecutive frames. In any specific frame, one of the two is in Counter mode while the other is in External mode. The functions are reversed in the successive frame. The SMX in counter mode is programmed to write data Figure 18 - 2048 Channel Timeslot Interchange Circuit CM-2 SMX #3 D11 D0o-D10o ODE Mz My Mx FP CK C16 MPU Interface CONNECTION MEMORY 1111 161616 C16 +5 C16 C16 D0-D15i CK FP Mz R/W ODE A0-A10ME D0-D15o Mx My CS DS CNT/EXT SMX #1 D0-D15i CK FP Mz R/W ODE A0-A10ME D0-D15o Mx My CS DS CNT/EXT SMX #2 Data Output DATA MEMORY DATA MEMORY Timing Generator DFP CFP

16.384 MHz

Notes: 1) U1 and U2 are required if the data output bus is to be enabled/disabled via the microprocessor interface. 2) All inputs not shown should be connected to Ground (V SS ). DTA DS R/W CS A0-A15 CD D0-D15

Parallel-to-Serial Conversion The SMX can be used in systems which employ serial architectures by converting the parallel I/O into a serial format. The Mitel MT9085 Parallel Access Circuit (PAC) is designed to interface to the parallel busses of the SMX. A single PAC can convert the output of a1024 channel switch into 2.048 Mbit/s or 4.096 Mbit/s serial format. A second PAC can be configured to implement serial to parallel conversion (see Figure 23). The PAC generates all framing signals required to implement a 1024 or 2048 channel matrix. Refer to the MT9085 data sheet for more information on operation of the PAC. For more information, see Mitel’s Application Note MSAN-135 “Design of Large Digital Switching Matrices using the SMX/PAC“. Figure 23 - 1024 Channel Serial Switch Matrix Using the PAC and SMX Timing Source C4i C16i S31 /4S OE CKD MCA MCB P0-P7 DFPo CFPo PAC S/P F0i S31 C16 C16 D0-D7i CK FP Mz R/W ODE A0-A9 ME D0-D7o Mx My CS DS SMX #1 DM - 1/2 F0 C4 C16 F0i C4i C16i P0-P7 OE CKD MCA MCB 2/4S S31 S31 PAC P/S SMX #2 CM - 1 D12 D0-D9 D11 D10 ODE Mx My Mz FP CK C16 MPU Interface NOTE: Connect all inputs not shown to VSS CONNECTION MEMORY DATA MEMORY DTA DS R/W CS A0-A15 CD D0-D15

• Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings* Parameter Symbol Min Max Units 1 Supply Voltage VDD -VSS VDD -0.3 7 V 2 All Input Voltages V i VSS -0.3 V DD +0.3 V 3 All Output Voltages V o VSS -0.3 V DD +0.3 V

4 Storage Temperature Range T S -40 125 °C

5 Current at Digital Outputs I O 150 mA

6 Continuous Power Dissipation P D 2W

Recommended Operating Conditions - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 Supply Voltage V DD 4.75 5.0 5.75 V

2 Operating Temperature T OP -40 70 °C

3 Input High Voltage V IH 0.7VDD V 4 Input low Voltage V IL 0 0.3VDD V Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Supply Current I DD 120 200 mA Outputs unloaded

2 Input High Voltage V IH 0.7VDD V 3 Input Low Voltage V IL 00 . 3 V DD V

4 Input Leakage Current I IL ±10 µA

5 Output High Current (all outputs

except D0i-D15i) IOH 8m A V OH =0.7 VDD

6 Output Low Current (all outputs

except DTA, CD and D0i-D15i) IOL 8m A V OL =0.3 VDD 7 Output High Current D0i-D15i I OH 2m A V OH =0.7 VDD 8 Output Low Current DTA & CD IOL 2m A V OL =0.3 VDD

9 Input Capacitance C i 10 pF

10 Output Pin Capacitance C o 10 pF V DD =5.0V±10%.

11 High Impedance Leakage I OZ 10 µA

† Timing is over recommended temperature and power supply voltages. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Figure 24 - Output Drive Enable Timing to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 ODE Setup t OS 0n s

2 ODE Hold t OH 20 ns

3 Data Output High Z to Active t DZA 35 ns C L=30pF

4 Data Output Active to High Z t DAZ 30 ns

1. Data Memory Modes And Connect Memory Mode - 1 2. Counter, External And Connect Memory Mode - 2 CK ODE D0o- D15o CK ODE D0o- D15o HIGH IMPEDANCE STATE - OUTPUT DRIVERS DISABLED CHANNEL N CHANNEL N + 1 tOS tOH tOS tOH tDZA 90% 10% tDAZ CHANNEL CHANNEL NN + 2 CHANNEL N + 1 tOS tOH tOS tOH tOS tOH tDZA tDAZ 90% 10%

† Timing is over recommended temperature and power supply voltages. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Figure 25 - Data Memory, Connect Memory-1 and Shift Register Mode Timing † Timing is over recommended temperature and power supply voltages. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Mode Timing (See Fig. 25) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Address Setup t AS 0n s

2 Address Hold t AH 18 ns

3 Data Output Delay t DD 93 4 n s C L = 30 pF

4 Data Input Setup t DS 0n s

5 Data Input Hold t DH 4n s

6 ME, Mx, My, Mz Setup t MES 0n s

7 ME, Mx, My, Mz Hold t MEH 26 ns

8 CK Clock Period t PCK 60 ns

(See Fig. 26) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 ADDR, R/W Hold Time t WEH 10 ns

2 ADDR,R/W Setup Time t WES 2n s

3 Data Setup t DS 0n s

4 Data Hold t DH 4n s

5 Data Output Delay t DD 93 4n s C L = 30 pF

A0-A15* ME/Mx/y/z D0o-D15o D0i-D15i* tAS tDH tDS tDH tAH tAH tAS tMES tMEH tAS tMEH tMES tDDtDD tDS tPCK Channel Timeslot *Timing applicable to Data Memory and Shift Register modes only.

Figure 26 - External, Connect Memory-2 and Counter Mode Timing † Timing is over recommended temperature and power supply voltages. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Figure 27 - Address Bus Timing in Shift Register Mode Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

2 Address Hold t AH 12 ns

3 Chip Select Setup t CSS 0n s

4 Chip Select Hold t CSH 0n s

A0-A15*, R/W ME/Mx/y/z D0i-D15i D0o-D15o Timing applicable to External mode only. Timing applicable to External and Counter modes. tWES tWEHtWES tMES tMES tMEH tMEH tDS tDH tDS tDH tDDtDD tWEH Channel Timeslot CS DS A0-A15 tCSHtCSS tAS tAH

*T CK = Clock (CK) Period † Timing is over recommended temperature and power supply voltages. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Figure 28 - Microprocessor Read Timing for Connect Memory Mode, Data Memory Mode and External Mode Memory & External Modes (See Fig. 28) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Chip Select Setup t CSS 0n s

2 Chip Select Hold t CSH 0n s

3 ADDR, R/W Setup t AS 0n s

4 ADDR, R/W Hold t AH 0n s

5D T A Delay t DTAD 4.5 9 T CK * 6D T A Hold t DTAH 0n s

7 Valid Data Out to DTA Low t RD 3T CK *

8D S High to Data Invalid t DH 02 7 n s

9 Output Data Active to High Z t DHZ 31 ns

A0-A15, R/W DTA Data Bus* tCSS tCSH tAS tAH tDTAD tDTAH tRD tDHZ tDH * In Data Memory Mode and External Mode, data is clocked out on D0o-D15o; in Connect Memory Mode data is clocked out on D0i-D15i (bidirectional).

*T CK = Clock (CK) Period † Timing is over recommended temperature and power supply voltages. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Figure 29 - Microprocessor Write Timing for Connect Memory Mode (See Fig. 29) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 5D T A Delay t DTAD 4.5 7.5 T CK * 6D T A Hold t DTAH 0n s 7D S Low to Data in Delay t DD 4.5 T CK * 8D T A Low to Data in Hold t DH 0n s 9D S Hold Time t DSH 0n s DS CS A0-A15,R/W DTA D0-D15i tCSS tAS tDSH tCSH tAH tDTAD tDH tDTAH* tDD * This parameter is specified with respect to the rising edge of DS or CS depending on which signal goes high first.

† Timing is over recommended temperature and power supply voltages. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Figure 30 - Frame Pulse and Change Detect Timing 30) - Voltages are with respect to Ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Frame Pulse Setup t FPS 6n s

2 Frame Pulse Hold t FPH 3n s

3 Change Detect Delay t CDD 38 ns

4 Change Detect Reset Delay t CDRD 01 3 n s

tCDD* tCDRD * Assumes change in memory contents detected in previous frame

NOTES: