MT9041

MT9041 MITEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

Features

• Provides T1 and E1 clocks, and ST-BUS/GCI framing signals locked to an input reference of either 8 kHz (frame pulse), 1.544 MHz (T1), or

2.048 MHz (E1)

• Meets AT & T TR62411 and ETSI ETS 300 011 specifications for a 1.544 MHz (T1), or

2.048 MHz (E1) input reference

• Typical unfiltered intrinsic output jitter is

0.013 UI peak-to-peak

• Jitter attenuation of 15 dB @ 10 Hz, 34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz
• Low power CMOS technology

Applications

• Synchronization and timing control for T1 and E1 digital transmission links
• ST-BUS clock and frame pulse sources
• Primary Trunk Rate Converters

Description

The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.544 MHz, or 8 kHz reference. The T1 and E1 outputs are fully compliant with AT & T TR62411 (ACCUNET ® T1.5) and ETSI ETS 300 011 intrinsic jitter and jitter transfer specifications, respectively, when synchronized to primary reference input clock rates of either 1.544 MHz or 2.048 MHz. The PLL also provides additional high speed output clocks at rates of 3.088 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz for backplane synchro- nization.

Ordering Information

-40°C to +85°C ISSUE 1 May 1995 MT9041 Multiple Output Trunk PLL Advance Information

MT9041 Advance Information 3-84 Figure 2 - Pin Connections Pin Description Pin # Name Description 1V SS Negative Power Supply Voltage. Nominally 0 Volts. 2,3 IC0 Internal Connection 0. Connect to VSS. 4P R I Primary Reference Input (TTL compatible). This input (either 8 kHz, 1.544 MHz, or 2.048 MHz as controlled by the input frequency selection pins) is used as the primary reference source for PLL synchronization. 5V DD Positive Supply Voltage. Nominally +5 volts. 6M C L K o Master Clock Oscillator Output. This is a CMOS buffered output used for driving a 20 MHz crystal. 7M C L K i Master Clock Oscillator Input. This is a CMOS input for a 20 MHz crystal or crystal oscillator. Signals should be DC coupled to this pin. 8 FP8-GCI Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that indicates the start of the active GCI-BUS frame. The pulse width is based upon the period of the 8.192 MHz synchronization clock. 9F 0 o Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 4.096 MHz synchronization clock. This is an active low signal. 10 FP8-STB Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 8.192 MHz synchronization clock. 11 C1.5 Clock 1.544 MHz (CMOS compatible). This ouput is a 1.544 MHz (T1) output clock locked to the reference input signal. 12 C3 Clock 3.088 MHz (CMOS compatible). This output is a 3.088 MHz output clock locked to the reference input signal. 13 C2 Clock 2.048 MHz (CMOS compatible). This output is a 2.048 MHz (E1) output clock locked to the reference input signal. 14 C4 Clock 4.096 MHz (CMOS compatible). This output is a 4.096 MHz output clock locked to the reference input signal. 15 V SS Negative Power Supply Voltage. Nominally 0 Volts. 16 C8 Clock 8.192 MHz (CMOS compatible). This output is an 8.192 MHz output clock locked to the reference input signal. 432

262728 VSS

C1.5 IC0 IC1 IC0 IC0 MS IC0 IC0 FSEL2 FSEL1 RST 12 13 14 15 16 17 18 VSS C16 VDD

Advance Information MT9041 3-85 17 C16 Clock 16.384 MHz (CMOS compatible). This output is a 16.384 MHz output clock locked to the reference input signal. 18 V DD Positive Supply Voltage. Nominally +5 volts. 19 IC0 Internal Connection 0. Connect to VSS. 20 IC1 Internal Connection 1. Leave open circuit. 21, 22 IC0 Internal Connection 0. Connect to VSS. 23 MS Mode Select Input (TTL compatible). This input selects the PLL mode of operation (i.e. , NORMAL or FREERUN, see Table 1). 24, 25 IC0 Internal Connection 0. Connect to VSS. 26 FSEL2 Frequency Select - 2 Input (TTL compatible). This input, in conjunction with FSEL1, selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz; see Table 3). 27 FSEL1 Frequency Select - 1 Input (TTL compatible). This input, in conjunction with FSEL2, selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz; see Table 3).

28 RST

Reset (TTL compatible). This input (active LOW) puts the MT9041 in its reset state. To guarantee proper operation, the device must be reset after power-up. The time constant for a power-up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RST pin must be held low for a minimum of 60 nsec to reset the device. Pin Description (continued) Pin # Name Description

MT9041 Advance Information 3-86 Functional Description The MT9041 is a fully digital, phase-locked loop designed to provide timing references to interface circuits for T1 and E1 Primary Rate Digital Transmission links. As shown in Figure 1, the PLL employs a high resolution Digitally Controlled Oscillator (DCO) to generate the T1 and E1 outputs. The interface circuit on the output of the DCO generates 1.544 MHz (C1.5), 3.088 MHz (C3 ), 2.048 MHz (C2), 4.096 MHz (C4), 8.192 MHz (C8), 16.384 MHz (C16), and three 8 kHz frame pulses F0o, FP8- STB, and FP8-GCI. Figure 3 - PLL Block Diagram As shown in Figure 3, the PLL of the MT9041 consists of a phase detector (PD), a loop filter, a high resolution DCO, and a digital frequency divider. The digitally controlled oscillator (DCO) is locked in frequency (n x f ref) to one of three possible reference frequencies, configured using pins FSEL1 and FSEL2. The PLL is capable of providing a full range of E1/T1 clock signals synchronized to the primary PRI input. The loop filter is a first order lowpass structure that provides approximately a 2 Hz bandwidth. Modes of Operation The MT9041 can operate in one of two modes, NORMAL or FREERUN, as controlled by mode select pin MS (see T able 1). Normal Mode There are three possible input frequencies for selection as the primary reference clock. These are 8 kHz, 1.544 MHz or 2.048 MHz. Frequency selection MS Description of Operation 0N O R M A L 1F R E E R U N Table 1- Operating Modes of the MT9041 Divider DCOPhase Loop Filterfref fsync Detector is controlled by the logic levels of FSEL1 and FSEL2, as shown in Table 2. This variety of input frequencies was chosen to allow the generation of all the necessary T1 and E1 clocks from either a T1, E1 or frame pulse reference source. PLL Measures of Performance To meet the requirements of AT & T TR62411 and ETSI 300 011, the following PLL performance parameters were measured:

• locking range and lock time
• free-run accuracy
• intrinsic jitter
• jitter transfer function
• output jitter spectrum
• wander Locking Range and Lock Time The locking range of the PLL is the range that the input reference frequency can be deviated from its nominal frequency while the output signals maintain synchronization. The relevant value is usually specified in parts-per-million (ppm). For both the T1 and E1 outputs, lock was maintained while an 8 kHz input was varied between 7900 Hz to 8100 Hz (corresponding to ±12500 ppm). This is well beyond the required ±100 ppm. The lock range of 12500 ppm also applies to 1.544 MHz and 2.048 MHz reference inputs. The lock time is a measure of how long it takes the PLL to reach steady state frequency after a frequency step on the reference input signal. The locking time is measured by applying an 8000 Hz signal to the primary reference and an 8000.8 Hz (+100 ppm) to the secondary reference. The output is monitored with a time interval analyzer during slow periodic rearrangements on the reference inputs. The lock time for both the T1 and E1 outputs is approximately 311 ms, which is well below the required lock time of 1.0 seconds. FSEL FSEL Input Reference Frequency

00 R e s e r v e d

1 0 1.544 MHz 1 1 2.048 MHz Table 2 - Input Frequency Selection of the MT9041

Advance Information MT9041 3-87 Freerun Accuracy The Freerun accuracy of the PLL is a measure of how accurately the PLL can reproduce the desired output frequency. The freerun accuracy is a function of master clock frequency which must be 20 MHz ±32 ppm in order to meet AT & T TR62411 and ETSI specifications. Jitter Performance The output jitter of a digital trunk PLL is composed of intrinsic jitter, measured using a jitter free reference clock, and frequency dependent jitter, measured by applying known levels of jitter on the references clock. The jitter spectrum indicates the frequency content of the output jitter. Intrinsic Jitter Intrinsic jitter is the jitter added to an output signal by the processing device, in this case the enhanced PLL. Tables 3 and 4 show the average measured intrinsic jitter of the T1 and E1 outputs. Each measurement is an average based upon a ±100 ppm deviation (in steps of 20 ppm) on the input reference clock. Jitter on the master clock will increase intrinsic jitter of the device, hence attention to minimization of master clock jitter is required. Jitter Transfer Function The jitter transfer function is a measure of the transfer characteristics of the PLL to frequency specific jitter on the referenced input of the PLL. It is directly linked to the loop bandwidth and the magnitude of the phase error suppression characteristics of the PLL. It is measured by applying jitter of specific magnitude and frequencies to the input of the PLL, then measuring the magnitude of the output jitter (both filtered and unfiltered) on the T1 or E1 output. Care must be taken when measuring the transfer characteristics to ensure that critical jitter alias frequencies are included in the measurement (i.e., for digital phase locked loops using an 8 kHz input). T ables 5 and 6 provide measured results for the jitter transfer characteristics of the PLL for both a 1.544 MHz and 2.048 MHz reference input clock. The transfer characteristics for an 8 kHz reference input will be the same. Figures 4 and 5 show the jitter attenuation performance of the T1 and E1 outputs plotted against AT & T TR62411 and ETSI requirements, respectively. Output Jitter in UIp-p Reference Input FLT0 Unfiltered FLT1 10Hz - 8kHz FLT2 10Hz - 40kHz FLT3 8kHz - 40kHz 8 kHz .011 .004 .006 .002 Table 3 -Typical Intrinsic Jitter for the T1 Output Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Output Jitter in UIp-p Reference Input FLT0 Unfiltered FLT1 20Hz - 100kHz FLT2 700Hz - 100kHz 8 kHz .011 .002 .002 1.544 MHz .011 .002 .002 2.048 MHz .011 .002 .002 Table 4 - Typical Intrinsic Jitter for the E1 Output Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

MT9041 Advance Information 3-88 Input Jitter Modulation Frequency (Hz) Input Jitter Magnitude (UIp-p) Measured Jitter Output (UIp-p) T1 Reference Input E1 Reference Input Output Jitter Magnitude (UIp-p) Jitter Attenuation (dB) Output Jitter Magnitude (UIp-p) Jitter Attenuation (dB) 10 20 2.42 18.34 2.41 18.38 20 20 1.62 21.83 1.618 21.84 40 20 .900 26.94 .908 26.86 100 20 .375 34.54 .376 34.52 330 10 .060 44.44 .060 44.44 500 8 .032 47.96 .032 47.96 1000 7 .015 53.38 .015 53.38 Table 5 - Typical Jitter Transfer Function for the T1 Output Notes 1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output signal, rendering the jitter transfer function unmeasurable. 2) Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Advance Information MT9041 3-89 Input Jitter Modulation Frequency (Hz) Input Jitter Magnitude (UIp-p) Measured Jitter Output (UIp-p) T1 Reference Input E1 Reference Input Output Jitter Magnitude (UIp-p) Jitter Attenuation (dB) Output Jitter Magnitude (UIp-p) Jitter Attenuation (dB) Table 6 - Typical Jitter Transfer Function for the E1 Output Notes 1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output signal, rendering the jitter transfer function unmeasurable. 2) Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Output jitter dominated by intrinsic jitter.

Advance Information MT9041 3-91 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings*- Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Symbol Min Max Units 1 Supply Voltage V DD -0.3 7.0 V 2 Voltage on any pin V I VSS -0.3 V DD +0.3 V

3 Input/Output Diode Current I IK/OK ±150 mA

4 Output Source or Sink Current I O ±150 mA

5 DC Supply or Ground Current I DD /ISS ±300 mA

6 Storage Temperature T ST -55 125 °C

7 Package Power Dissipation PLCC P D 900 mW

Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 Supply Voltage V DD 4.5 5.0 5.5 V 2 Input HIGH Voltage V IH 2.0 V DD V 3 Input LOW Voltage V IL VSS 0.8 V

4 Operating Temperature T A -40 25 85 °C

VDD =5.0 V±10%; VSS =0V; TA =-40 to 85°C. Characteristics Sym Min Typ ‡ Max Units Test Conditions S U P Supply Current IDD 55 mA Under operating condition 2 I N Input HIGH voltage V IH 2.0 V 3 Input LOW voltage V IL 0.8 V 4 O U T Output current HIGH I OH -4 mA V OH =2.4 V 5 Output current LOW I OL 4m A V OL =0.4 V

6 Leakage current on all inputs I IL 10 µA VIN=V SS

MT9041 Advance Information 3-92 Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 8 kHz reference clock period t P8R 125 µs I N P U T S

1.544 MHz reference clock period tP15R 648 ns

3 2.048 MHz reference clock period t P20R 488 ns

4 Input to output propagation delay

with an 8 kHz reference clock tPD8 183 ns MCLKi = 20.000 000MHz

5 Input to output propagation delay

with a 1.544 MHz reference clock tPD15 243 ns MCLKi = 20.000 000MHz

6 Input to output propagation delay

with a 2.048 MHz reference clock tPD20 183 ns MCLKi = 20.000 000MHz

7 Input rise time (except MCLKi) 8 ns

8 Input fall time (except MCLKi) 8 ns

9 Delay between C1.5 and C2 t D-20-15 18 ns

10 Frame pulse F0o output pulse

11 Frame pulse F0o output rise time tR-F0o 5 9 ns Load = 85pF

12 Frame pulse F0o output fall time tF-F0o 5 9 ns Load = 85pF

13 Frame pulse FP8-STB output

pulse width tW-FP8STB 122 ns

14 Frame pulse FP8-STB output rise

time tR-FP8STB 59n s Load = 85pF

15 Frame pulse FP8-STB output fall

time tF-FP8STB 59n s Load = 85pF 16 O U T P U T S Frame pulse FP8-GCI output pulse width tW-FP8GCI 122 ns

17 Frame pulse FP8-GCI output rise

time tR-FP8GCI 59n s Load = 85pF

18 Frame pulse FP8-GCI output fall

time tF-FP8GC I 59n s Load = 85pF 19 C1.5 clock period t P-C1.5 648 ns 20 C1.5 clock output rise time t RC1.5 5 9 ns Load = 85pF 21 C1.5 clock output fall time t FC1.5 5 9 ns Load = 85pF 22 C1.5 clock output duty cycle 50 % 23 C3 clock period t P-C3 324 ns

24 C3 clock output rise time t RC3 5 9 ns Load = 85pF

25 C3 clock output fall time t FC3 5 9 ns Load = 85pF

26 C3 clock output duty cycle 50 %

27 C2 clock period t P-C2 488 ns

28 C2 clock output rise time t RC2 5 9 ns Load = 85pF

29 C2 clock output fall time t FC2 5 9 ns Load = 85pF

30 C2 clock output duty cycle 50 %

Advance Information MT9041 3-93 † -Timing is over recommended temperature & power supply voltages.‡ -Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

31 C4 clock period t P-C4 244 ns

32 C4 clock output rise time t RC4 5 9 ns Load = 85pF

33 C4 clock output fall time t FC4 5 9 ns Load = 85pF

U T P U T S C4 clock output duty cycle 50 %

35 C8 clock period t P-C8 122 ns

36 C8 clock output rise time t RC8 5 9 ns Load = 85pF

37 C8 clock output fall time t FC8 5 9 ns Load = 85pF

38 C8 clock output duty cycle 50 %

39 C16 clock period t P-C16 61 ns

40 C16 clock output rise time t RC16 5 9 ns Load = 85pF

41 C16 clock output fall time t FC16 5 9 ns Load = 85pF

42 C16 clock output duty cycle 43 50 55 % Duty cycle on

MCLKi =50% Characteristics Sym Min Typ ‡ Max Units Test Conditions

MT9041 Advance Information 3-94 Figure 6 - Timing Information for MT9041 C16 C1.5 tP-C8 tW-FP8STB tP-C16 tP-C4 tW-F0o tW-FP8GCI tPD-20 FP8-GCI FP8-STB F0o PRI-2.048 MHz PRI-1.544 MHz tPD-15 tPD-8 PRI- 8 kHz tD-20-15 tP-C2 tP-C3 tP-C1.5

Advance Information MT9041 3-95 † Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing Figure 7 - Master Clock Input Characteristics Sym Min Typ ‡ Max Units Test Conditions L O C K Master clock input rise time t rMCLKi 4n s

2 Master clock input fall time t fMCLKi 4n s

3 Master clock frequency t pMCLKi 19.99936 20 20.000640 MHz

4 Duty Cycle of the master clock 40 50 60 %

2.4V 1.5V 0.4V trMCLK tfMCLK

MT9041 Advance Information 3-96 Notes: