MT89L80AN

MT89L80 ZARLINK | Alldatasheet

Document overview

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Technical content

Features

• 3.3 volt supply
• 5 V tolerant inputs and TTL compatible outputs.
• 256 x 256 channel non-blocking switch
• Accepts serial streams at 2.048 Mb/s
• Per-channel three-state control
• Patented per channel message mode
• Non-multiplexed microprocessor interface
• Zarlink ST-BUS compatible
• Low power consumption: typical 15 mW
• Pin compatible with the MT8980DP

Applications

• Key telephone systems
• PBX systems
• Small and medium voice switching systems

Description

This VLSI CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digi tal exchange, PBX or Central Office. It provides simultaneous connections for up to 256 64 kbit/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream. In addition, the MT89L80 provi des microprocessor read and write access to individual ST-BUS channels. Sept. 2006

Ordering Information

MT89L80ANR 48 Pin SSOP Tape & Reel MT89L80APR 44 Pin PLCC Tape & Reel MT89L80AP 44 Pin PLCC Tubes MT89L80AN 48 Pin SSOP Tubes MT89L80APR1 44 Pin PLCC* Tape & Reel MT89L80ANR1 48 Pin SSOP* Tubes MT89L80AN1 48 Pin SSOP* Tubes MT89L80AP1 44 Pin PLCC* Tubes *Pb Free Matte Tin -40°C to +85 °C CMOS ST-BUSTM Family MT89L80 Digital Switch Data Sheet Figure 1 - Functional Block Diagram STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 Serial to Parallel Converter Data Memory Frame Counter Control Register Control Interface Output MUX Connection Memory Parallel to Serial Converter CS R/W A5/ DTA D7/ CSTo C4i F0i VDD VSS ODE STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 DS RESET ** for 48-pin SSOP only

Zarlink Semiconductor Inc. Figure 2 - Pin Connections Pin Description Pin # Name Description44 PLCC SSOP 22 DTA Data Acknowledgment (5 V Tolerant Three-state Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. 3-5 3-5 STi0-2 ST-BUS Inputs 0 to 2 (5 V-tolerant Inputs). Serial data input streams. These streams have data rates of 2.048 Mbit/s with 32 channels. 7-11 7-11 STi3-7 ST-BUS Inputs 3 to 7 (5 V-tolerant Inputs). Serial data input streams. These streams may have data rates of 2.048 Mbit/s with 32channels. 12 12,36 V DD +3.3 Volt Power Supply. 13 RESET Device Reset (5 V-tolerant input). This pin is only available for the 48-pin SSOP package.This active low input puts the device in its reset state. It clears the internal counters and registers. All ST-BUS outputs are set to the high impedance state. In normal operation. The RESET pin must be held low for a minimum of 100nsec to reset the device. Internal pull-up. 13 14 F0i Frame Pulse (5 V-tolerant Input). This is the input for the frame synchronization pulse for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on the next negative transition of C4i. 17 29 STi3 STi4 STi5 STi6 STi7 V DD F0i C4i STo3 STo4 STo5 STo6 STo7 V SS NC STi1 DTA ODE STo1 NC NC DS CS NC R/W

44 PIN PLCC

48 PIN SSOP

V SS VDD NC DTA STi0 STi1 STi2 NC STi3 STi4 STi5 STi6 STi7 V DD RESET F0i C4i NC

48 CSToVSS

27 D7A5 22

26 CSDS 23

25 VSSR/W 24

(JEDEC MO-118, 300mil Wide)

Zarlink Semiconductor Inc. Functional Description In recent years, there has been a trend in telephony towa rds digital switching, partic ularly in association with software control. Simultaneously, there has been a trend in system architectures towards distributed processing or multi-processor systems. In accordance with these trends, Zarlin k has devised the ST-BUS (Serial Telecom Bus). This bus architecture can be used both in software-controlled digital voice and da ta switching, and for interprocessor communications. The uses in switching and in interprocessor communication s are completely integrated to allow for a simple general purpose architecture appropriate for the systems of the future. 14 15 C4i 4.096 MHz Clock (5 V-tolerant Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this clock. 15-17 16-18 A0-2 Address 0-2 / Input Streams 8-10 (5 V-tolerant Input). These are the inputs for the address lines on the microprocessor interface. 19-21 20-22 A3-5 Address 3-5 / Input Streams 11-13 (5 V-tolerant Input). These are the inputs for the address lines on the microprocessor interface. 22 23 DS Data Strobe (5 V-tolerant Input). This is the input for the active high data strobe on the microprocessor interface. 23 24 R/W Read/Write (5 V-tolerant Input). This is the input for the read/write signal on the microprocessor interface - high for read, low for write. 24 26 CS Chip Select (5 V-tolerant Input). This is the input for the active low chip select on the microprocessor interface 25-27 27-29 D7-D5 Data Bus (5 V-tolerant I/O): These are the bidirectional data pins on the microprocessor interface. 29-33 31-35 D4-D0 Data Bus (5 V-tolerant I/O): These are the bidirectional data pins on the microprocessor interface. 34 1, 25,37 VSS Ground. 35-39 38-42 STo7-3 ST-BUS Outputs 7 to 3 (5 V-Tolerant Three-state Outputs). These are the pins for the eight 2048 kbit/s ST-BUS output streams. 41-43 44-46 STo2-0 ST-BUS Outputs 2to 0 (5 V-Tolerant Three-state Outputs). These are the pins for the eight 2048kbit/s ST-BUS output streams. 44 47 ODE Output Drive Enable (5 V-tolerant Input). If this input is held high, the STo0-STo7 output drivers function normally. If this input is low, the STo0-STo7 output drivers go into their high impedance state. NB: Even when ODE is high, channels on the STo0-STo7 outputs can go high impedance under software control. 1 4 8 CSTo Control ST-BUS Output (5 V-Tolerant Output). Each frame of 256 bits on this ST-BUS output contains the values of bit 1 in the 256 locations of the Connection Memory High. 6, 18, 28, 40 6, 19, 30, 43 NC No Connection. Pin Description (continued) Pin # Name Description44 PLCC SSOP

Zarlink Semiconductor Inc. The serial streams of the ST-BUS operate cont inuously at 2048 kbit/s and are arranged in 125 µs wide frames which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST-BUS; a key device being the MT89L80 chip. The MT89L80 can switch data from channels on ST-BUS inputs to channels on ST-BUS outputs, and simultaneously allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST- BUS outputs (Message Mode). To the microprocessor , the MT89L80 looks like a memory peripheral. The microprocessor can write to the MT89L80 to establish switched connections between input ST-BUS channels and output ST-BUS channels, or to transmit messages on output ST-BUS channels. By reading from the MT89L80, the microprocessor can receive messages from ST-BUS inpu t channels or check which switched connections have already been established. By integrating both switching and interprocessor commu nications, the MT89L80 allows systems to use distributed processing and to switch voice or data in an ST-BUS architecture. Hardware Description Serial data at 2048 kbit/s is received at the eight ST-BUS inputs (STi0 to STi7), and serial data is transmitted at the eight ST-BUS outputs (STo0 to STo7). Each serial in put accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encod ed analog/voice sample as provided by a codec (e.g., Zarlink’s MT8964). This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory. Locations in the Data Memory are associated with particular channels on partic ular ST-BUS input streams. These locations can be read by the microprocessor which controls the chip. Locations in the Connection Memory, which is split into hi gh and low parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input, then the contents of the Connection Memory Low location associated with the output channel is used to address the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode), then the contents of the Connection Memory Low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes. The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives address information at A5 to A0 and handles the microprocessor control signals CS , DTA, R/W and DS. There are two parts to any address in the Data Memory or Connecti on Memory. The higher order bits come from the Control Register, which may be written to or read from via the Control Interface. The lower order bits come from the address lines directly. The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the Connection Memory Low. The Connection Memory High de termines whether individual output channels are in Message Mode, and allows individual output channels to go into a high-imp edance state, which enables arrays of MT89L80s to be constructed. It also controls the CSTo pin. All ST-BUS timing is derived from the two signals C4i and F0i.

Zarlink Semiconductor Inc. Figure 3 - Address Memory Map Software Control The address lines on the Control Interface give access to the Control Register directly or, depending on the contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory. If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory and stream selected in the Control Register. The data in the Control Register consists of mode contro l bits, memory select bits, and stream address bits (see Fig. 4). The memory select bits allo w the Connection Memory High or Low or the Data Memory to be chosen, and the stream address bits define one of the ST-BUS input or output streams. Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the Connection Memory Low. The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e., the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1, regardless of the actual values. A5 A4 A3 A2 A1 A0 Hex Address Location 00 - 1F Control Register * Channel 0 Channel 1† Channel 31 * Writing to the Control Register is the only fast transaction. † Memory and stream are specified by the contents of the Control Register. Bit Name Description

7 Split Memory When 1, all subsequent reads are from the Data Memory and writes are to the Connection

Memory Low, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available. 76 5432 10 Mode Control Bits (unused) Memory Select Bits Stream Address Bits

Zarlink Semiconductor Inc. Figure 4 - Control Register Bits Figure 5 - Connection Memory High Bits

6 Message

When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when the ODE pin is low. When 0, the Connection Memory bits for each channel determine what is output. 5 (unused) 4-3 Memory Select Bits 0-0 - Not to be used 0-1 - Data Memory (read only from the microprocessor port) 1-0 - Connection Memory Low 1-1 - Connection Memory High 2-0 Stream Address Bits The number expressed in binary notation on these bits refers to the input or output ST-BUS stream which corresponds to the subsection of memory made accessible for subsequent operations. Bit Name Description

2 Message

When 1, the contents of the corresponding location in Connection Memory Low are output on the location’s channel and stream. When 0, the contents of the corresponding location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location’s channel and stream. 1 CSTo Bit This bit is output on the CSTo pin one c hannel early. The CSTo bit for stream 0 is output first.

0 Output

If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the output driver for the location’s channel and stream. This allows individual channels on individual streams to be made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it. Bit Name Description 76 5432 10 Mode Control Bits (unused) Memory Select Bits Stream Address Bits 76 5432 1 0 No Corresponding Memory - These bits give 0s if read. Per Channel Control Bits

Zarlink Semiconductor Inc. Figure 6 - Connection Memory Low Bits If bit 6 of the Control Register is 0, then bits 2 an d 0 of each Connection Memory High location function normally (see Fig. 5). If bit 2 is 1, the associated ST-BUS out put channel is in Message Mode; i.e., the byte in the corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the ST- BUS input stream and channel where the byte is to be found (see Fig. 6). If the ODE pin is low, then all serial outputs are high-impedance. If it is high and bit 6 in the Control Register is 1, then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the Connection Memory High location enables the output dr ivers for the corresponding individual ST-BUS output stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5). Bit 1 of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS streams, and the bit for stream 0 is output first in the channel; e.g., bit 1’s for channel 9 of streams 0-7 are output synchronously with ST-BUS channel 8 bits 7-0. Use in a Simple Digital Switching System Figs. 7 and 8 show how MT89L80s can be used with MT8964s to form a simple digital switching system. Fig. 7 shows the interface between the MT89L80s and the filter/codecs. Fig. 8 shows the position of these components in an example architecture. The MT8964 filter/codec in Fig. 7 receives and transmi ts digitized voice signal s on the ST-BUS input D R, and ST- BUS output D X, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT89L80, which is used as a digital speech switch. The MT8964 is controlled by the ST-BUS input D C originating from the bottom MT89L80, which generates the appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability Bit Name Description 7-5* Stream Address Bits* The number expressed in binary notation on these 3 bits is the number of the ST-BUS stream for the source of the connection. Bit 7 is the most significant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on STi4. 4-0* Channel Address Bits* The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (The ST-BUS stream where the channel lies is is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19. *If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. 76 5432 10 Stream Address Bits Channel Address Bits

Zarlink Semiconductor Inc. * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings* Parameter Symbol Min. Max. Units 1 Supply Voltage -0.3 5.0 V 2 Voltage on any I/O pin (except supply pins) V O VSS-0.3 V DD+0.3 V

3 Current at Digital Outputs I O 20 mA

4 Storage Temperature T S -55 +125 °C

5 Package Power Dissipation P D 1W

Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics Sym. Min. Typ. Max. Units Test Conditions

1 Operating Temperature T OP -40 +85 °C

2 Positive Supply V DD 3.0 3.6 V 3 Input High Voltage V IH 0.7VDD VDD V 4 Input High Voltage on 5 V Tolerant Inputs V IH 5.5 V 5 Input Low Voltage V IL VSS 0.3VDD V Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions 1 I N P U T S Supply Current I DD 4 7 mA Outputs unloaded 2 Input High Voltage V IH 0.7VDD V 3 Input Low Voltage V IL 0.3VDD V

4 Input Leakage I IL 5 µAV I between VSS and VDD

5 Input Pin Capacitance C I 10 pF

O U T P U T S Output High Voltage V OH 0.8VDD VI OH = 10 mA 7 Output High Current I OH 10 mA Sourcing. V OH=2.4V 8 Output Low Voltage V OL 0.4 V I OL = 5 mA 9 Output Low Current I OL 5m A S i n k i n g . V OL = 0.4V

10 High Impedance Leakage I OZ 5 µAV O between VSS and VDD

11 Output Pin Capacitance C O 10 pF

Characteristics Sym Level Units Test Conditions 1 CMOS Threshold Voltage V TT 0.5VDD V 2 CMOS Rise/Fall Threshold Voltage high V HM 0.7VDD V 3 CMOS Rise/Fall Threshold Voltage low V LM 0.3VDD V

Zarlink Semiconductor Inc. † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i Figure 9 - Frame Alignment Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions I N P U T S Clock Period* t CLK 220 244 300 ns

2 Clock Width High t CH 85 122 150 ns

3 Clock Width Low t CL 85 122 150 ns

4 Clock Transition Time t CTT 10 ns

5 Frame Pulse Setup Time t FPS 10 190 ns

6 Frame Pulse Hold Time t FPH 10 190 ns

7F r a m e P u l s e W i d t h t FPW 244 ns C4i F0i BIT CELLS Channel 31 Bit o Channel 0 Bit 7

Zarlink Semiconductor Inc. Figure 10 - Clock Timing † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. Characteristics Sym. Min. Typ. ‡ Max. Units Test Conditions 1 O U T P U T S STo0/7 Delay - Active to High Z t SAZ 55 5 n s R L=1 KΩ*, CL=150 pF

2 STo0/7 Delay - High Z to Active t SZA 55 5 n s C L=150 pF

3 STo0/7 Delay - Active to Active t SAA 55 5 n s C L=150 pF

4 Output Driver Enable Delay t OED 50 ns R L=1 KΩ*, CL=150 pF

5 External Control Delay t XCD 55 ns C L=150 pF

N Serial Input Setup Time t SIS 20 ns

7 Serial Input Hold Time t SIH 20 ns

Zarlink Semiconductor Inc. Figure 13 - Serial Inputs † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Chip Select Setup Time t CSS 0n s

2 Read/Write Setup Time t RWS 5n s

3 Address Setup Time t ADS 5n s

4 Acknowledgment Delay

Control Register Read tAKD 52 120 ns C L=150 pF Control Register Write t AKD 25 65 ns C L=150 pF Connection Memory Read t AKD 62 120 ns C L=150 pF Connection Memory Write t AKD 30 53 ns C L=150 pF Data Memory Read t AKD 560 1220 ns C L=150 pF

5 Fast Write Data Setup Time t FWS 0n s

6 Slow Write Data Delay t SWD 122 ns

7 Read Data Setup Time t RDS 0n s C L= 150 pF

8 Data Hold Time Read

tDHT 10 90 ns R L=1 KΩ∗, CL=150 pF tDHT 51 0 n s

9 Read Data To High Impedance t RDZ 15 50 90 ns R L=1 KΩ∗, CL=150 pF

10 Chip Select Hold Time t CSH 0n s

11 Read/Write Hold Time t RWH 0n s

12 Address Hold Time t ADH 8n s

13 Acknowledgment Hold Time t AKH 50 80 ns R L=1 KΩ∗, CL=150 pF

Zarlink Semiconductor Inc. Figure 14 - Processor Bus DS CS R/W A5to DTAD7to t CSS tRWS tADS tAKD tRDS tSWD tFWS tCSH tRWH tADH tAKH tDHT tRDZ VHM VLM VHM VLM VHM VLM VHM VLM VHM VLM VHM VLM

c Zarlink Semiconductor 2003 All rights reserved. APPRD. ISSUE DATE ACN Package Code Previous package codes

www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I 2C Patent rights to use these components in and I 2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE For more information about all Zarlink products visit our Web Site at