MT8986AC

MT8986 MITEL | Alldatasheet

Document overview

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Technical content

Features

• 256 x 256 or 512 x 256 switching configurations
• 8-bit or 4-bit channel switching capability
• Guarantees frame integrity for wideband channels
• Automatic identification of ST-BUS/GCI interfaces
• Accepts serial streams with data rates up to

8.192 Mb/s

• Rate conversion from 2.048 Mb/s to 4.096 or

8.192 Mb/s and vice-versa

• Programmable frame offset on inputs
• Per-channel three-state control
• Per-channel message mode
• Control interface compatible to Intel/Motorola CPUs
• Low power consumption

Applications

• Medium size digital switch matrices
• Hyperchannel switching (e.g., ISDN H0)
• M V I P ™ interface functions
• Serial bus control and monitoring
• Centralized voice processing systems
• Voice/Data multiplexer
• 32 kbit/s channel switching

Description

The Multiple Rate Digital Switch (MRDX) is an upgraded version of MITEL's MT8980D Digital Switch (DX). It is pin compatible with the MT8980D and retains all of its functionality. This device is designed to provide simultaneous connections (non- blocking) for up to 256 64kb/s channels or blocking connections for up to 512 64kb/s channels. The serial inputs and outputs connected to MT8986 may have 32 to 128 64kb/s channels per frame with data rates ranging from 2048 up to 8192 kb/s. The MT8986 provides per-channel selection between variable and constant throughput delays allowing voice and grouped data channels to be switched without corrupting the data sequence integrity. In addition, the MT8986 can be used for switching of 32 kb/s channels in ADPCM applications. The MT8986 is ideal for medium size mixed voice and data switching/processing applications. Figure 1 - Functional Block Diagram STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 * STi10 * STi11 * STi12 * STi13 * STi14 * STi15 STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 * STo9 * CLK FR AS/ ALE IM DS RD CS R/W WR A0/ DTA AD7/ AD0 CSTo VDD V SS ODE Serial to Parallel Converter Multiple Buffer Data Memory Output MUX Parallel to Serial Converter Timing Unit Internal Registers Microprocessor Interface Connection Memory * 44 Pin only ISSUE 3 May 1995 MT8986 Multiple Rate Digital Switch CMOS ST-BUS  FAMILY

Ordering Information

MT8986AC 40 Pin Ceramic DIP MT8986AE 40 Pin Plastic DIP MT8986AP 44 Pin PLCC MT8986AL 44 Pin QFP -40°C to +85°C

Figure 2 - Pin Connections Pin Description Pin # Name Description40 DIP PLCC QFP 12 4 0 D T A Data Acknowledgement (Open Drain Output). This active low output indicates that a data bus transfer is complete. A 10kΩ pull-up resistor is required at this output. 2-7 2-5 7-9 41-43 1-3 STi0-5 ST-BUS Inputs 0 to 5 (Inputs). Serial data input streams. These streams may have data rates of 2.048, 4.096 or 8.192 Mbit/s with 32, 64 or 128 channels, respectively. DTA STi0 STi1 STi2 AS/ALE ODE STo0 STo1 STo2 STi4/STo8 STo3 STo4 STo5 STo6/A6 STo7/A7 VSS AD0 AD1 AD2 AD3 AD4 IM STi11/A3 STi12/A4 STi3/A5 DS/RD STi15/STo9 AD5 AD6 AD7 CS

44 PIN QFP

40 PIN DIP

R/W \\WR 11 23 165432 4 4 4 3 4 2 4 1 40 2318 19 20 21 22 24 25 26 27 28 17 29 DTA STi0 STi1 STi2 AS/ALE ODE STo0 STo1 STo2 STi4/STo8 STo3 STo4 STo5 STo6/A6 STo7/A7 VSS AD0 AD1 AD2 AD3 AD4 IM STi11/A3 STi12/A4 STi3/A5 DS/RD STi15/STo9 AD5 AD6 AD7 CS R/W /WR CSTo STi3 STi4 STi5 STi6/A6 STi7/A7 VDD FR CLK STi8/A0 STi9/A1 STi10/A2

44 PIN PLCC

8 10 4 STi6/A6 ST-BUS Input 6/Addr.6 input (Input). The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is used along with a higher input rate of 8.192 or 4.096 Mb/s, this pin provides A6 address input function. For 2.048 and 4.096 Mb/s (8x4) applications or when multiplexed CPU bus (44 pin only) is selected, this pin assumes STi6 function. See Control Register bits description and Tables 1, 2, 6 & 7 for more details. Note that for applications where both A6 and STi6 inputs are required simultaneously (e.g., 8 x 4 switching configuration at 4.096 Mb/s or rate conversion between 2.048Mb/s to 4.196 or 8.192 Mb/s) the A6 input should be connected to pin STo6/A6. 9 11 5 STi7/A7 ST-BUS Input 7/Addr.7 input (Input): The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is used along with a higher input rate of 8.192 Mb/s, this pin provides A7 address input function. For 2.048 and 4.096 Mb/s (8x4) applications or when multiplexed CPU bus (44 pin only) is selected, this pin assumes STi7 function. See Control Register bits description and Tables 1, 2, 6 & 7 for more details. Note that for applications where both A7 and STi7 inputs are required simultaneously (e.g., 2.048 to 8.192 Mb/s rate conversion) the A7 input should be connected to pin STo7/A7. 10 12 6 V DD +5 Volt Power Supply. 11 13 7 FR Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI interface specifications. 12 14 8 CLK Clock (Input). Serial clock for shifting data in/out on the serial streams. Depending on the serial interface speed selected by IMS (Interface Mode Select) register, the clock at this pin can be 4.096 or 8.192 MHz. 13-15 15-17 9-11 A0-2/ STi8-10 Address 0-2 / Input Streams 8-10 (Input). When non-multiplexed CPU bus is selected, these lines provide the A0-A2 address lines to MT8986 internal registers. When 16x8 switching configuration is selected (in 44 pin only), then these pins are ST-BUS serial inputs 8 to 10 receiving data at 2.048 Mb/s. 16-18 19-21 13-15 A3-5/ STi11-13 Address 3-5 / Input Streams 11-13 (Input). When non-multiplexed CPU bus is selected, these lines provide the A3-A5 address lines to MT8986 internal registers. When 16x8 switching configuration is selected (in 44 pin only), then these pins are ST-BUS serial inputs 11 to 13 receiving data at 2.048 Mb/s. 19 22 16 DS/RD Data Strobe/Read (Input). When non-multiplexed CPU bus or Motorola multiplexed bus (44 pin only) are selected, this input is DS. This active high input works in conjunction with CS to enable read and write operation. For Intel/National multiplexed bus (44 pin only), this input is RD. This active low input configures the data bus lines (AD0-AD7) as outputs. 20 23 17 R/W \\WR Read/Write \\ Write (Input). In case of non-multiplexed and Motorola multiplexed buses (44 pin only), this input is R/W. This input controls the direction of the data bus lines (AD0-AD7) during a microprocessor access. With Intel/National multiplexed timing (44 pin only), this input is WR. This active low signal configures the data bus lines (AD0-AD7) as inputs. 21 24 18 CS Chip Select (Input). Active low input enabling a microprocessor read or write of the control register or internal memories. 22-29 25-27 29-33 19-21 23-27 AD7- AD0 Data Bus (Bidirectional): These pins provide microprocessor access to the internal control registers, connection memories high and low and data memories. In multiplexed bus mode (44 pin) these pins also provide the input address to the internal Address Latch circuit. 30 34 28 V SS Ground. Pin Description (continued) Pin # Name Description40 DIP PLCC QFP

31 35 29 STo7/A7 ST-BUS Output 7/Address 7 input (Three-state output/input). The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is used along with data rates employing 8.192 Mb/s rates, this pin provides A7 address input function. For 2.048 Mb/s applications or when multiplexed CPU bus (44 pin only) is selected, this pin assumes STo7 function. See Tables 1, 2, 6 & 7 for more details. Note that for applications where A7 input and STo7 output are required simultaneously (e.g., 8.192 to 2.048 Mb/s rate conversion), the A7 input should be connected to pin STi7/A7. 32 36 30 STo6/A6 ST-BUS Output 6/Address 6 input (Three-state output/input). The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is used along with a higher data rate employing 8.192 or 4.096 Mb/s, this pin provides the A6 address input function. For 2.048 Mb/s applications or when multiplexed CPU bus (44 pin only) is selected, this pin assumes STo6 function. See Tables 1, 2, 6 & 7 for more details. Note that for applications where both A6 input and STo6 output are required applications), the A6 input should be connected to pin STi6/A6. 33-38 37-39 41-43 31-33 35-37 STo5-0 ST-BUS Outputs 5 to 0 (Three-state Outputs). Serial data output streams. These serial streams may be composed of 32, 64 and 128 channels at data rates of 2.048, 4.096 or 8.192 Mbit/s, respectively. 39 44 38 ODE Output Drive Enable (Input). This is the output enable input for the STo0 to STo9 serial outputs. If this input is low STo0-9 are high impedance. If this input is high each channel may still be put into high impedance by using per-channel control bits in Connect Memory High. 40 1 39 CSTo Control ST-BUS Output (Output). This is a 2.048 Mb/s output containing 256 bits per frame. The level of each bit is determined by the CSTo bit in the Connect Memory high locations. - 6 AS/ALE Address Strobe or Latch Enable (Input). This input is only used if multiplexed bus is selected via the IM input pin (44 pin only). The falling edge of this signal is used to sample the address into the address latch circuit. In case of non-multiplexed bus, this input is not required and should be left open. - 18 IM CPU Interface Mode (Input). If HIGH, this input configures MT8986 in multiplexed microprocessor bus mode. If this input pin is not connected or grounded, the MT8986 assumes non-multiplexed CPU interface. - 28 STi15/ STo9 ST-BUS Input 15 / ST-BUS Output 9 (Input/three-state output). This pin is only used if multiplexed CPU bus is selected. If 16-input x 8-output switching configuration is enabled in the SCB bits (IMS register), this pin is an input receiving serial ST-BUS stream 15 at a data rate of 2.048 Mbit/s. If Stream Pair Selection capability is enabled (see switching configuration section), this pin is the ST-BUS stream 9 output. When non-multiplexed bus structure is used, this pin should be left open. - 40 STi14/ STo8 ST-BUS Input 14 / ST-BUS Output 8 (Input/three-state output). This pin is only used if multiplexed CPU bus is selected. If 16-input x 8-output switching configuration is enabled in the SCB bits (IMS register), this pin is an input that receives serial ST-BUS stream 14 at a data rate of 2.048 Mbit/s. If Stream Pair Selection capability is enabled (see switching configuration section), this pin is the ST-BUS stream 8 output. When non-multiplexed bus structure is used, this pin should be left open. Pin Description (continued) Pin # Name Description40 DIP PLCC QFP

With the integration of voice, video and data services in the same network, there has been an increasing demand for systems which ensure that data at N x 64 kbit/s rates maintain sequence integrity while being transported through time-slot interchange circuits. This requirement demands time-slot interchange devices which perform switching with constant throughput delay for wideband data applications while guaranteeing minimum delay for voice channels. The MT8986 device meets the above requirement and allows existing systems based on the MT8980D to be easily upgraded to maintain the data integrity when wideband data is transported. The device is designed to switch 32, 64 or N x 64 kbit/s data. The MT8986 can provide frame integrity for data applications and minimum throughput switching delay for voice applications on a per channel basis. The serial streams of the MT8986 device can operate at 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125 µs wide frames which contain 32, 64 and 128 channels, respectively. In addition, a built-in rate conversion circuit allows the user to interconnect various backplane speeds like 2.048 or 4.096 or 8.192 Mb/s while maintaining the control of throughput delay function on a per-channel basis. By using Mitel Message mode capability, the microprocessor can access input and output time- slots on a per channel basis to control external circuits or other ST-BUS devices. The MT8986 automatically identifies the polarity of the frame synchronization input signal and configures its serial port to be compatible to both ST-BUS and GCI formats. In the 44 pin packages, two different microprocessor bus interfaces can be selected through an input mode pin (IM): Non-Multiplexed or Multiplexed. These interfaces provide compatibility with Intel/ National multiplexed and Motorola Multiplexed/Non- Multiplexed buses. In 44 pin, the MT8986 provides a 16 x 8 switching configuration to form a 512 x 256 channel blocking matrix. Also, a flexible Stream Pair Selection operation allows the software selection of which pair of input and output streams can be connected to an internal 128 x 128 matrix. See Switching Configurations section for details. Functional Description A functional Block Diagram of the MT8986 device is shown in Figure 1. Depending on the application, the MT8986 device receives TDM serial data at different rates and from different number of serial streams. Data and Connect Memories For all data rates, the received serial data is converted to parallel format by the serial to parallel converters and stored sequentially in a Data Memory. Depending on the selected operation programmed in the IMS (Interface Mode Select) register, the Data Memory may have up to 512 bytes in use. The sequential addressing of the Data Memory is performed by an internal counter which is reset by the input 8 kHz frame pulse (FR) marking the frame boundaries of the incoming serial data streams. Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input as in connection mode or it can be from the Connect Memory Low as in message mode. Data destined for a particular channel on the serial output stream is read from the Data Memory or Connect Memory Low during the previous channel time-slot. This allows enough time for memory access and parallel to serial conversion. Connection and Message Modes In connection mode, the addresses of the input source data for all output channels are stored in the Connect memories High (CMH) and Low (CML). The CML and CMH are mapped so that each location corresponds to an output channel on the output streams. The number of source address bits in CMH and CML to be utilized varies according to the switching configuration selected in the IMS register. For details on the use of the source address data (CAB and SAB bits), see CMH and CML bit descrip- tion (Figures 5 & 6). Once the source address bits are programmed by the CPU, the contents of the Data Memory at the selected address are transferred to the parallel-to-serial converters. By having the output channel specify the source channel through the connect memory, the user can route the same input channel to several output channels, allowing broadcast facility within the switch. In message mode the CPU writes data to the Connect Memory Low locations corresponding to the output link and channel number. The contents of the Connect Memory Low are transferred directly to the parallel-to-serial converter one channel before it is to

be output. The Connect Memory Low data is transmitted on to the output every frame until it is changed by the CPU with a new data. The features of each output channel in the MT8986 are controlled by the Connect Memory High bits. These bits determine individual output channels to be in message or connection mode, select throughput delay types and enable/disable output drivers. The Connect Memory High also provides additional stream and channel address bits for some configurations. In addition, the Connect Memory High provides one bit to allow the user to control the CST o output in 2.048 Mb/s applications. If an output channel is set to high-impedance, the TDM serial stream output will be placed in high impedance during that channel time. In addition to the per-channel control, all channels on the TDM outputs can be placed in high impedance by pulling the ODE input pin LOW. This overrides the individual per-channel programming by the Connect Memory High bits. The Connect Memory data is received via the Microprocessor Interface through the data I/O lines. The addressing of the MT8986 internal registers, Data and Connect memories is performed through address input pins and some bits of the device's Control register. The higher order address bits come from the Control register, which may be written or read through the microprocessor interface. The lower order address bits come directly from address input pins. For details on the device addressing, see Software Control and Control register bits description (Figure 3 & Tables 5, 6 and 7). Serial Data Interface The master clock (CLK) can be either at 4.096 or

8.192 MHz allowing serial data link operations at

2.048, 4.096 and 8.192 Mb/s. These data rates can be independently selected on input and output streams allowing the MT8986 device to be used in various speed backplanes and in rate conversion applications. The selected data rates apply to the inputs or the output streams. Different bit rates among input streams or among output streams are not allowed. Due to the I/O data rate selection flexibility, two major operations can be selected: Identical or Different I/O data rates. The DMO bit (Device Main Operation) in the IMS register is used for selecting between Identical I/O rates or Different I/O rates. On system power-up, the CPU should set up the DMO, the IDR (Input Data Rate) and ODR (Output Data Rate) bits located in the IMS register. When Identical I/O data rates are selected by the DMO bit, the switching configuration and the number of the device's input and output streams can be selected through the SCB bits (Switching Configuration Bits) in the IMS register. See Switching Configurations section for details. Depending on the application, the interface clock can be selected to be twice the data rate or equal to the data rate. This selection is performed through bit CLKM in the IMS register. For applications where both serial inputs and outputs are at 2.048 Mb/s (ST- BUS or GCI format), the CLKM bit should be set LOW enabling the interface clock to be twice the bit rate. In applications where both inputs and outputs are at 4.096 or 8.192 Mb/s, CLKM should be set HIGH enabling the interface clock to be equal to the bit rate. In applications where inputs and outputs are at different rates, the CLKM bit has no effect. In applications with serial links at 2.048 Mb/s (see Figures 16 to 19), the input 8 kHz frame pulse can be in either ST-BUS or GCI format. The MT8986 device automatically detects the presence of an input frame pulse and identifies what type of backplane is present on the serial interface. Upon determining the interface connected to the serial port, the internal timing unit establishes the appropriate transmit and sampling edges. In ST-BUS format, every second falling edge of the 4.096 MHz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. In GCI format, every second rising edge of the 4.096 MHz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries. For identical I/O rates at 4.096 and 8.192 Mb/s (see Figure 20), the clock and interface data rates are equal. The bit transmit and sampling edges vary according to the applied frame pulse polarity. For example, if the FR pulse polarity is positive, the bit transmit operation is done on every rising edge of CLK and the bit sampling on every falling edge. If the FR pulse polarity is negative, these edges are inverted. For different I/O rates, the MT8986 side operating at 2.048 Mb/s data rate will comply with ST-BUS or GCI interfaces for transmit and sampling procedures. The MT8986 side operating at 4.096 or

8.192 Mb/s behaves according to the frame pulse

polarity applied. See Figures 22 to 25. Switching Configurations Switching configurations are determined basically by the interface rates selected at the serial inputs and outputs. To specify the switching configuration required, the IMS register has to be initialized on system power-up. In case of Identical I/O rates (DMO bit LOW) at both inputs and outputs, the switching configuration is selected by the two SCB

bits as shown in table 8 (see IMS register). In case of different I/O rates (DMO bit HIGH), the switching configuration is always non-blocking with different number of I/O streams which is defined by the IDR and ODR bits (see IMS register). Identical Input/Output Data Rates When identical input/output data rate is selected by the DMO bit, the I/O rate is determined by the IDR0- 1 bits, and the ODR0-1 bits are ignored. For each data rate specified by the IDR bits, different switching configurations can be selected in the SCB1-0 bits. Serial Links with Data Rates at 2.048 Mb/s When 2.048 Mb/s data rate is selected at the IDR bits, four different I/O configurations can be selected by the SCB1-0 bits (see Table 8); 8 x 8, 16 x 8, 4 x 4 with stream pair selection and nibble switching. If 8 x 8 switching configuration is selected, a 256 x 256 channel non-blocking switching matrix is available. In this configuration, the MT8986 device is configured with 8 input and 8 output data streams with 32 64 Kbit/s channels each. The interface clock for this operation is 4.096 MHz with both ST-BUS and GCI compatibilities and the per-channel selection between variable and constant throughput delay functions is provided. This configuration is available in both the 40 and 44 pin packages. In 16 x 8 switching configuration, a 512 x 256 channel blocking switch matrix is available. This configuration is only provided in the 44 pin package and when the CPU interface is configured in multiplexed bus mode. The device clock in this application is 4.096 MHz, ST-BUS or GCI compatible. This configuration only provides variable throughput delay. If the stream pair selection switching configuration is selected, only four input and four outputs (4 pairs of serial streams) can be selected by the CPU to be internally connected to the switch matrix, totalling a 128 x 128 channel non-blocking switch. From the 10 serial link pairs available, two pairs are permanently connected to the internal matrix (STi0/ST o0 and STi1/ST o1). An internal stream pair selection capability allows two additional pairs of serial links to be selected from the remaining 8 pairs (from STi/ STo2 to STi9/STo9) and be connected to the internal matrix along with the permanently connected STi0/ STo0 and STi1/STo1 streams. The two additional pair of streams called stream pair A and stream pair B, should be selected in the Stream Pair Selection register (SPS). The device clock for this operation is

4.096 MHz compatible to ST-BUS and GCI

interfaces. In addition, the per-channel selection between variable or constant throughput delay is available. This configuration is only provided in the 44 pin packages. In case of nibble switching, 4-bit wide 32 kb/s data channels can be switched within the device. In this case, every serial stream is run at 2.048 Mb/s and transports 64 nibbles per frame. When Nibble Switching is selected at SCB bits, the MT8986 automatically assumes a 8 input x 4 output stream configuration, providing a blocking switch matrix of 512 x 256 nibbles. If a non-blocking switch matrix is required for nibble switching, the switch capacity is reduced to 256 x 256 channel with a 4 input x 4 output configuration; the non-blocking matrix can be arranged by the user by selecting any four of the 8 input streams. In nibble switching the interface clock is 4.096 MHz. Serial Links with Data Rates at 4.096 Mb/s Two I/O configurations can be enabled by the SCB bits when input and output data rates are 4.096 Mb/s on each serial stream: 8 x 4 and 4 x 4. When 8 x 4 switching configuration is selected, a 512 x 256 channel blocking switch is available with serial streams carrying 64, 64 Kb/s channels each. For this operation, a 4.096 MHz interface clock equal to the bit rate should be provided to MT8986. Only variable throughput delay mode is provided. In case of 4 x 4 switching configuration, a 256 x 256 channel non-blocking switch is available with serial streams carrying 64, 64 Kb/s channels each. In this configuration, the interface clock is 4.096 MHz and the per-channel selection between variable and constant throughput delay operation is provided. Figure 20 shows the timing for 4.096 Mb/s operation. Serial Links with Data Rates at 8.192 Mb/s Only 2 input x 2 output stream configuration is available for 8.192 Mb/s, allowing a 256 x 256 channel non-blocking switch matrix to be implemented. To enable this operation, the IDR bits should be programmed to select 8.192 Mb/s rates and the SCB bits have no effect. At 8.192 Mb/s, every input and output stream provides 128 time- slots per frame. The interface clock for this operation should be 8.192 MHz. Figure 20 shows the timing for 8.192 Mb/s operation. T able 1 summarizes the MT8986 switching configurations for identical I/O data rates.

Table 1. Switching Configurations for Identical Input and Output Data Rates

2 Mb/s

constant throughput delay selection is provided. serial interface clock (CLK input pin) is different. serial inputs while building large switch matrices. received at the serial inputs. serial inputs and not with the FR frame pulse input. Table 2. Switching Configurations for Different I/O Data Rates

Register (FIO). If this function is not required in the user's applications, the FIO register should be set up during system initialization to a state where offset functions are disabled. Delay Through the MT8986 The switching of information from the input serial streams to the output serial streams results in a delay. Depending on the type of information to be switched, the MT8986 device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, variable throughput delay can be selected ensuring minimum delay between input and output data. In wideband data applications, constant throughput delay can be selected maintaining the frame integrity of the information through the switch. The delay through the MT8986 device varies according to the type of throughput delay selected in the V /C bit of the connect memory high. Variable Throughput Delay Mode (V/C bit = 0) Identical I/O Data Rates The delay in this mode is dependent on the combination of source and destination channels and it is independent of the input and output streams. The minimum delay achievable in the MT8986 depends on the data rate selected for the serial streams. For instance, for 2.048 Mb/s the minimum delay achieved corresponds to three time-slots. For

4.096 Mb/s it corresponds to five time-slots while for

8.192 Mb/s it is nine time-slots. Switching configurations with input and output channels that provides more than its corresponding minimum throughput delay, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame period. Table 3a shows the MT8986 throughput delay for each data rate operation. Different I/O Data Rates Except for 2 Mb/s to 4 Mb/s and 2 Mb/s to 8 Mb/s rate conversion operations, the throughput delay in the MT8986 may vary according to the output stream used for switching. T able 3b explains the worst case conditions for the throughput delay when different I/O data rate switching configurations are used. Constant Throughput Delay mode (V /C bit = 1) In this mode frame sequence integrity is maintained in both Identical and Different I/O Data Rate Table 3a. Variable Throughput Delay Values for Identical I/O Rate Applications n= input channel, t.s. = time-slot Table 3b. Min/Max Throughput Delay Values for Different I/O Rate Applications Notes: dmin and dmax are measured in time-slots and at the point in time when the output channel is completely shifted out. t.s. = time-slot fr. = 125 µs frame 2 Mb/s t.s. = 3.9 µs 4 Mb/s t.s. = 1.95 µs 8 Mb/s t.s. = 0.975 µs Input Rate Output Channel (# m) m < n m=n, n+1, n+2 m= n+3, n+4 m=n+5, .. n+8 m > n+8 I/O Data Rate Configuration Output Stream Used 0, 1 2, 3 4, 5 6, 7 2 Mb/s to 4 Mb/s dmin=5x 4Mb/s t.s. dmax=1 fr.+(4x 4Mb/s t.s.) 2 Mb/s to 8 Mb/s dmin=9x 8Mb/s t.s. dmax=1 fr.+(8x 8Mb/s t.s.) 4 Mb/s to 2 Mb/s dmin=3x 2Mb/s t.s. dmax=1 fr.+(2x 2Mb/s t.s.) dmin=(2x 2Mb/s t.s.)+(1x 4Mb/s t.s.) 8 Mb/s to 2 Mb/s dmin=3x 2Mb/s t.s. dmax=1 fr.+(2x 2Mb/s t.s.) dmin=(2x 2Mb/s t.s.)+ (3x 8Mb/s t.s.) dmax=1 fr.+(1x 2Mb/s t.s.)+(3x 8Mb/s t.s.) dmin=(2x 2Mb/s t.s.)+ (2x 8Mb/s t.s.) dmax=1 fr.+(1x 2Mb/s t.s.)+(2x 8Mb/s t.s.) dmin=(2x 2Mb/s t.s.)+ (1x 8Mb/s t.s.) dmax=1 fr.+(1x 2Mb/s t.s.)+(1x 8Mb/s t.s.)

Table 4. Constant Throughput Delay values

2.048 Mb/s d=[32 + (32 - IN) + (OUT - 1)]; (expressed in # time-slots)

4.096 Mb/s d=[64 + (64 - IN) + (OUT - 1)]; (expressed in # time-slots)

8.192 Mb/s d=[128 + (128 - IN) + (OUT - 1)]; (expressed in # time-slots)

CPU Interface Mode (IM) input pin. ALE, then Intel bus timing is selected. except for the data memory which can be read only. addressed by the A4 to A0 bits according to Table 5.

together control all the major functions of the device. Interface and Switching Configurations sections. corresponding to input or output ST-BUS streams. once every frame unless the ODE input pin is LOW. the corresponding channel on the ST-BUS streams. Table 5. Address Memory Map

00100000 Channel 0*

01100000 Channel 32**

CMH is transmitted during ST-BUS channel 31 bit 6. For more detailed description of the CSTo operation, see section 6 of Application Note MSAN- 123. The Bit V /C (Variable/Constant Delay) of each Connect Memory High location allows the per- channel selection between Variable and Constant throughput delay modes. Initialization of the MT8986 On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially hazardous condition when multiple MT8986 ST-BUS outputs are tied together to form matrices, as these outputs may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition. During the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. Care should be taken that no two ST-BUS outputs drive the bus simultaneously. When this process is complete, the microprocessor controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the CMH b0s.

Control Register - Read/Write Figure 3 - Control Register Description BIT NAME DESCRIPTION 7 SM Split Memory. When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory Low, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available. 6 ME Message Enable. When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when in High Impedance as set by the ODE input. When 0, the Connection Memory bits for each channel determine what is output. 5 STA3 Stream Address Bit 3. This bit is used in the 44 pin packages when 16 x 8 switching configuration is selected. It is used with STA2-0 to select one of the 16 input data streams whenever the Data Memory is to be read. The programming of this bit has no effect in other switching configurations. 4-3 MS1-0 Memory Select Bits. The memory select bits operate as follows: 0-0 - Not to be used 0-1 - Data Memory (read only from the CPU) 1-0 - Connection Memory Low 1-1 - Connection Memory High 2-0 STA2-0 The number expressed in binary notation on these bits refers to the input or output ST- BUS stream which corresponds to the subsection of memory made accessible for subsequent operations. The use of these bits depends on the switching configuration as well as the device’s main operation defined by the DMO bit of the Interface Mode Selection register. Tables 6 and 7 show the utilization of these bits according to the device’s main operation. SM ME STA3 MS1 MS0 STA2 STA1 STA0 76543210

Table 6. Use of STA Bits for Identical I/O Data Rate Operation

• - only in the 44 pin packages.

** - for Data Memory Read operations A0 is not required since two nibbles are provided per read access. Table 7. Use of STA Bits for Different I/O Data Rate Operation implies that different address inputs are used to select individual positions within the subsections for each type of memory.

2 Mb/s 8x8 STA2, STA1, STA0 STA2, STA1, STA0 A4, A3, A2, A1, A0

2 Mb/s * 4x4 * STA1, STA0 STA1, STA0 A4, A3, A2, A1, A0

2 Mb/s * 16x8 * STA3, STA2, STA1,

4 Mb/s 4x4 STA1, STA0 STA1, STA0 A6, A4, A3, A2, A1, A0

4 Mb/s 8x4 STA2, STA1, STA0 STA1, STA0 A6, A4, A3, A2, A1, A0

8 Mb/s 2x2 STA0 STA0 A7, A6, A4, A3, A2, A1, A0

2 Mb/s to

4 Mb/s

8 Mb/s

4 Mb/s to

8 Mb/s to

Interface Mode Selection Register - Read/Write Figure 4 - IMS Register Description BIT NAME DESCRIPTION 7 DMO Device Main Operation. This bit is used by the CPU to define one of the two main operations of the MT8986 device. If this bit is LOW, the MT8986 is configured for identical I/O data rates. For this operation, the user should also specify the switching configuration through the SCB bits. If this bit is HIGH, the MT8986 device is configured in Different I/O data rate. This allows combinations of input and output data rates as shown in Table 2. The SCB bits have no effect in this application and the device is in Non-Blocking switch configuration with a 256 x 256 channel capacity. 6-5 IDR1-0 Input Data Rate Selection. These two bits select three different data rates for the inputs of the MT8986. In the case of identical I/O rates (DMO bit = 0), these bits also determine the serial output data rate. IDR1 IDR0 Input Rate 0 0 2.048 Mb/s 0 1 4.096 Mb/s 1 0 8.192 Mb/s 1 1 reserved 4-3 ODR1-0 Output Data Rate Selection. These bits are only used when Different I/O rates are selected (DMO bit=1). These two bits select three different data rates for the serial outputs of the MT8986. These bits are ignored if DMO bit = 0. ODR1 ODR0 Output Rate 0 0 2.048 Mb/s 0 1 4.096 Mb/s 1 0 8.192 Mb/s 1 1 reserved 2-1 SCB1-0 Switching Configuration Bits 1-0. These bits should only be used when DMO is set LOW. The use of these bits to select the switching configuration of the MT8986 device is described in Table 8. 0 CLKM Clock Mode. This bit is only used when the MT8986 device is set to operate in identical I/O data rates. When set High, this bit selects the interface clock to be equal to the bit rate. If Low, this bit selects the interface clock to be twice the bit rate. For Different I/O data rate applications, this bit is ignored. DMO IDR1 IDR0 ODR1 ODR0 SCB1 SCB0 CLKM 76543210

Table 8. Switching Configurations for Identical I/O Rates

Connection Memory High - Read/Write Figure 5 - Connection Memory High (CMH) Bits x=Don’t care BIT NAME DESCRIPTION 6V /C Variable/Constant Throughput Delay Mode. This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes in a per-channel basis. Tables 1 and 2 describe the switching configurations that have this function. In the modes where this function is not available, this bit has not effect. 5 SAB3 Source Stream Address bit 3. This bit is used along with bits SAB0-2 in CML to select up to 16 different source streams for the connection. Depending on the state of DMO bit and the switching configuration enabled, not all SAB3-0 bits have to be used. See Tables 9 and 10 for details on the utilization of the SAB bits. 4-3 CAB6-5 Sou rce Channel Address bits 5 and 6. These two bits are used together with bits CAB0-4 in Connect Memory Low to select up 128 different source channels for the connection. Depending on the data rate used in the input/output streams, 5, 6 or all 7 CAB bits can be used respectively, to select 32, 64 or 128 different channels. See Tables 9 and 10 for details on the utilization of the CAB bits. 2 MC Message Channel. When 1, the contents of the corresponding location in Connection Memory Low are output on the corresponding channel and stream. When 0, the contents of the programmed location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location’s channel and stream. 1 CSTo CSTo Bit. This bit is only available in 2.048 Mb/s applications. It drives a bit time on the CSTo output pin. 0 OE Output Enable. This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to be made high-impedance, allowing switch matrices to be constructed. A HIGH enables the driver and a LOW disables it. XV /C SAB3 CAB6 CAB5 MC CSTo OE 76543210 (CM high bits)

Table 9. CAB and SAB Bits Programming for Identical I/O Rate Applications Table 10. CAB and SAB Bits Programming for Different I/O Rate Applications used. See Tables 9 and 10 for details. can be used to select respectively 32, 64 or 128 different channels. See Tables 9 and 10 for details. of the connection which is output on the channel and stream associated with this location.

Switch Matrix Architectures The MT8986 is an ideal device for designs of medium size switch matrix. For applications where voice and grouped data channels are transported within the same frame, the voice samples have to be time interchanged with a minimum delay while maintaining the integrity of grouped data. To guarantee the integrity of grouped data during switching and to provide a minimum delay for voice connections, the MT8986 provides the per-channel selection between variable and constant throughput delay. This can be selected by the V /C bit of the Connection Memory High locations. Different connectivities at different data rates can be built to accommodate Non-Blocking matrices of up to 512 channels while maintaining the per channel selection of the device's throughput delay. Some examples of such Non-Blocking configurations are given in Figures 9 to 11. For applications where voice and data samples are encoded into individual 64 kb/s time-slots on an 8kHz frame basis, the switch matrix can operate with time interchange procedures where only variable Figure 9 - 512-Channel Switch with Serial Streams at 2.048 Mb/s Figure 10 - 256-Channel Switch with Rate Conversion between 2.048 and 4.096 Mb/s Figure 11 - 256-Channel Switch with Rate Conversion between 2.048 and 8.192 Mb/s MT8986 MT8986 MT8986 MT8986 IN OUT

8 Streams

@ 2.048 Mb/s @ 2.048 Mb/s @ 2.048 Mb/s @ 2.048 Mb/s MT8986 IN 8 Streams @ 2.048 Mb/s MT8986

4 Streams

@ 4.096 Mb/s STi0 STi7 STo0 STo7 STo0 STo1 STo2 STo3 STi0 STi1 STi2 STi3 8 Streams @ 2.048 Mb/s OUT MT8986 IN 8 Streams @ 2.048 Mb/s MT8986

2 Streams

@ 8.192 Mb/s STi0 STi7 STo0 STo7 STo0 STo1 STi0 STi1 @ 2.048 Mb/s OUT

throughput delay is guaranteed. For such applications, the MT8986 device allows cost effective implementations of Non-Blocking matrices ranging up to 1024 channels. Figures 12 and 13 show the block diagram of implementations with Non-Blocking capacities of 512 and 1024-channel, respectively. Interfacing MT8986 with 8051 The Intel 8051 is a very cost effective solution for many applications that do not require a large CPU interaction and processing overhead. However, in applications where 8051 is connected to peripherals operating on a synchronous 8 kHz time-base like the MT8986, some connectivity issues have to be addressed. The MT8986 may hold the CPU read/ write cycle due to internal contention between the MT8986 microport and the internal serial to parallel and parallel to serial converters. Since the 8051 family of CPUs do not provide Data Ready type of inputs, some external logic and software intervention have to be provided between the MT8986 and the 8051 microcontrollers to allow read/ write operation. The external logic described in Figure 14 is a block diagram of a logical connection between MT8986 and 8051. Its main function is to store the 8051 data during a write and the MT8986 data during a read. For a write, MT8986 address is latched by the internal address latch on the falling edge of the ALE input. Whenever a read or write operation is done to the MT8986 device, the address decoded signal (MTA ) is used to latch or "freeze" the state of RD, WR , and the ALE signals, until the data acknow- ledge output signal is provided by the MT8986 device, releasing the latches for a new read/write cycle. Latch U5 is used to hold the 8051 data for a write until the CPU is ready to accept it (when DTA Figure 12 - 512-Channel Non-Blocking Switch Matrix with Serial Streams at 2.048 or 4.096 Mb/s Figure 13 - 1024-Channel Non-Blocking Switch Matrix with Serial Streams at 2.048 Mb/s IN OUT

16 Streams

@2.048 Mb/s @2.048 Mb/s @2.048 Mb/s 8MT8986 MT8986 512 x 256 512 x 256 IN OUT @4.096 Mb/s @4.096 Mb/s @4.096 Mb/s 4MT8986 MT8986 512 x 256 512 x 256 IN IN @2.048 Mb/s @2.048 Mb/s MT8986 512 x 256 MT8986 512 x 256 MT8986 512 x 256 MT8986 512 x 256 MT8986 512 x 256 MT8986 512 x 256 MT8986 512 x 256 MT8986 512 x 256 @2.048 Mb/s @2.048 Mb/s @2.048 Mb/s @2.048 Mb/s OUT OUT

Figure 14 - Interfacing the MT8986 to the 8051 Microcontroller RES RST 8051 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE RD WR D CK Q PR D CK Q PR D CK Q PR CS MTA MT8986 Address Decode LATCH LATCH LE OE OE LE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE RD WR CS DTA RD MTA DTA MTA AD0-AD7 MT8986 DTA RES R C LRD LWR MT8986 Access goes low). Latch U4 stores the MT8986 output data during a read cycle whenever DTA goes low. When writing to the MT8986, one write operation is sufficient. However, when reading MT8986, two read operations with the same address are required, with the second being valid. Enough time need to be provided between two CPU accesses to allow the first access to complete; i.e., to allow for an internal MT8986 reaction over the first RD /WR access. For a read operation, a minimum of 1220 ns have to be guaranteed between two successive accesses. For write, at least 800 ns has to be respected.

• Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 15 - Output Test Load Absolute Maximum Ratings* Parameter Symbol Min Max Units 1V DD - VSS -0.3 7 V 2 Voltage on Digital Inputs V I VSS -0.3 V DD +0.3 V 3 Voltage on Digital Outputs V O VSS -0.3 V DD +0.3 V

4 Current at Digital Outputs I O 40 mA

5 Storage Temperature T S -65 +150 °C

6 Package Power Dissipation P D 2W

Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Operating Temperature T OP -40 25 +85 °C

2 Positive Supply V DD 4.75 5.0 5.25 V

3 Input Voltage V I 0V DD V

Characteristics Sym Min Typ ‡ Max Units Test Conditions I N P U T S Supply Current I DD 10 15 mA Outputs unloaded 2 Input High Voltage V IH 2.0 V 3 Input Low Voltage V IL 0.8 V

4 Input Leakage (input pins)

Input Leakage (I/O pins) IIL 100 µAV I between VSS and VDD

5 Input Pin Capacitance C I 8p F

O U T P U T S Output High Voltage V OH 2.4 V I OH = 10 mA 7 Output High Current I OH 10 15 mA Sourcing. V OH =2.4V 8 Output Low Voltage V OL 0.4 V I OL = 5 mA 9 Output Low Current I OL 5 10 mA Sinking. V OL = 0.4V

10 High Impedance Leakage I OZ 5 µAV O between VSS and VDD

11 Output Pin Capacitance C O 8p F

when testing output levels or high impedance states. S2 is switched to VDD or V SS when testing output levels or high impedance states.

† Timing is over recommended temperature & power supply voltages (VDD =5V±5%, VSS =0V, TA=–40 to 85°C). ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 16 - ST-BUS Timing (CLKM bit=0) Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Frame Pulse width t FRW 244 ns

2 Frame Pulse setup time t FRS 10 190 ns

3 Frame Pulse hold time t FRH 20 190 ns

4 STo delay Active to Active t DAA 45 100 ns C L=150 pF

5 STi setup time t ST IS 20 ns

6 STi hold time t ST IH 20 ns

7 Clock period t CLK 190 244 300 ns

8 CK Input Low t CL 85 122 150 ns

9 CK Input High tCH 85 122 150 ns

10 Clock Rise/Fall Time tr,tf 10 ns

2.0V 0.8V STi tFRW tCLK tCH tCL tFRS tST IS tST IH tFRH Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch.0 Bit 5 Ch. 0 Bit 5 tDAA 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V FR STo tr tf STi

† Timing is over recommended temperature & power supply voltages (VDD =5V±5%, VSS =0V, TA=–40 to 85°C). ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 17 - GCI Timing (CLKM bit=0) Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Clock Period t CK 150 244 300 ns

2 Pulse Width t CL , tCH 73 122 150 ns

3 Frame Width High t WFH 244 ns

4 Frame Setup t FRS 10 190 ns

5 Frame Hold t FRH 20 190 ns

6 Data Delay/Clock Active to

tDAA 45 100 ns C L=150 pF

7 Serial Input Setup t ST IS 20 ns

8 Serial Input Hold t ST IH 20 ns

9 Clock Rise/Fall Time t r, tf 10 ns

2.0V 0.8V STo CLK FR CLK FR STi/ STo See Detail a Detail a Note: bit 0 identifies the first bit of the GCI frame tCL tCH tCK tDAA tWFH tFRS tFRH tST IS tST IH STi Ch. 0 Bit 6 Ch. 0 Bit 7 Ch. 0 Bit 4 Ch. 0 Bit 5 Ch. 31 Bit 0 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V tr tf

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 O U T P U T S STo0/9 Delay - Active to High ZtSAZ 100 ns R L=1 KΩ *, CL=150 pF

2 STo0/9 Delay - High Z to Active t SZA 100 ns C L=150 pF

3 Output Driver Enable Delay t OED 65 ns R L=1 KΩ *, CL=150 pF

4 CSTo Output Delay t XCD 06 0 n s C L=150 pF

Figure 18 - Serial Outputs and External Control CSTo CLK STo0 to STo9 STo0 to STo9 Bit Cell Boundary (GCI) (ST-BUS) t SAZ tSZA tXCD 2.0V 0.8V 2.4V 0.4V 2.4V 0.4V 2.4V 0.4V Figure 19 - Output Driver Enable ODE STo0 to STo9 2.0V 0.8V 2.4V 0.4V tOED tOED (refer to Figures 20-25) Characteristics Sym Min Typ Max Units Test Conditions

1 Clock Period

4.096Mb/s 8.192Mb/s tCK 190 110 244 122 300 150 ns ns

2 Clock Pulse High

4.096Mb/s 8.192Mb/s t CH 122 150 ns ns

3 Clock Pulse Low

4.096Mb/s 8.192Mb/s t CL 122 150 ns ns

4 Frame Sync Setup

4.096Mb/s 8.192Mb/s tFS 190 ns ns

5 Frame Sync Hold

4.096Mb/s 8.192Mb/s t FH 190 ns ns

• High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.

6 Frame Sync Width

4.096Mb/s 8.192Mb/s tFW 244 122 ns ns

7 Valid Data Delay from CK Input

4.096Mb/s 8.192Mb/s t DD ns ns C L=150 pF C L= 50 pF

8 Input Data Setup

4.096Mb/s 8.192Mb/s t DS ns ns

9 Input Data Hold

4.096Mb/s 8.192Mb/s t DH ns ns

10 STo Delay from Active to High Z

4.096Mb/s 8.192Mb/s t AZ ns ns C L=150 pF, RL=1 KΩ * C L= 50 pF, RL=1 KΩ *

11 STo Delay from High Z to Active

4.096Mb/s 8.192Mb/s tZA ns ns C L=150 pF C L= 50 pF]

12 Output Drive Enable Delay

4.096Mb/s 8.192Mb/s t OED ns ns C L=150 pF, RL=1 KΩ * C L= 50 pF, RL=1 KΩ * (refer to Figures 20-25) Characteristics Sym Min Typ Max Units Test Conditions

Figure 22 - Rate Conversion Mode (DMO bit=1) - 4 Mb/s to 2 Mb/s CLK (4.096 MHz) FR (positive) STo STi CLK (4.096 MHz) FR (negative) STo STi Ch. 0 Bit 7 Ch. 0 Bit 5 Ch. 0 Bit 6 Ch. 63 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 5 Ch. 0 Bit 6 Ch. 63 Bit 0 t CK tCH tCL tFS tFH tFW tDS tAZ tZA tDD tFS tFH tFW tDD tDS tDH Ch. 0 Bit 5 High Z 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V tDH

Figure 23 - Rate Conversion Mode (DMO bit=1) - 2 Mb/s to 4 Mb/s CLK (4.096 MHz) FR (positive) STo STi CLK (4.096 MHz) FR (negative) STo STi Ch. 0 Bit 7 High ZCh. 0 Bit 5 Ch. 0 Bit 6 tCK tFS tFH tCH tCL tFW tDD tAZ Ch. 63 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 5 Ch. 0 Bit 6 Ch. 63 Bit 0 tDS tDH Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 31 Bit 0 tFS tFH tDD tDS tDH tFW Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 31 Bit 0 Ch. 0 Bit 5 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V tZA

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 ALE pulse width t ALW 20 ns

2 Address setup from ALE falling t ADS 8n s

3 Address hold from ALE falling t ADH 9n s

4R D active after ALE falling t ALRD 9n s

5 Data setup from DTA Low on Read t DDR 10 ns C L=150 pF

6C S hold after RD /WR tCSRW 0n s 7R D pulse width (fast read) t RW 80 ns 8C S setup from RD tCSR 0n s

9 Data hold after RD tDHR 10 50 90 ns C L=150 pF,RL=1 KΩ∗

10 WR pulse width (fast write) t WW 90 ns

11 WR delay after ALE falling t ALWR 10 ns

12 CS setup from WR tCSW 0n s

13 Data setup from WR (fast write) tDSW 90 ns

14 Valid Data Delay on write

(slow write) tSWD 122 ns

15 Data hold after WR inactive t DHW 8n s

16 Acknowledgement Delay:

Reading/Writing Conn. Memories Writing to Control & Mode Reg. Reading from Control & Mode Reg. tAKD 560 1220 125 ns ns ns ns C L=150 pF

17 Acknowledgement Hold Time t AKH 10 60 110 ns C L=150 pF,RL=1 KΩ *

Figure 26 - Intel/National Multiplexed Bus Timing AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A ALE AD0- AD7 CS RD WR DTA tALW tADS tADH DATAADDRESS tALRD tSWD tCSRW tRW tDHR tWW tDHWtCSW tALWR tAKD tDDR tAKH 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V tDSW tCSR

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 AS pulse width t ASW 80 ns

2 Address setup from AS falling t ADS 8n s

3 Address hold from AS falling t ADH 9n s

4 Data setup from DTA Low on Read t DDR 10 ns C L=150 pF

5C S hold after DS falling t CSH 0n s 6C S setup from DS rising t CSS 0n s

7 Data hold after write t DHW 8n s

8 Data setup from DS - write

(fast write) tDWS 25 ns

9 Valid Data Delay on write

(slow write) tSWD 122 ns

10 R/W setup from DS rising t RWS 60 ns

11 R/W hold after DS falling tRWH 9n s

12 Data hold after read t DHR 10 50 90 ns C L=150 pF,

R L=1 KΩ∗

13 DS delay after AS falling tDSH 10 ns

14 Acknowledgement Delay:

Reading/Writing Conn. Memories Writing Control & Mode Regs. Reading from Control & Mode Regs. tAKD 560 1220 125 ns ns ns ns C L=150 pF

15 Acknowledgement Hold Time t AKH 10 60 110 ns C L=150 pF,

R L=1 KΩ∗

Figure 27 - Motorola Multiplexed Bus Timing AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A CS DTA AD7-0 RD DS R/W AS ADDRESS ADDRESS DATA DATA tRWH tRWS tASW tDSH tADS tADH tSWD tDWS tDHW tDHR tCSS tCSH tAKD tAKH tDDR 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V AAA AAA AAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A A A AD7-0 WR 2.0V 0.8V

† Timing is over recommended temperature & power supply voltages . ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions 1C S Setup from DS rising t CSS 0n s 2R / W Setup from DS rising t RWS 30 ns

3 Add setup from DS rising t ADS 5n s

4C S hold after DS falling t CSH 0n s 5R / W hold after DS falling t RWH 5n s

6 Add hold after DS falling t ADH 5n s

7 Data setup from DTA Low on Read t DDR 10 ns C L=150 pF

8 Data hold on read tDHR 10 50 90 ns C L=150 pF,

R L=1 KΩ∗

9 Data setup on write (fast write) t DSW 20 ns

10 Valid Data Delay on write

(slow write) tSWD 122 ns

11 Data hold on write t DHW 8n s

12 Acknowledgement Delay:

Reading/Writing Conn. Memories Writing Control & Mode Regs. Reading from Control & Mode Regs. tAKD 560 1220 155 ns ns ns ns C L=150 pF

13 Acknowledgement Hold Time t AKH 10 60 110 ns C L=150 pF,

R L=1 KΩ∗

Figure 28 - Motorola Non-Multiplexed Bus Timing DS CS R/W A0-A6 D0-D7 READ D0-D7 WRITE DTA tCSS tRWS tADS tCSH tRWH tADH VALID DATA tSWD tDSW tDHR tDDR tAKD tDHW tAKH VALID DATA 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V