MT8981D

MT8981D ZARLINK | Alldatasheet

Document overview

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Technical content

Features

• Zarlink ST -BUS compatible
• 4-line x 32-channel inputs
• 4-line x 32-channel outputs
• 128 ports non-blocking switch
• Single power supply (+5 V)
• Low power consumption: 30 mW Typ.
• Microprocessor-control interface
• Three-state serial outputs

Description

This VLSI ISO-CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to 128 64 kbit/s channels. Each of the four serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s ST -BUS stream. In addition, the MT8981 provides microprocessor read and write access to individual ST -BUS channels. Figure 1 - Functional Block Diagram STo0 STo1 STo2 STo3 Serial to Parallel Converter Data Memory Frame Counter Control Register Control Interface Output MUX Connection Memory Parallel to Serial Converter CS R/W A5/ DTA D7/ C4i F0i VDD VSS ODE STi0 STi1 STi2 STi3 DS ISSUE8 March 1997 MT8981D Digital Switch ISO-CMOS ST -BUS FAMIL Y

Ordering Information

MT8981DE 40 Pin Plastic DIP MT8981DP 44 PLCC -40 C to +85 C

Figure 2 - Pin Connections Pin Description Pin # Name Description DIP PLCC

12 D T A

Data Acknowledgement (Open Drain Output). This is the data acknowledgement on the microprocessor interface. This pin is pulled low to signal that the chip has processed the data. A 909 Ω , 1/4W, resistor is recommended to be used as a pullup. 2-4 3-5 STi0- STi2 ST-BUS Input 0 to 2 (Inputs). These are the inputs for the 2048 kbit/s ST -BUS input streams. 5 7 STi3 ST-BUS Input 3 (Input). These are the inputs for the 2048 kbit/s ST -BUS input streams. 6-9 8-11 IC Internal Connections. Must be connected to V DD 10 12 V DD Power Input. Positive Supply. 11 13 F0i Framing 0-Type (Input). This is the input for the frame synchronization pulse for the 2048 kbit/s ST -BUS streams. A low on this input causes the internal counter to reset on the next negative transition of C4i. 12 14 C4i 4.096 MHz Clock (Input). ST -BUS bit cell boundaries lie on the alternate falling edges of this clock. 13- 15- A0-A2 Address 0 to 2 (Inputs). These are the inputs for the address lines on the microprocessor interface. 16- 19- A3-A5 Address 3 to 5 (Inputs). These are the inputs for the address lines on the microprocessor interface 19 22 DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface. 20 23 R/W Read or Write (Input). This is the input for the read/write signal on the microprocessor interface - high for read, low for write. 21 24 CS Chip Select (Input). This is the input for the active low chip select on the microprocessor interface. 17 29 STi3 IC IC IC IC VDD F C4i STo3 IC IC IC IC VSS NC STi1 DTA ODE STo1 NC NC DS CS NC R/W

44 PIN PLCC

F C4i DS IC ODE STo0 STo1 STo2 STo3 IC IC IC IC VSS C S R/W

40 PIN PLASTIC DIP

Data 7 to 5 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor interface. 25- 29- D4-D0 Data 4 to 0 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor interface. 30 34 V SS Power Input. Negative Supply (Ground). 31- 35- IC Internal Connections. Leave pins disconnected. 35 39 STo3 ST-BUS Output 3 (Three-state Outputs). These are the pins for the four 2048 kbit/s ST - BUS output streams. 36- 41- STo2- STo0 ST-BUS Output 2 to 0 (Three-state Outputs). These are the pins for the four 2048 kbit/s ST -BUS output streams. 39 44 ODE Output Drive Enable (Input). If this input is held high, the STo0-STo3 output drivers function normally. If this input is low, the STo0-STo3 output drivers go into their high impedance state. NB: Even when ODE is high, channels on the STo0-STo3 outputs can go high impedance under software control. 40 1 IC Internal Connection. Leave pin disconnected. Pin Description (continued) Pin # Name Description DIP PLCC

In recent years, there has been a trend in telephony towards digital switching, particularly in association with software control. Simultaneously, there has been a trend in system architectures towards distributed processing or multi-processor systems. In accordance with these trends, Zarlink has devised the ST -BUS (Serial Telecom Bus). This bus architecture can be used both in software-controlled digital voice and data switching, and for interprocessor communications. The uses in switching and in interprocessor communications are completely integrated to allow for a simple general purpose architecture appropriate for the systems of the future. The serial streams of the ST -BUS operate continuously at 2048 kbit/s and are arranged in 125 µ s wide frames which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST -BUS; a key device being the MT8981 chip. The MT8981 can switch data from channels on ST - BUS inputs to channels on ST -BUS outputs, and simultaneously allows its controlling microprocessor to read channels on ST -BUS inputs or write to channels on ST -BUS outputs (Message Mode). To the microprocessor, the MT8981 looks like a memory peripheral. The microprocessor can write to the MT8981 to establish switched connections between input ST -BUS channels and output ST -BUS channels, or to transmit messages on output ST -BUS channels. By reading from the MT8981, the microprocessor can receive messages from ST -BUS input channels or check which switched connections have already been established. By integrating both switching and interprocessor communications, the MT8981 allows systems to use distributed processing and to switch voice or data in an ST -BUS architecture. Hardware Description Serial data at 2048 kbit/s is received at the four ST - BUS inputs (STi0 to STi3), and serial data is transmitted at the four ST -BUS outputs (STo0 to STo3). Each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g., Zarlink’s MT8964). This serial input word is converted into parallel data and stored in the 128 X 8 Data Memory. Locations in the Data Memory are associated with particular channels on particular ST -BUS input streams. These locations can be read by the microprocessor which controls the chip. Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST -BUS output streams. When a channel is due to be transmitted on an ST -BUS output, the data for the channel can either be switched from an ST -BUS input or it can originate from the microprocessor. If the data is switched from an input, then the contents of the Connection Memory Low location associated with the output channel is used to address the Data Memory. This Data Memory address corresponds to the channel on the input ST -BUS stream on which the data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode), then the contents of the Connection Memory Low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes. The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives address information at A5 to A0 and handles the microprocessor control signals CS DTA, R/W and DS. There are two parts to any address in the Data Memory or Connection Memory. The higher order bits come from the Figure 3 - Address Memory Map A5 A4 A3 A2 A1 A0 HEX ADDRESS LOCATION X X X X X 00 - 1F Control Register * Channel 0 Channel 1 Channel 31 * Writing to the Control Register is the only fast transaction. † Memory and stream are specified by the contents of the Control Register.

Control Register, which may be written to or read from via the Control Interface. The lower order bits come from the address lines directly. The Control Register also allows the chip to broadcast messages on all ST -BUS outputs (i.e., to put every channel into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the Connection Memory Low. The Connection Memory High determines whether individual output channels are in Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of MT8981s to be constructed. It also controls the CSTo pin. All ST -BUS timing is derived from the two signals C4i and F0i. Software Control The address lines on the Control Interface give access to the Control Register directly or, depending on the contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory. If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory and stream selected in the Control Register. The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and the stream address bits define one of the ST -BUS input or output streams. Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the Connection Memory Low. The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e., the contents of the Connection Memory Low are output on the ST -BUS output streams once every frame unless the ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1, regardless of the actual values. Figure 4 - Control Register Bits BIT NAME DESCRIPTION

7 Split

When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory Low, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.

6 Message

When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when the ODE pin is low. When 0, the Connection Memory bits for each channel determine what is output. 5 (unused) 4-3 Memory Select Bits 0-0 - Not to be used 0-1 - Data Memory (read only from the microprocessor port) 1-0 - Connection Memory Low 1-1 - Connection Memory High 2 (unused) Must be a 0. 1-0 Stream Address Bits The number expressed in binary notation on these bits refers to the input or output ST -BUS stream which corresponds to the subsection of memory made accessible for subsequent operations. 76 5432 10 Mode Control Bits (unused) Memory Select Bits Stream Address Bits (unused)

Figure 5 - Connection Memory High Bits Figure 6 - Connection Memory Low Bits BIT NAME DESCRIPTION

2 Message

When 1, the contents of the corresponding location in Connection Memory Low are output on the location’s channel and stream. When 0, the contents of the corresponding location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location’s channel and stream.

1 Unused

0 Output

If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the output driver for the location’s channel and stream. This allows individual channels on individual streams to be made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it. BIT NAME DESCRIPTION 7 (Unused) Must be a 0. 6-5* Stream Address Bits* The number expressed in binary notation on these 2 bits is the number of the ST -BUS stream for the source of the connection. Bit 6 is the most significant bit. e.g., if bit 6 is 1, and bit 5 is 0, then the source of the connection is a channel on STi2. 4-0* Channel Address Bits* The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (The ST -BUS stream where the channel lies is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19. *If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. 76 5432 1 0 No Corresponding Memory - These bits give 0s if read. Per Channel Control Bits 76 5432 1 0 76 5432 1 0 (unused) Stream Address Bits Channel Address Bits

If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally (see Fig. 5). If bit 2 is 1, the associated ST - BUS output channel is in Message Mode; i.e., the byte in the corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the ST -BUS input stream and channel where the byte is to be found (see Fig. 6). If the ODE pin is low, then all serial outputs are high- impedance. If it is high and bit 6 in the Control Register is 1, then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the Connection Memory High location enables the output drivers for the corresponding individual ST -BUS output stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5).

Applications

Use in a Simple Digital Switching System Fig. 7 and 8 show how MT8981s can be used with MT8964s to form a simple digital switching system. Fig. 7 shows the interface between the MT8981s and the filter/codecs. Fig. 8 shows the position of these components in an example architecture. The MT8964 filter/codec in Fig. 7 receives and transmits digitised voice signals on the ST -BUS input D R , and ST -BUS output D X , respectively. These signals are routed to the ST -BUS inputs and outputs on the top MT8981, which is used as a digital speech switch. The MT8964 is controlled by the ST -BUS input D C originating from the bottom MT8981, which generates the appropriate signals from an output channel in Message Mode. This architecture optimises the messaging capability of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an ST -BUS output. This signalling ST -BUS output is monitored by a microprocessor (not shown) through an ST -BUS input on the bottom MT8981. Fig. 8 shows how a simple digital switching system may be designed using the ST -BUS architecture. This is a private telephone network with 128 extensions which uses a single MT8981 as a speech switch and a second MT8981 for communication with the line interface circuits. A larger digital switching system may be designed by cascading a number of MT8981s. Fig. 9 shows how four MT8981s may be arranged in a non-blocking configuration which can switch any channel on any of the ST -BUS inputs to any channel on the ST -BUS outputs. Figure 7 - Example of Typical Interface between 8981s and 8964s for Simple Digital Switching System 8981 used as speech switch MT8981 STo0 STi0 STo0 STi0 MT8981 8981 used in message mode for control and signalling DX DR DC MT8964 Filter/Codec Signalling Logic Line Driver and 2- to 4- Wire Converter Line Interface Circuit with 8964 Filter/Codec

Figure 10 - Application Circuit with 6802 MEK6802D3 System D7-D0 A15-A0 R/W MR VMA E A15 A14 A13 VMA A12 A11 A10 VMA MD HCT 138 MD HCT 138 MD HCT 138 MD HCT 138 MD HCT 240 D TA CS C4i F0i MR

4 MHz2M

Ω C4i SN HCT 393 SN HCT 393 909 Ω 1/4W MT 8980 DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 VDD F C4i DS R/W

40 CSTo

C S 510 Ω 100pF5V1

• Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. Figure 11 - Output Test Load Absolute Maximum Ratings* Parameter Symbol Min Max Units DD - V SS -0.3 7 V

2 Voltage on Digital Inputs V

I V SS -0.3 V DD+0.3 V 3 Voltage on Digital Outputs V O VSS-0.3 V DD+0.3 V

4 Current at Digital Outputs I O 40 mA

5 Storage Temperature T S -65 +150 °C

6 Package Power Dissipation P D 2W

Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Operating Temperature T OP -40 +85 °C

2 Positive Supply V DD 4.75 5.25 V

3 Input Voltage V I 0V DD V

Characteristics Sym Min Typ ‡ Max Units Test Conditions 1 I N P U T S Supply Current I DD 6 10 mA Outputs unloaded 2 Input High Voltage V IH 2.0 V 3 Input Low Voltage V IL 0.8 V

4 Input Leakage I IL 5 µAV I between VSS and VDD

5 Input Pin Capacitance C I 8p F

O U T P U T S Output High Voltage V OH 2.4 V I OH = 10 mA 7 Output High Current I OH 10 15 mA Sourcing. V OH=2.4V 8 Output Low Voltage V OL 0.4 V I OL = 5 mA 9 Output Low Current I OL 5 10 mA Sinking. V OL = 0.4V

10 High Impedance Leakage I OZ 5 µAV O between VSS and VDD

11 Output Pin Capacitance C O 8p F

when testing output levels or high impedance states. S2 is switched to VDD or VSS when testing output levels or high impedance states.

† Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Contents of Connection Memory are not lost if the clock stops, however, ST -BUS outputs go into the high impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i Figure 12 - Frame Alignment Figure 13 - Clock Timing Characteristics Sym Min Typ ‡ Max Units Test Conditions I N P U T S Clock Period* t CLK 220 244 300 ns

2 Clock Width High t CH 95 122 150 ns

3 Clock Width Low t CL 110 122 150 ns

4 Clock Transition Time t CTT 20 ns

5 Frame Pulse SetupTime t FPS 20 200 ns

6 Frame Pulse Hold Time t FPH 0.020 50 µs

7 Frame Pulse Width t FPW 244 ns

2.0V 0.8V 2.0V 0.8V C4i F0i BIT CELLS Channel 31 Bit o Channel 0 Bit 7

† Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. Characteristics Sym Min Typ ‡ Max Units Test Conditions O U T P U T S STo0/3 Delay - Active to High Z t SAZ 20 50 80 ns R L=1 KΩ*, CL=150 pF

2 STo0/3 Delay - High Z to Active t SZA 25 60 125 ns C L=150 pF

3 STo0/3 Delay - Active to Active t SAA 30 65 125 ns C L=150 pF

4 STo0/3 Hold Time t SOH 25 45 ns C L=150 pF

5 Output Driver Enable Delay t OED 45 125 ns R L=1 KΩ*, CL=150 pF

6 External Control Hold Time t XCH 05 0 n s C L=150 pF

7 External Control Delay t XCD 75 110 ns C L=150 pF

N Serial Input Setup Time t SIS -40 -20 ns

9 Serial Input Hold Time t SIH 90 ns

Figure 14 - Serial Outputs and External Control Figure 15 - Output Driver Enable Figure 16 - Serial Inputs C4i 2.0V 0.8V STo0 to STo3 2.4V 0.4V STo0 to STo3 2.4V 0.4V STo0 to 2.4V 0.4V Bit Cell Boundary STo3 t SOH tSAZ tSZA tSOH tSAA Bit Cell Boundaries C4i 2.0V 0.8V 2.0V 0.8V tSIS tSIH STi0 to STi3 ODE 2.0V 0.8V STo0 to STo3 2.4V 0.4V tOED tOED

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. ➀ Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period. Figure 17 - Processor Bus Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Chip Select Setup Time t CSS 20 0 ns

2 Read/Write Setup Time t RWS 25 5 ns

3 Address Setup Time t ADS 25 5 ns

4 Acknowledgement Delay Fast

tAKD 40 100 ns C L=150 pF tAKD 2.7 7.2 cycles C4i cycles➀

5 Fast Write Data Setup Time t FWS 20 ns

6 Slow Write Data Delay t SWD 2.0 1.7 cycles C4i cycles➀ 7 Read Data Setup Time t RDS 0.5 cycles C4i cycles➀, CL= 150 pF

8 Data Hold Time Read

tDHT 20 ns R L=1 KΩ∗, CL=150 pF tDHT 20 10 ns

9 Read Data To High Impedance t RDZ 50 90 ns R L=1 KΩ∗, CL=150 pF

10 Chip Select Hold Time t CSH 0n s

11 Read/Write Hold Time t RWH 0n s

12 Address Hold Time t ADH 0n s

13 Acknowledgement Hold Time t AKH 10 60 80 ns R L=1 KΩ∗, CL=150 pF

2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.4V 0.4V 2.4V (Read) 2.0V (Write) 0.8V (Read 0.8V (Write) CS R/W DTA tCSS tRWS tADS tAKD tRDS tSWD tFWS tCSH tRWH tADH tAKH tDHT tRDZ to to

Notes:

www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I 2C Patent rights to use these components in and I 2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE For more information about all Zarlink products visit our Web Site at