MT8979AC

MT8979 MITEL | Alldatasheet

Document overview

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Technical content

Features

• Single chip primary rate 2048 kbit/s CEPT transceiver with CRC-4 option
• Meets CCITT Recommendation G.704
• Selectable HDB3 or AMI line code
• Tx and Rx frame and multiframe synchronization signals
• Two frame elastic buffer with 32 µsec jitter buffer
• Frame alignment and CRC error counters
• Insertion and detection of A, B, C, D signalling bits with optional debounce
• On-chip attenuation ROM with option for ADI codecs
• Per channel, overall and remote loop around
• ST-BUS compatible

Applications

• Primary rate ISDN network nodes
• Multiplexing equipment
• Private network: PBX to PBX links
• High speed computer to computer links

Description

The MT8979 is a single chip CEPT digital trunk transceiver that meets the requirements of CCITT Recommendation G.704 for digital multiplex equipment. The MT8979 is fabricated in Mitel’s low power ISO-CMOS technology. Figure 1 - Functional Block Diagram V DD RxD RxA RxB TxA TxB E2i E8Ko V SS CEPT Link Interface Digital Attenuator ROM ST-BUS Timing Circuitry PCM/Data Interface Serial Control Interface ABCD Bit RAM Control Logic Phase Detector CEPT Counter TxMF C2i F0i RxMF DSTi DSTo ADI CSTi0 CSTi1 CSTo XCtl XSt Remote Digital Loop- backs

2 Frame

Ordering Information

MT8979AC 28 Pin Ceramic DIP MT8979AE 28 Pin Plastic DIP MT8979AP 44 Pin PLCC -40° to 85°C ISSUE 7 May 1995 MT8979 CEPT PCM 30/CRC-4 Framer & Interface ISO-CMOS ST-BUS  FAMILY

Figure 2 - Pin Connections Pin Description Pin # Name Description DIP PLCC 1 2 TxA Transmit A (Output): A split phase unipolar signal suitable for use with TxB and an external line driver and transformer to construct the bipolar line signal. 2 3 TxB Transmit B (Output :) A split phase unipolar signal suitable for use with TxA and an external line driver and transformer to construct the bipolar line signal. 3 5 DSTo Data ST-BUS (Output) : A 2048 kbit/s serial output stream which contains the 30 PCM or data channels received from the CEPT line. 4 4 NC No Connection.

59 R x A

Receive A (Input): Received split phase unipolar signal decoded from a bipolar line receiver. 61 0 R x B Receive B (Input): Received split phase unipolar signal decoded from a bipolar line receiver. 7 11 RxD Received Data (Input) : Input of the unipolar data generated from the line receiver. This data may be NRZ or RZ. 8 13 CSTi1 Control ST-BUS Input #1 : A 2048 kbit/s stream that contains channel associated signalling, frame alignment and diagnostic functions. 9 NC No Connection. 10 NC No Connection. 11 17 ADI Alternate Digit Inversion (Input) : If this input is high, the CEPT timeslots which are specified on CSTi0 as voice channels are ADI coded and decoded. When this bit is low it disables ADI coding for all channels. This feature allows either ADI or non-ADI codecs to be used on DSTi and DSTo. 12 19 CSTi0 Control ST-BUS Input #0 : A 2048 kbit/s stream that contains 30 per channel control words and two Master Control Words.

44 PIN PLCC

28 PIN CERDIP/PDIP

2318 19 20 21 22 24 25 26 27 28 17 29 NC

13 20 E8Ko Extracted 8 kHz Clock (Output) : An 8 kHz output generated by dividing the extracted 2048 kHz clock by 256 and aligning it with the received CEPT frame. The 8 kHz signal can be used for synchronizing the system clock to the extracted 2048 kHz clock. Only valid when device achieves synchronization (goes low during a loss of signal or a loss of basic frame synchronization condition). E8Ko goes high impedance when 8kHzSEL = 0 in MCW2. 15 23 XCtl External Control (Output): An uncommitted external output pin which is set or reset via bit 1 in Master Control Word 2 on CSTi0. The state of XCtl is updated once per frame. 16 24 XSt External Status : The state of this pin is sampled once per frame and the status is reported in bit 1 of the Master Status Word 1 on CSTo. 17 26 CSTo Control ST-BUS Output : A 2048 kbit/s serial control stream which provides the 16 signalling words, two Master Status Words, Phase Status Word and CRC Error Count. 18 NC No Connection. 19 28 DSTi Data ST-BUS Input : This pin accepts a 2048 kbit/s serial stream which contains the 30 PCM or data channels to be transmitted on the CEPT trunk. 20 NC No Connection. 21 34 C2i 2048 kbit/s System Clock (Input) : The master clock for the ST-BUS section of the chip. All data on the ST-BUS is clocked in on the falling edge of the C2i and output on the rising edge. The falling edge of C2i is also used to clock out data on the CEPT transmit link. 22 37 TxMF Transmit Multiframe Boundary (Input): This input can be used to set the channel associated and CRC transmitted multiframe boundary (clear the frame counters). The device will generate its own multiframe if this pin is held high. 23 38 RxMF Received Multiframe Boundary (Output): An output pulse delimiting the received Multiframe boundary. (This multiframe is not related to the received CRC multiframe.) The next frame output on the data stream (DSTo) is received as frame 0 on the CEPT link. 24 NC No Connection. 25 40 E2i Extracted 2048 kHz Clock (Input) : The falling edge of this 2048 kHz clock is used to latch the received data (RxD). This clock input must be derived from the CEPT received data and must have its falling edge aligned with the center of the received bit (RxD). 26 42 F0i Frame Pulse Input: The ST-BUS frame synchronization signal which defines the beginning of the 32 channel frame. 27 44 IC Internal Connection : Tie to VSS (Ground) for normal operation. 28 1 V DD Positive Power Supply Input (+5 Volts). 14 6,8, VSS Negative Power Supply Input (Ground). Pin Description (Continued) Pin # Name Description DIP PLCC

The MT8979 is a CEPT trunk digital link interface conforming to CCITT Recommendation G.704 for PCM 30 and I.431 for ISDN. It includes features such as: insertion and detection of synchronization patterns, optional cyclical redundancy check and far end error performance reporting, HDB3 decoding and optional coding, channel associated or common channel signalling, programmable digital attenuation and a two frame received elastic buffer. The MT8979 can also monitor several conditions on the CEPT digital trunk, which include, frame and multiframe synchronization, received all 1’s alarms, data slips as well as framing and CRC errors, both near and far end. The system interface to the MT8979 is a TDM bus structure that operates at 2048 kbit/s known as the ST-BUS. This serial stream is divided into 125 µs frames that are made up of 32 x 8 bit channels. The line interface to the MT8979 consists of split phase unipolar inputs and outputs which are supplied from/to a bipolar line receiver/driver, respectively. CEPT Interface The CEPT frame format consists of 32, 8 bit timeslots. Of the 32 timeslots in a frame, 30 are defined as information channels, timeslots 1-15 and 17-31 which correspond to telephone channels 1-30. An additional voice/data channel may be obtained by placing the device in common channel signalling mode. This allows use of timeslot 16 for 64 kbit/s common channel signalling. Synchronization is included within the CEPT bit stream in the form of a bit pattern inserted into timeslot 0. The contents of timeslot 0 alternate between the frame alignment pattern and the non-frame alignment pattern as described in Figure 4. Bit 1 of the frame alignment and non-frame alignment bytes have provisions for additional protection against false synchronization or enhanced error monitoring. This is described in more detail in the following section. In order to accomplish multiframe synchronization, a 16 frame multiframe is defined by sending four zeros in the high order quartet of timeslot 16 frame 0, i.e., once every 16 frames (see Figure 5). The CEPT format has four signalling bits, A, B, C and D. Signalling bits for all 30 information channels are transmitted in timeslot 16 of frames 1 to 15. These timeslots are subdivided into two quartets (see Table 6). Cyclic Redundancy Check (CRC) An optional cyclic redundancy check (CRC) has been incorporated within CEPT bit stream to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability. The CRC process treats the binary string of ones and zeros contained in a submultiframe (with CRC bits set to binary zero) as a single long binary number. This string of data is first multiplied by x 4 then divided by the generating polynomial x4+x+1. This division process takes place at both the transmitter and receiver end of the link. The remainder calculated at the receiver is compared to the one received with the data over the link. If they are the same, it is of high probability that the previous submultiframe was received error free. The CRC procedure is based on a 16 frame multiframe, which is divided into two 8 frame submultiframes (SMF). The frames which contain the frame alignment pattern contain the CRC bits, C to C4 respectively, in the bit 1 position. The frames Figure 3 - CEPT Link Frame & Multiframe Format Frame 15 0 14 15 0 Timeslot 0 1 30 31 Most Significant Bit (First) Least Significant Bit (Last) Bit 12 34 5 67 8 FrameFrameFrameFrame Timeslot Timeslot Timeslot Bit Bit Bit Bit Bit BitBit 2.0 ms (8/2.048) µs 125 µs

• •••

end in the Si bits (refer to T able 1). frame boundaries and repeats at an 8 kHz rate. Table 1. Coding of Spare Bits Si1 and Si2 serial input, 30 are defined as information channels. 10 CRC result for SMFII is in error. CRC result for SMFI is error free. 01 CRC result for SMFII is error free. CRC result for SMFI is in error.

00 CRC results for both SMFI, II are

Note 1 : With CRC active, this bit is ignored.

1 Alarm indication to the

• • • Timeslot 16 of frame 15

0000 XYXX

Figure 7 - ST-BUS Stream Format CHANNEL 31 03 0 BIT CHANNEL CHANNEL CHANNEL CHANNEL 31 0 BIT BIT BIT BIT BIT BIT BIT

• • • Least Significant Bit (Last) Most Significant Bit (First) (8/2.048)µs 125µs 765 432 1 0 the ERR bit can be used to evaluate the bit error rate of the line according to the CCITT Recommendation G.732 (see section on Frame Alignment Error Counter). Channel 19 contains the Phase Status Word (see T able 15), which can be used to determine the phase relationship between the ST-BUS frame pulse (F0i and the rising edge of E8Ko. This information could be used to determine the long term trend of the received data rate, or to identify the direction of a slip. Channel 20 contains the CRC error count (see T able 16). This counter will wrap around once terminal count is achieved (256 errors). If the maintenance option is selected (bit 3 of MCW3) the counter is reset once per second. Channel 21 contains the Master Status Word 2 (see T able 17). This byte identifies the status of the CRC reframe and CRC sync. It also reports the Si bits received in timeslot 0 of frames 13 and 15 and the ninth and most significant bit (b 8) of the 9-bit Phase Status Word. Elastic Buffer The MT8979 has a two frame elastic buffer at the receiver, which absorbs the jitter and wander in the received signal. The received data is written into the elastic buffer with the extracted E2i (2048 kHz) clock and read out of the buffer on the ST-BUS side with the system C2i (2048 kHz) clock (e.g., PBX system clock). Under normal operating conditions, in a synchronous network, the system C2i clock is phase-locked to the extracted E2i clock. In this situation every write operation to the elastic buffer is followed by a read operation. Therefore, underflow or overflow of data in the elastic buffer will not occur. If the system clock is not phase-locked to the extracted clock (e.g., lower quality link which is not selected as the clock source for the PBX) then the data rate at which the data is being written into the device on the line side may differ from the rate at which it is being read out on the ST-BUS side. When the clocks are not phase-locked, two situations can occur: Case #1: If the data on the line side is being written in at a rate SLOWER than it is being read out on the ST-BUS side, the distance between the write pointer and the read pointer will begin to decrease over time. When the distance is less than two channels, the buffer will perform a controlled slip which will move the read pointers to a new location 34 channels away from the write pointer. This will result in the REPETITION of the received frame. Case #2: If the data on the line side is being written in at a rate FASTER than it is being read out on the ST-BUS side, the distance between the write pointer and the read pointer will begin to increase over time. When the distance exceeds 42 channels, the elastic buffer will perform a controlled slip which will move the read pointer to a new location ten channels away from the write pointer. This will result in the LOSS of the last received frame. Note that when the device performs a controlled slip, the ST-BUS address pointer is repositioned so that there is either a 10 channel or 34 channel delay between the input CEPT frame and the output ST-BUS frame. Since the buffer performs a controlled slip only if the delay exceeds 42 channels or is less than two channels, there is a minimum eight channel hysteresis built into the slip mechanism. The device can, therefore, absorb eight channels or 32.5µs of jitter in the received signal. There is no loss of frame synchronization, multiframe synchronization or any errors in the signalling bits when the device performs a slip.

Frame Alignment Error Counter The MT8979 provides an indication of the bit error rate found on the link as required by CCITT Recommendation G.703. The ERR bit (Bit 5 of MSW1) is used to count the number of errors found in the frame alignment signal and this can be used to estimate the bit error rate. The ERR bit changes state when 16 errors have been detected in the frame alignment signal. This bit can not change state more than once every 128 ms, placing an upper limit on the detectable error rate at approximately 10 -3. The following formula can be used to calculate the BER: where: 7 - is the number of bits in the frame alignment signal (0011011). 16 - is the number of errored frame alignment signals counted between changes of state of the ERR bit. 4000 - is the number of frame alignment signals in a one second interval. This formula provides a good approximation of the BER given the following assumptions: 1. The bit errors are uniformly distributed on the line. In other words, every bit in every channel is equally likely to get an error. 2. The errors that occur in channel 0 are bit errors. If the first assumption holds and the bit error rate is reasonable, (below 10 -3) then the probability of two or more errors in seven bits is very low. Attenuation ROM All transmit and receive data in the MT8979 is passed through the digital attenuation ROM according to the values set on bits 5 - 0 of data channels in the control stream (CSTi0). Data can be attenuated on a per-channel basis from 1 to -6 dB for both Tx and Rx data (refer Table 2). Digital attenuation is applied on a per-channel basis to the data found one channel after the control information stored in the control channel CSTi0, i.e., control stream 0 channel 4 contains the attenuation setting for data stream (DSTo) channel 5. BER= 16* number of times ERR bit toggles 7 * 4000 * elapsed time in seconds Signalling Bit RAM The A, B, C, & D Bit RAM is used to retain the status of the per-channel signalling bits so that they may be multiplexed into the Control Output Stream (CSTo). This signalling information is only valid when the module is synchronized to the received data stream. If synchronization is lost, the status of the signalling bits will be retained for 6.0 ms provided the signalling debounce is active. Integrated into the signalling bit RAM is a debounce circuit which will delay valid signalling bit changes for 6.0 to 8.0 ms. By debouncing the signalling bits, a bit error will not affect the call in progress. (See T able 3, bits 3-0 of channel 15 on the CSTi0 line.) CEPT PCM 30 Format MUX The CEPT Link Multiplexer formats the data stream corresponding to the CEPT PCM 30 format. This implies that the multiplexer will use timeslots 1 to 15 and 17 to 31 for data and uses timeslots 0 & 16 for the synchronization and channel associated signalling. The frame alignment or non-frame alignment signals for timeslot zero are sourced by the control stream input CSTi1 channel 16 and 17, respectively. The most significant bit of timeslot zero will optionally contain the cyclical redundancy check, CRC multiframe pattern and Si bits used for far-end CRC monitoring. Framing Algorithms There are three distinct framers within the MT8979. These include a frame alignment signal framer, a multiframe framer and a CRC framer. Figure 13 shows the state diagram of the framing algorithms. The dotted lines shows optional features, which are enabled in the maintenance mode. The frame synchronization circuit searches for the first frame alignment signal within the bit stream. Once detected, the frame counters are set to find the non-frame alignment signal. If bit 2 of the non-frame alignment signal is not one, a new search is initiated, else the framer will monitor for the frame alignment in the next frame. If the frame alignment signal is found, the device immediately declares frame synchronization.

The multiframe synchronization algorithm is dependent upon the state of frame alignment framer. The multiframe framer will not initiate a search for multiframe synchronization until frame sync is achieved. Multiframe synchronization will be declared on the first occurrence of four consecutive zeros in the higher order quartet of channel 16. Once multiframe synchronization is achieved, the framer will only go out of synchronization after detection of two errors in the multiframe signal or loss of frame alignment synchronization. The CRC synchronization algorithm is also dependent on the state of the frame alignment framer, but is independent of the multiframe synchronization. The CRC framer will not initate a search for CRC framing signal until frame alignment synchronization is achieved. Once frame alignment synchronization is acquired, the CRC framer must find two framing signals in bit 1 of the non-frame alignment signal. Upon detection of the second CRC framing signal the MT8979 will immediately go into CRC synchronization. When maintenance feature is enabled (maint bit = 1) the CRC framer will force a complete reframe of the device if CRC frame synchronization is not found within 8 ms or more than 914 CRC errors occur per second. Figure 13 - Synchronization State Diagram out of synchronization search for frame alignment signal verify bit 2 of non- frame alignment signal verify second occurrence of frame alignment signal find two CRC frame alignment CRC synchronization acquired search for multiframe align- ment signal multiframe synchro- nization acquired check for two errored multiframe alignment signals No No Yes Yes Yes Yes Yes Yes No # of consecutive incorrect frame alignment signals = 3 time out > 8ms No - - - - - Only if the maintenance option is selected signals No number of CRC errors > 914/s frame synchroni- zation acquired

Table 2. Per Channel Control Word: Data Format for CSTi0 Channels 0-14, and 16-30 Table 3. Master Control 1 (MCW1): Data Format for CSTi0 Channel 15

7 DATA Data Channel: If ‘1‘, then the controlled timeslot on the CEPT 2048 kbit/s link is

transmission or reception, and digital attenuation is disabled.

6 LOOP Per-Channel Loopback: If ‘1‘, then the controlled timeslot on the transmitted

received timeslot. If ‘0‘, then this function is disabled. This function only operates if frame synchronization is received from the CEPT link. If more than one channel is looped per frame only the first one will be active. 5,4,3 RXPAD4,2,1 Receive Attenuation Pad: Per timeslot receive attenuation control bits. 2,1,0 TXPAD4,2,1 Transmit Attenuation Pad: Per timeslot transmit attenuation control bits. 7 (N/A) Keep at ‘1‘ for normal operation.

6 LOOP16 Channel 16 Loopback: If ‘1‘, then timeslot 16 on the transmitted CEPT 2048 kbit/s link

is looped internally to replace the data received on timeslot 16. If ‘0,‘ then this function is disabled. only a single timeslot can be looped within the frame. 5,4 (N/A) Keep at ‘1‘ for normal operation.

Table 4. Master Control 2 (MCW2): Data Format for CSTi0 Channel 31 Table 5. Multiframe Alignment Signal: Data Format for CSTi1 Channel 0 7 (N/A) Keep at ‘1‘ for normal operation. 6 (N/A) Keep at ‘0‘ for normal operation.

5 CCS Common Channel Signalling: If 1, then the MT8979 operates in its common channel

pin. Channel 15 on the CSTi0 pin contains the information for the control of timeslot 16. Channels 0 to 15 on CSTi1 and CSTo are unused. transmit the ABCD signalling bits. received from the CEPT link. If ‘0‘, then the E8Ko pin goes into its high impedance state.

3 TXAIS Transmit Alarm Indication Signal:

If ‘1‘, then an all 1’ s alarm signal is transmitted on all timeslots. If ‘0‘, then the timeslots functions normally.

2 TXTS16AIS Transmit Timeslot 16 Alarm Indication Signal:

If ‘1‘, then an all 1’s alarm signal is transmitted on timeslot 16. If ‘0‘, then timeslot 16 functions normally.

1 XCTL External Control:

If ‘1‘, then the XCtl pin is driven high. If ‘0‘, then the XCtl pin is driven low. should be kept at ‘0‘ to allow multiframe alignment to be detected. frame 0 of the multiframe. It is a spare bit which should be kept at ‘1‘ if unused. received link has been lost. A ‘0’ indicates that multiframe alignment is detected. should be kept at ‘1‘ if unused.

Table 6. Channel Associated Signalling: Data Format for CSTi1 Channels 1 to 15 Table 7. Frame Alignment Signal: Data Format for CSTi1 Channel 16 channels 1 to 15 as this would interfere with multiframe alignment. each multiframe on the CEPT link .

7 IU0 International Use 0: When CRC is disabled, this bit is transmitted on the CEPT 2048

form the frame alignment signal and should be set to ‘0011011‘.

Table 8. Non-Frame-Alignment Signal: Data Format for CSTi1 Channel 17 Table 9. Master Control Word 3 (MCW3): Data Format for CSTi1 Channel 18

7 IU1 International Use 1: When the CRC is disabled and SiMUX bit in MCW3 is disabled, this

6 NFAF Transmit Non-Frame Alignment Bit: This bit is transmitted on the CEPT 2048 kbit/s link

5 ALM Non-Frame Alignment Alarm: This bit is transmitted on the CEPT 2048 kbit/s link in bit

kept at ‘0‘ under normal operation. and on crossing international borders they should be set to ‘1‘. 7N / A Keep at zero for normal operation. outgoing Si2 bit in frame 15.

5 RMLOOP Remote Loopback: If set the RxA

4 HDB3en Enable HDB3 Encoding: A ’1’ will disable the HDB3 line coding and transmit the

3 Maint Maintenance: A ’1’ will force a terminal reframe if the CRC multiframe synchro- nization

with every one second interval). A ’0’ will disable this option.

2 CRCen Enable Cyclical Redundancy Check: A ’1’ will enable the CRC generation on the

regardless of the state of CRCen. 1 DGLOOP Digital Loopack: When set, the transmitted signal is looped around from DSTi to DSTo. The normal received data is interrupted.

0 ReFR Force Reframe: If set, for at least 1 frame, and then cleared the chip will begin to search

the change from high to low will cause a reframe, not a continuous low level.

Table 10. Received Multiframe Alignment Signal: Data Format for CSTo Channel 0 Table 11. Received Channel Associated Signalling: Data Format for CSTo Channels 1 to 15 Table 12. Received Frame Alignment Signal: Data Format for CSTo Channel 16 multiframe. They should all be ‘0‘. timeslot 16 of frame 0 of the multiframe. It is a spare bit which should be ‘1‘ if unused. alignment is detected. It is not debounced. which should be ‘1‘ if unused. They are not debounced. telephone channels 1 to 15 as this implies interference with multiframe alignment. positions 5 to 8 of timeslot 16 in frame 3 of each multiframe on the CEPT link .

7 IU0 International Use 0: This is the bit which is received from the CEPT 2048 kbit/s link in bit

CEPT 2048 kbit/s link in bit positions 2 to 8 of timeslot 0 of frame-alignment frames. These bits form the frame alignment signal and should have the values of ‘0011011‘.

Table 13. Received Non-Frame Alignment Signal: Data Format for CSTo Channel 17 Table 14. Master Status Word 1 (MSW1): Data Format for CSTo Channel 18 Table 15. Phase Status Word (PSW): Data Format for CSTo Channel 19

7 IU1 International Use 1: This is the bit which is received from the CEPT 2048 kbit/s link in

framing or as international bits.

6 NFAF Receive Non-Frame Alignment Bit: This is the bit which is received from the CEPT

5 ALM Non-Frame Alignment Alarm: This is the bit which is received from the CEPT 2048

normal operation and should go to ‘1 ‘to signal an alarm. national use, and on crossing international borders they should have the value ‘1‘.

7 TFSYN

the MT8979. It goes to ‘0‘ when frame synchronization is detected. the MT8979. It goes to ‘0‘ when multiframe synchronization is detected.

5 ERR Frame Alignment Error: This bit changes state when 16 or more errors have been

4 SLIP Control Slip: This bit changes state when a slip occurs between the received CEPT

2048 kbit/s link and the 2048 kbit/s ST-BUS.

3 RXAIS Receive Alarm Indication Signal: This bit goes to ‘1‘ to signal that an all-ones alarm

all-ones alarm signal is removed.

2 RXTS16AIS Receive Timeslot 16 Alarm Indication Signal: This bit goes to ‘1‘ to signal that an

link. It goes to ’0’ when the all-ones alarm signal is removed. 1 XS External Status: This bit contains the data sampled once per frame at the XS pin. between the ST-BUS frame pulse and the rising edge of E8Ko. timeslot count reported in TxTSC above.

Table 16. CRC Error Count: Data Format for CSTo Channel 20 Table 17. Master Status Word 2 (MSW2): Data Format for CSTo Channel 21

3 CRCTimer CRC Timer: Transition from 1 to 0 indicates the start of one second interval in which

CRC errors are accumulated. This bit stays high for 8 ms.

2 CRCRef CRC Reframe: A ’1’ indicates that the receive CRC multiframe synchronization could

not be found within the time out period of 8 ms after detecting frame synchronization. This bit will go low if CRCSync goes low or if Maintenance is not activated. 1 CRCSync CRC Sync: A ’0’ indicates that CRC multiframing has been detected.

0 FrmPhase Frame Count: This is the ninth and most significant bit (b8) of the Phase Status Word

then this bit will toggle when the reading goes below ST-BUS channel 0, bit 0. The MT8979 is only a link interface to the CEPT trunk. As such, an external line driver and receiver is required along with an appropriate pulse transformer before being connected to the line. Transmitter In order to generate a bipolar line signal, the link interface to the MT8979 provides the user with two bipolar steering outputs, TxA and TxB. These correspond to the required positive and negative pulses on the transmission line. Figure 14 shows a recommended output circuit for driving a line pulse transformer. The transistors are driven into saturation when they are turned on, which applies a step function to the transformer. The step input to the transformer produces a nearly constant di/dt before the current reaches steady state. By operating in the transient portion of the inductance response, the secondary of the transformer produces an almost square pulse. The base terminal of the transistors is AC coupled to the MT8979 so that there is no DC path from V DD to ground. Figure 14 - Bipolar Line Driver TxA TxB MT8979 •

• •
• •
• +12V 33µH 47µF TIPo RINGo :.5 1.: 1.:

• Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. † Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Absolute Maximum Ratings* - Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Symbol Min Max Units 1 Supply Voltage V DD -0.3 7 V 2 Voltage at Digital Inputs V I -0.3 V DD + 0.3 V

3 Current at Digital Inputs I I 30 mA

4 Voltage at Digital Outputs V O -0.3 V DD + 0.3 V

5 Current at Digital Outputs I O 30 mA

6 Storage Temperature T ST -65 150 °C

7 Package Power Dissipation P 800 mW

Recommended Operating Conditions - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Operating Temperature T OP -40 85 °C

2 Supply Voltage V DD 4 . 555 . 5 V 3 Input Voltage High V H 2.4 V DD V For 400 mV noise margin 4 Input Voltage Low V L VSS 0.4 V For 400 mV noise margin Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Power Dissipation P 40 88 mW Outputs unloaded

2 Supply Current I DD 8 16 mA Outputs unloaded

3 Input High Voltage V IH 2.0 V DD V 4 Input Low Voltage V IL 00 . 8 V

5 Input Leakage I IL 11 0 µAV I = 0 to VDD

6 Output High Voltage V OH 2.4 V DD VI OH =7 mA @ V OH =2.4 V 7 Output High Current I OH 7 20 mA Source V OH =2.4 V 8 Output Low Voltage V OL VSS 0.4 V I OL =2 mA @ V OL = 0.4 V 9 Output Low Current I OL 2 10 mA Sink V OL =0.4 V

10 High Impedance Leakage I OZ 11 0 µAV O = 0 to VDD

Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Input Pin Capacitance C I 8p F

2 Output Pin Capacitance C O 8p F

† Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. *t SOD = 125 ns (max) over 0 - 70°C temperature range. Figure 17 - Clock and Frame Alignment for 2048 kbit/s ST-BUS Streams Figure 18 - Clock and Frame Timing for 2048 kbit/s ST-BUS Streams Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 C2i Clock Period t P20 400 488 600 ns

2 C2i Clock Width High or Low t W20 200 244 ns t P20 = 488 ns

3 Frame Pulse Setup Time t FPS 50 150 ns

4 Frame Pulse Hold Time t FPH 50 ns

5 Frame Pulse Width t FPW 100 300 ns

6 Serial Output Delay t SOD 150* ns 150 pF Load

7 Serial Input Setup Time t SIS 30 ns

8 Serial Input Hold Time t SIH 55 ns

9 Frame Pulse Setup Time 2 t FPS2 20 ns

Channel 31 Channel 0 Channel 0 Bit 0 Bit 7 Bit 6 ST-BUS Bit Stream Bit Cell F0i C2i DSTi or CSTi0/1 DSTo or CSTo V IL VIH VIL VIH VIL VIH VOL VOH tFPS tFPH tFPW tFPS2 tP20 tSIS tW20 tW20 tSIH tSOD

† Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. *2 5 6 tP20 - 100ns Figure 19 - Functional Timing for Receive Multiframe Clocks Figure 20 - Functional Timing for Transmit Multiframe Clock Figure 21 - Clock and Frame Timing for 2048 kbit/s ST-BUS Streams Note 1: These two signals do not have a defined phase relationship. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Receive Multiframe Output Delay t RMFD 150 ns 50 pF

2 Transmit Multiframe Setup Time t TMFS 50 ns

3 Transmit Multiframe Hold Time t TMFH 50 * ns

4 Tx Multiframe to C2 Setup Time t MF2S 100 ns

Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Bit 7 Frame 0Frame 15 F0i C2i TxMF DSTi Bit Cells Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Bit 7 Frame 0Frame N F0i C2i RxMF (1) TxMF (1) tRMFD tTMFS tMF2S tTMFH tRMFD

† Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 External Control Delay t XCD 100 ns 50 pF load

2 External Status Setup Time t XSS 50 ns

3 External Status Hold Time t XSH 50 ns

4 E8Ko Output Delay t 8OD 150 ns 50 pF load

5 E8Ko Output Low Width t 8OL 62.5 µs 50 pF load 6 E8Ko Output High Width t 8OH 62.5 µs 50 pF load

7 E8Ko Output Transition Time t 8OT 20 ns 50 pF load

ST-BUS Bit Cell Boundary Between Bit 3 Channel 17 and Bit 2 Channel 17 tXSS tXSH C2i XS V IH V IL VIH VIL Figure 24 - E8Ko Timing Timeslot 0 Bit 4 Timeslot 16 Bit 4 Timeslot 0 Bit 4 Received CEPT Bits E2i VIH VIL E8Ko VOH VOL t8OD t8OT t8OD t8OD t8OL t8OH t8OT t8OT

† Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * The difference between tTSD for TxA and TxB is not greater than 20 ns. Figure 25 - Transmit Timing for CEPT Link Figure 26 - Receive Timing for CEPT Link Characteristics Sym Min Typ ‡ Max Units Test Conditions

1 Transmit Steering Delay* t TSD 25 150 ns 200 pF load

2 Transmit Steering Transition Time tTST 40 ns 200 pF load

3 E2i Clock Period t PEC 400 488 600 ns

4 E2i Clock Width High or Low t WEC 200 244 ns

5 Receive Data Setup Time t RDS 30 ns

6 Receive Data Hold Time t RDH 40 ns

7 Receive Steering Setup Time t RSS 30 ns

8 Receive Steering Hold Time t RSH 40 ns

V IH VIL VOH VOL tTST tTSD tTST tTSD Bit Cell Bit CellsReceived CEPT Link Bit Cells E2i RxA or RxB V IH V IL V IH V IL V IH V IL tWEC tWEC tRDS tRDH tRSS tRSH RxD tPEC

Control and Status Register Summary Master Control Word 1 (MCW1) - CSTi0, Channel 15 Master Control Word 2 (MCW2) - CSTi0, Channel 31 Master Control Word 3 (MCW3) - CSTi1, Channel 18 Per Channel Cotnrol Word - CSTi0, Channels 0-14 and 16-30 Channel Associated Signalling - CSTi1, Channels N = 1 to 15 Frame Alignment Signals - CSTi1, Channel 16 Multiframe Alignment Signals - CSTi1, Channel 0 Non-Frame Alignment Signal - CSTi1, Channel 17 76 543 210 UNUSED Keep at 1 LOOP16

1 Enabled

0 Disabled

0 Debounce

1 Common

0 Channel

1 Alarm On

0 Alarm Off

1 Set High

0 Cleared

1 Disabled

0 Enabled

1 No ADI

0 Enable ADI

RxPAD4 RxPAD2 RxPAD1 TxPAD4 TxPAD2 TxPAD1 A(N) Tx Signalling Bit B(N) Tx Signalling Bit C(N) Tx Signalling Bit D(N) Tx Signalling Bit A(N + 15) Tx Signalling Bit B(N + 15) Tx Signalling Bit C(N + 15) Tx Signalling Bit D(N + 15) Tx Signalling Bit IUO Should be kept at 1 FAF2-8 Frame Alignment Signal - Keep at "0011011" MA1-4 Multiframe Alignment Signal - Keep at "0000" Spare Bit Should be 1 Y 1A l a r m O n X2, X3 Spare Bits - Should be 1 IU1 Reserved for International Use NFAF Keep at "1" ALM 1A l a r m O n 0A l a r m O f f NU1-5 Bits Reserved for National Use - Should be kept at "1"

Master Control Word 1 (MSW1) - CSTo, Channel 18 Master Status Word 2 (MSW2) - CSTo, Channel 21 Phase Status Word - CSTo, Channel 19 CRC Error Counter - CSTo, Channel 20 Received Channel Associated Signalling - CSTo, Channels N = 1 to 15 Received Frame Alignment Signals - CSTo, Channel 16 Received Multiframe Alignment Signals - CSTo, Channel 0 Received Non-Frame Alignment Signal - CSTo, Channel 17 76 543 210 TFSYN

1 Out of Sync

0 In Sync

0 No Alarm

1 Alarm

0 XSt Low

is: 1C o r r e c t 0E r r o r e d Si1 Remote SMF1 is:

1 Correct

1 Reframed

1 CRC Frame

0 CRC Frame

Transmit Timeslot Count, Timeslots between F0i and E8Ko TxBTC Transmit Bit Count - bit positions within TxTSC between F0i and E8Ko CERC 0 - 7 Bits 0 - 7 of CRC Error Counter A(N) Rx Signalling Bit B(N) Rx Signalling Bit C(N) Rx Signalling Bit D(N) Rx Signalling Bit A(N + 15) Rx Signalling Bit B(N + 15) Rx Signalling Bit C(N + 15) Rx Signalling Bit D(N + 15) Rx Signalling Bit IUO International Bit FAF2-8 Received Frame Alignment Signal MA1-4 Received Multiframe Alignment Signal International Bit Y

1 Remote MF

0 Remote MF

X2, X3 International Bits IU1 Reserved for International Use NFAF ALM

1 Detected

Received Bits Reserved for National Use

NOTES: