MT8972B

MT8971B MITEL | Alldatasheet

Document overview

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Technical content

Features

• Full duplex transmission over a single twisted pair
• Selectable 80 or 160 kbit/s line rate
• Adaptive echo cancellation
• Up to 3km (8971B) and 4 km (8972B)
• ISDN compatible (2B+D) data format
• Transparent modem capability
• Frame synchronization and clock extraction
• MITEL ST-BUS compatible
• Low power (typically 50 mW), single 5V supply

Applications

• Digital subscriber lines
• High speed data transmission over twisted wires
• Digital PABX line cards and telephone sets
• 80 or 160 kbit/s single chip modem Figure 1 - Functional Block Diagram DSTi/Di CDSTi/ F0/CLD C4 /TCK F0o/RCK MS0 MS1 MS2 RegC DSTo/Do CDSTo/ CDo Transmit Interface Prescrambler Scrambler Control Register Transmit/ Clock Receive Timing & Control Status Transmit Timing Master Clock Phase Locked Sync Detect Receive DPLL Receive Interface De - Prescrambler Descrambler Differentially Encoded Biphase Receiver Differentially Encoded Biphase Transmitter Transmit Filter & Line Driver Receive Filter MUX Address Echo Canceller Error Signal Echo Estimate V Bias VDD VSS VBias VRef LOUT LOUT DIS Precan LIN OSC2 OSC1 CDi ISSUE 7 May 1995

Description

The MT8971B (DSIC) and MT8972B (DNIC) are multi-function devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair. They use adaptive echo-cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modem with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted. The MT8971B/72B is fabricated in Mitel’s ISO CMOS process.

Ordering Information

MT8971BE 22 Pin Plastic DIP MT8972BE 22 Pin Plastic DIP MT8972BC 22 Pin Ceramic DIP MT8971BP 28 Pin PLCC MT8972BP 28 Pin PLCC -40°C to +85°C MT8971B/72B Digital Subscriber Interface Circuit Digital Network Interface Circuit ISO2-CMOS ST-BUS  FAMILY

Figure 2 - Pin Connections Pin Description Pin # Name DescriptionDIP PLCC 12 L OUT Line Out. Transmit Signal output (Analog). Referenced to VBias. 23 V Bias Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to VDD . 34 V Ref Internal Reference Voltage output. Connect via 0.33 µF decoupling capacitor to VDD . 4,5, 5,7, MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the various operating modes for a particular application. See Table 1 for the operating modes. 7 9 RegC Regulator Control output (Digital). A 512 kHz clock used for switch mode power supplies. Unused in MAS/MOD mode and should be left open circuit. 81 0 F 0 /CLD Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative pulse input for the MASTER indicating the start of the active channel times of the device. Output for the SLAVE indicating the start of the active channel times of the device. Output in MOD mode providing a pulse indicating the start of the C-channel. 9 12 CDSTi/ CDi Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control & signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 10 13 CDSTo/ CDo Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial control & signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 11 14 V SS Negative Power Supply (0V). 12 15 DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 13 16 DSTi/Di Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN mode. In MOD mode this is a continuous bit stream at the bit rate selected. 14 17 F0o /RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns wide negative pulse indicating the end of the active channel times of the device to allow daisy chaining. In MOD mode provides the receive bit rate clock to the system. 15 19 C4 /TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin provides the transmit bit rate clock to the system. 16 21 OSC2 Oscillator Output. CMOS Output. 11 12

22 PIN PDIP/CERDIP

/CLD CDSTi/CDi CDSTo/CDo VSS VDD LIN TEST LOUT DIS Precan OSC1 OSC2 /TCK F0o/RCK DSTi/Di DSTo/Do

28 PIN PLCC

• LOUT VBias VRef NC VDD LIN TEST NC LOUT DIS Precan OSC1 OSC2 NC /TCK MS2 NC MS1 MS0 RegC F0/CLD NC CDSTi/CDi CDSTo/CDo VSS DSTo/Do NC F0o/RCK DSTi/Di

The MT8971B/72B is a device which has been designed primarily as an interface for the Integrated Services Digital Network (ISDN). However, it may be used in practically any application that requires high speed data transmission over two wires, including smart telephone sets, workstations, data terminals and computers. In the ISDN, the DNIC is ideal for providing the interface at the U reference point. The device supports the 2B+D channel format (two 64 kbit/s B- channels and one 16 kbit/s D-channel) over two wires as recommended by the CCITT. The line data is converted to and from the ST-BUS format on the system side of the network to allow for easy interfacing with other components such as the S- interface device in an NT1 arrangement, or to digital PABX components. Smart telephone sets with data and voice capability can be easily implemented using the MT8971B/72B as a line interface. The device’s high bandwidth and long loop length capability allows its use in a wide variety of sets. This can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in both the home and central office or remote concentration equipment. Within the subscriber equipment the MT8971B/72B would terminate the line and encode/ decode the data and voice for transmission while additional electronics could provide interfaces for a standard telephone set and any number of data ports supporting standard data rates for such things as computer communications and telemetry for remote meter reading. Digital workstations with a high degree of networking capability can be designed using the DNIC for the line interface, offering up to 160 kbit/s data transmission over existing telephone lines. The MT8971B/72B could also be valuable within existing computer networks for connecting a large number of terminals to a computer or for intercomputer links. The highest data rates existing for terminal to computer links is 19.2 kbit/s over conventional analog modems. With the DNIC, this can be increased up to 160 kbit/s at a very low cost per line for terminal to computer links and in many cases this bandwidth would be sufficient for computer to computer links. Figure 1 shows the block diagram of the MT8971B/ 72B. The DNIC provides a bidirectional interface between the DV (data/voice) port and a full duplex line operating at 80 or 160 kbit/s over a single pair of twisted wires. The DNIC has three serial ports. The DV port (DSTi/Di, DSTo/Do), the CD (control/data) port (CDSTi/CDi, CDSTo/CDo) and a line port (L IN, LOUT ). The data on the line is made up of information from the DV and CD ports. The DNIC must combine information received from both the DV and CD ports and put it onto the line. At the same time, the data received from the line must be split into the various channels and directed to the proper ports. The usable data rates are 72 and 144 kbit/s as required for the basic rate interface in ISDN. Full duplex transmission is made possible through on board adaptive echo cancellation. The DNIC has various modes of operation which are selected through the mode select pins MS0-2. The two major modes of operation are the MODEM (MOD) and DIGITAL NETWORK (DN) modes. MOD mode is a transparent 80 or 160 kbit/s modem. In DN mode the line carries the B and D channels formatted for the ISDN at either 80 or 160 kbit/s. In the DN mode the DV and CD ports are standard ST- BUS and in MOD mode they are transparent serial data streams at 80 or 160 kbit/s. Other modes include: MASTER (MAS) or SLAVE (SLV) mode, where the timebase and frame synchronization are provided externally or are extracted from the line and DUAL or SINGLE (SINGL) port modes, where both the DV and CD ports are active or where the CD port is inactive and all information is passed through the DV port. For a detailed description of the modes see “Operating Modes” section. In DIGITAL NETWORK (DN) mode there are three channels transferred by the DV and CD ports. They are the B, C and D channels. The B1 and B2 channels each have a bandwidth of 64 kbit/s and are used for carrying PCM encoded voice or data. These channels are always transmitted and received through the DV port (Figures 3, 4, 5, 6). The C- channel, having a bandwidth of 64 kbit/s, provides a means for the system to control the DNIC and for the DNIC to pass status information back to the system. The C-channel has a Housekeeping (HK) bit which is the only bit of the C-channel transmitted and received on the line. The 2B+D channel bits and the HK bit are double-buffered. The D-channel can be transmitted or received on the line with either an 8, 16 or 64 kbit/s bandwidth depending on the DNIC’s mode of operation. Both the HK bit and the D- channel can be used for end-to-end signalling or low speed data transfer. In DUAL port mode the C and D channels are accessed via the CD port (Figure 7) while in SINGL port mode they are transferred through the DV port (Figures 5, 6) along with the B1 and B2 channels.

subtracted from the precancelled received signal. comparator and passed to the biphase receiver. this new estimate is stored back in RAM. In MOD mode, all the ports have a different format. clocks for transmit and receive data, respectively. relationship to the data on the DV port. whether DN or MOD mode is used. Table 1. Mode Select Pins

SINGL port option only exists in DN mode. Table 2. Mode Definitions Table 3. Pin Configurations and the DV port transferring the B1& B2 channels. port is disabled and CDSTi should be pulled high. also at the baud rate and is synchronized to the CLD output.

2.048 Mbits/s and the line at 80 or 160 kbits/s configured according to the applicable ISDN

D-C D BEFORE C-CHANNEL - The D-channel is transferred before the C-channel following F0. C-D C BEFORE D-CHANNEL - The C-channel is transferred before the D-channel following F0. modes of operation DV and CD ports are enabled during the appropriate channel times.

written to the Diagnostics Register (Table 5). Table 4. Control Register -At 160 kbit/s full convergence requires 850 ms with ATTACK held high for the first 240 frames or 30 ms. -At 80 kbit/s full convergence requires 1.75 s with ATTACK held high for the first 480 frames or 60 ms. depending upon the status of bit-3. 0 Reg Sel-1 Register Select-1. Must be set to ’0’ to select the Control Register. 1 Reg Sel-2 Register Select-2. Must be set to ’0’ to select the Control Register. "1", the Diagnostics Register will not be reset. 3 BRS Bit Rate Select. When set to ’0’ selects 80 kbit/s. When set to ’1’, selects 160 kbit/s. timeslot on the line providing a 64 kbit/s D-channel link.

5 PSEN

canceller will require the normal amount of time to converge to a reflection coefficient.

➂ Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode. ➃ Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode. Table 5. Diagnostic Register depending upon the status of bit-3. ➁ Do not use LOUT to LIN loopback in DN/SLV mode. ➂ Do not use DSTo to DSTi loopback in MOD/MAS mode. PSEN, DINB, DRR and all diagnostics are disabled. PSEN, DINB, DRR and all diagnostics are disabled. 0 Reg Sel-1 Register Select-1. Must be set to ’0’ to select the Diagnostic Register. 1 Reg Sel-2 Register Select-2. Must be set to ’1’ to select the Diagnostic Register. 0 0 All loopback testing functions disabled. Normal operation. 0 1 DSTi internally looped back into DSTo for system diagnostics. recovery circuitry. When set to ’0’, the operation continues in synchronization.

5 PSWAP

’0’, LOUT pin functions normally. 7 Not Used Must be set to ’0’ for normal operation. positive going transition indicating a logic "1".

Table 6. Status Register

0 SYNC Synchronization - When set this bit indicates that synchronization to the received

line data sync pattern has been acquired. For DN mode only. noise. The farther this 2 bit value is from 0 the better the SNR. 3 Rx HK Housekeeping - This bit is the received housekeeping (HK) bit from the far end. 4-6 Future Future Functionality. These bits return Logic 1 when read. which are critical for adaptive echo cancellation. extraction at the receiving end. There is no D.C. B2 channels are transmitted.

Typical connection diagrams are shown in Figures 13 and 14 for the DN mode as a MASTER and SLAVE, respectively. L OUT is connected to the coupling transformer through a resistor R2 and capacitors C2 and C2’ to match the line characteristic impedance. Suggested values of R2, C2 and C2’ for 80 and 160 kbit/s operation are provided in Figures 13 and 14. Overvoltage protection is provided by R1, D1 and D2. C1 is present to properly bias the received line signal for the L IN input. A 2:1 coupling transformer is used to couple to the line with a secondary center tap for optional phantom power feed. Varistors have been shown for surge protection against such things as lightning strikes. If the scramblers power up with all zeros in them, they are not capable of randomizing all-zeros data sequence. This increases the correlation between the transmit and receive data which may cause loss of convergence in the echo canceller and high bit error rates. In DN mode the insertion of the SYNC pattern will provide enough pseudo-random activity to maintain convergence. In MOD mode the SYNC pattern is not inserted. For this reason, at least one ”1” must be fed into the DNIC on power up to ensure that the scramblers will randomize any subsequent all-zeros sequence. Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s DV Port ST-BUS CD Port ST-BUS Master Clocks Mode Select Lines +5V 0.33 µF 0.33 µF DSTi DSTo CDSTi CDSTo MS0 MS1 MS2 VRef VBias LOUT LIN OSC1 OSC2 F0o NC D.C. coupled, Frequency locked 10.24 MHz clock. R2 = 390Ω R1 = 47Ω C2’ = 1.5 nF C2 = 22 nF +5V D1 = D2 = MUR405 2 : 1 1.0 µF Line Feed Voltage For 80 kbit/s: C2’ = 3.3 nF C1 = 0.33 µF

68 Volts

(Typ)

2.5 Joules

0.02 Watt

Note: Low leakage diodes (1 & 2) are required so that the DC voltage at L IN ≈ VBias To Next DNIC MT8971B/72B Refer to AC Electrical Characteristics DN Mode Clock Timing DV Port ST-BUS CD Port ST-BUS Master Clocks Mode Select Lines +5V 0.33 µF 0.33 µF DSTi DSTo CDSTi CDSTo MS0 MS1 MS2 VRef VBias LOUT LIN OSC1 OSC2 R2 = 390Ω R1 = 47Ω C2’ = 1.5 nF C2 = 22 nF +5V D1 = D2 = MUR405 2:1 1.0 µF For 80 kbit/s: C2’ = 3.3 nF C1 = 0.33 µF (Typ) Note: Low leakage diodes (1 & 2) are required so that the DC voltage at LIN ≈ VBias

10.24 MHz XTAL

C3=33pF=C4 Supply MT8971B/72B

** Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. † Parameters over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. † Parameters over recommended temperature & power supply voltage ranges. Absolute Maximum Ratings** - Voltages are with respect to ground (VSS ) unless otherwise stated. Parameter Symbol Min Max Units 1 Supply Voltage V DD -0.3 7 V 2 Voltage on any pin (other than supply) V Max -0.3 V DD +0.3 V

3 Current on any pin (other than supply) I Max 40 mA

4 Storage Temperature T ST -65 +150 °C

5 Package Power Dissipation (Derate 16mW/°C above 75°C) PDiss 750 mW

Recommended Operating Conditions† - Voltages are with respect to ground (VSS ) unless otherwise stated. Characteristics Sym Min Typ* Max Units Test Conditions 1 Operating Supply Voltage V DD 4.75 5.00 5.25 V

2 Operating Temperature T OP -40 +85 °C

3 Input High Voltage (except OSC1) V IH 2.4 V DD V for 400 mV noise margin 4 Input Low Voltage (except OSC1) V IL 0 0.4 V for 400 mV noise margin Characteristics Sym Min Typ* Max Units Test Conditions O U T P U T S Operating Supply Current I DD 10 15 mA 2 Output High Voltage (ex OSC2) V OH 2.4 V I OH =10mA

3 Output High Current

(except OSC2) Output High Current - OSC2 IOH 10 15 mA Source current. V OH =2.4V 4 8 12 mA Source current. V OH =3.0V 5I OH 10 µA Source current VOH =3.5V 6 Output Low Voltage (ex OSC2) V OL 0.4 V I OL =5mA

7 Output Low Current

(except OSC2) Output Low Current - OSC2 IOL 5 7.5 mA Sink current. V OL =0.4V 8 20 30 mA Sink current. V OL =2.0V 9I OL 10 µA Sink current. VOL =1.5V 10 High Imped. Output Leakage I OZ 10 µAV IN=V SS to VDD

11 Output Voltage (V Ref)

(VBias) VO VBias-1.8 VDD /2 V V12 I N P U T S Input High Voltage (ex OSC1) VIH 2.0 V 14 Input Low Voltage (ex OSC1) V IL 0.8 V 15 Input High Voltage (OSC1) V IHo 4.0 V 16 Input Low Voltage (OSC1) V ILo 1.0 V

17 Input Leakage Current I IL 10 µAV IN=V SS to VDD

18 Input Pulldown Impedance

ZPD 50 k Ω

19 Input Leakage Current for

IIOSC 20 40 µA

† Timing is over recommended temperature & power supply voltages. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ➀ Duty cycle is measured at VDD /2 volts. † Timing is over recommended temperature & power supply voltages. * Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Notes: 1) When operating as a SLAVE the C4 clock has a 40% duty cycle. 2) When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e., FC =2.5xfC4 ). The relative phase between these two clocks (Φ in Fig. 17) is not critical and may vary from 0 ns to tC4P . However, the relative jitter must be less than JC (see Figure 17). Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams Characteristics Sym Min Typ* Max Units Test Conditions I N P U T S Input Voltage (L IN) VIN 5.0 V pp

2 Input Current (L IN)I IN -10 +10 µAf Baud=160 kHz

3 Input Impedance (L IN)Z IN 20 40 k Ω fBaud=160 kHz

4 Crystal/Clock Frequency f C 10.24 MHz

5 Crystal/Clock Tolerance T C -100 0 +100 ppm

6a Crystal/Clock Duty Cycle ➀ DC C 40 50 60 % Normal temp. & V DD 6b Crystal/Clock Duty Cycle ➀ DC C 45 50 55 % Recommended at max./ min. temp. & VDD 7 Crystal/Clock Loading C L 33 50 pF From OSC1 & OSC2 to V SS . 8 O U T P U T S Output Capacitance (L OUT )C o 8p F

9 Load Resistance (L OUT )

(VBias, VRef) R Lout 500 100 Ω kΩ

10 Load Capacitance (L OUT )

(VBias, VRef) C Lout 0.1 20 pF µF Capacitance to VBias. 11 Output Voltage (L OUT )V o 3.2 4.3 4.6 V pp R Lout = 500Ω , CLout = 20pF Characteristics Sym Min Typ* Max Units Test Conditions 1C 4 Clock Period t C4P 244 ns 2C 4 Clock Width High or Low t C4W 90 122 150 ns In Master Mode - Note 1

3 Frame Pulse Setup Time t F0S 50 ns

4 Frame Pulse Hold Time t F0H 50 ns

5 Frame Pulse Width t F0W 172 244 ns

6 10.24 MHz Clock Jitter (wrt C4)J C -15 +15 ns Note 2 Channel 31 Bit 0 Channel 0 Bit 7 Channel 0 Bit 6 F0b ST-BUS BIT CELLS

Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode † Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Figure 18 - RCK, TCK & CLD Timing For MOD Mode Characteristics Sym 80 kbit/s 160 kbit/s Units Test ConditionsMin Typ* Max Min Typ* Max 1T C K/RCK Clock Period t CP 12.5 6.25 µs 2 TCK /RCK Clock Width tCW 6.25 3.125 µs

3 TCK /RCK Clock Transition TimetCT 20 20 ns C L=40pF

4C L D to TCK Setup Time tCLDS 3.125 1.56 µs 5C L D to TCK Hold Time tCLDH 3.125 1.56 µs 6C L D Width Low tCLDW 6.05 2.925 µs 7C L D Period tCLDP 8xtCP 8xtCP µs 2.0V 0.8V 2.0V 0.8V tC4P tC4WtF0S tF0H tF0W tC4W OSC1 2.0V 0.8V 3.0V 2.0V JC Φ RCK TCK CLD tCT tCP tCLDS tCLDH tCW tCT tCLDW tCW 2.4V 0.4V 2.4V 0.4V 2.4V 0.4V tCP Note 1: TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the DV port. RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the Do output and may be skewed with respect to TCK due to end-to-end delay. Note 2: At the slave end TCK is phase locked to RCK. The rising edge of TCK will lead the rising edge of RCK by approximately 90o.

† Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Figure 19 - Data Timing For DN Mode † Timing is over recommended temperature & power supply voltage ranges. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Note 1: Attenuation measured from Master L OUT to Slave LIN at 3/4baud frequency. * Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing. Characteristics Sym Min Typ* Max Units Test Conditions

1 DSTi/CDSTi Data Setup Time t RS 30 ns

2 DSTi/CDSTi Data Hold Time t RH 50 ns

3a DSTo/CDSTo Data Delay t TD 120 ns C L=40pF 3b DSTo/CDSTo High Z to Data Delay t ZTD 100 140 ns C L=40pF Characteristics Sym 80 kbit/s 160 kbit/s Units Test ConditionsMin Typ* Max Min Typ* Max

1 Di/CDi Data Setup Time t DS 150 150 ns

2 Di/CDi Data Hold Time t DH 4.5 2.5 µs

3 Do Data Delay Time t RD 100 100 ns C L=40pF

4 CDo Data Delay Time t TD 100 100 ns C L=40pF

Performance Characteristics of the MT8971B DSIC Characteristics Sym Min Typ* Max Units Test Conditions

1 Allowable Attenuation for Bit Error

Rate of 10-6 (Note 1) Afb 03 02 5 d B S N R ≥16.5dB (300kHz bandlimited noise)

2 Line Length at 80 kbit/s -24 AWG

-26 AWG L80 3.0 2.2 km attenuation - 6.9 dB/km attenuation - 10.0 dB/km

3 Line Length at 160 kbit/s -24 AWG

-26 AWG L160 3.0 2.2 km attenuation - 8.0 dB/km attenuation - 11.5 dB/km Performance Characteristics of the MT8972B DNIC Characteristics Sym Min Typ* Max Units Test Conditions Rate of 10-6 (Note 1) Afb 04 03 3 d B S N R ≥16.5dB (300kHz bandlimited noise) -26 AWG L80 5.0 3.4 km attenuation - 6.9 dB/km attenuation - 10.0 dB/km -26 AWG L160 4.0 3.0 km attenuation - 8.0 dB/km attenuation - 11.5 dB/km 2.0V 0.8V 2.4V 0.4V 2.0V 0.8V Bit Stream DSTi CDSTi DSTo CDSTo Bit Cell tTD tRS tRH tTDtZTD

Figure 20 - Data Timing For Master Modem Mode Tx Bit Stream TCK Di CDI CDo Rx Bit Stream Do 2.4V 0.4V 2.0V 0.8V 2.4V 0.4V 2.4V 0.4V Bit Cell tDS tDH tTDtTD tRD tRD Bit Cell RCK

Figure 21 - Data Timing for Slave Modem Mode TCK Di CDI CDo Do 2.4V 0.4V 2.0V 0.8V 2.4V 0.4V 2.4V 0.4V tDS tDH tTDtTD RCK ¼ tCP